Driving method of pixel circuit and display device

Abstract

This invention discloses a driving method for a pixel circuit and a display device. The pixel circuit includes a current driving module, which generates a driving current during the light-emitting phase to drive a light-emitting device to emit light. The light-emitting time of the light-emitting device within one frame is controlled by a ramp signal. The driving method includes: the light-emitting phase comprising at least two sub-light-emitting phases; and in each sub-light-emitting phase, the voltage of the ramp signal changes in a ramp-like manner to adjust the light-emitting time of the light-emitting device in each sub-light-emitting phase. Compared with the prior art, this invention improves the switching speed of the light-emitting device from a bright state to a dark state, thus improving the display effect.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a driving method of a pixel circuit and a display device. BACKGROUND

[0002] With the continuous development of display technology, the application range of display panels is more and more extensive, and people's requirements for display panels are also higher and higher. Especially the display quality of display panels is always one of the important indicators for consumers and panel manufacturers to measure the quality of display panels. The display panel includes a light emitting device and a pixel circuit for driving the light emitting device, and the performance of the pixel circuit determines the light emitting effect of the light emitting device, and further determines the display effect of the display panel.

[0003] In the prior art, there are various structural forms of pixel circuits, one of which adopts a comparison between a ramp signal and a data signal to confirm the light emitting time of the light emitting device, and further control the gray scale of the light emitting device. Among them, the switching speed of the light emitting device from bright state to dark state is too slow, which leads to the problem of gray scale switching display (for example, color deviation), which is particularly serious when low gray scale display is performed. SUMMARY

[0004] Embodiments of the present application provide a driving method of a pixel circuit and a display device to improve the switching speed of the light emitting device from bright state to dark state and improve the display effect.

[0005] To achieve the above technical purpose, embodiments of the present application provide the following technical solutions:

[0006] A driving method of a pixel circuit, the pixel circuit comprising a current driving module, the current driving module generating a driving current to drive a light emitting device to emit light in a light emitting phase;

[0007] The light emitting time of the light emitting device in a frame is controlled by a ramp signal; the driving method comprises:

[0008] The light emitting phase comprises at least two sub-light emitting phases; in each of the sub-light emitting phases, the voltage of the ramp signal changes in a ramp shape to respectively adjust the light emitting time of the light emitting device in each of the sub-light emitting phases.

[0009] Optionally, in each of the sub-light emitting phases, the ramp signal changes from a first voltage to a second voltage;

[0010] Preferably, in each of the sub-light emitting phases, the slope of the ramp signal is the same.

[0011] Optionally, the pixel circuit further comprises a time driving module, and the slope signal controls the light emitting time of the current driving module by controlling the working state of the time driving module.

[0012] The current driving module comprises a first driving transistor, and the driving current is generated by the first driving transistor in response to the gate voltage thereof; and the time driving module controls the time when the current driving module generates the driving current by controlling the gate of the first driving transistor.

[0013] Optionally, between adjacent sub-light emitting stages, further comprising:

[0014] a sub-data resetting stage, in which the gate of the first driving transistor in the current driving module is data reset;

[0015] Preferably, the current driving module has a threshold voltage compensation function, and the sub-data resetting stage comprises:

[0016] a sub-initializing stage, in which the gate of the first driving transistor is initialized;

[0017] a sub-data writing stage, in which the gate of the first driving transistor is data written.

[0018] Optionally, the pixel circuit further comprises a time driving module, and the slope signal controls the light emitting time of the current driving module by controlling the working state of the time driving module.

[0019] The current driving module comprises a first driving transistor, and the driving current is generated by the first driving transistor in response to the gate voltage thereof; and the time driving module controls the time when the current driving module generates the driving current by controlling the current flow path of the first driving transistor.

[0020] Optionally, the data voltage written into the current driving module is an amplitude data voltage, and the data voltage written into the time driving module is a time data voltage.

[0021] The driving method is digital driving; accordingly, the amplitude data voltage is a constant voltage value, and the time data voltage is adjustable.

[0022] Alternatively, the driving method is digital-analog hybrid driving; accordingly, both the amplitude data voltage and the time data voltage are adjustable.

[0023] Optionally, if the driving method is digital driving, before the light emitting stage, further comprising:

[0024] a time data writing stage, in which the time data voltage is written into the time driving module row by row.

[0025] a magnitude data writing stage, in which the magnitude data voltages are written into all the current driving modules simultaneously;

[0026] Preferably, the magnitude data writing stage is performed simultaneously with the time data writing stage.

[0027] Optionally, the current driving module has a threshold voltage compensation function, and before the magnitude data writing stage, the current driving module further comprises:

[0028] a current driving initialization stage, in which all the current driving modules are initialized simultaneously;

[0029] Optionally, the time driving module has a threshold voltage compensation function, and during the time data writing stage, while the time data voltages are written into the time driving modules of the current row, the time driving modules of the next row are initialized;

[0030] Preferably, the current driving initialization stage is performed before the time data writing stage, and the magnitude data writing stage is performed after the time data writing stage.

[0031] Alternatively, the current driving initialization stage and the magnitude data writing stage are both performed simultaneously with the time data writing stage.

[0032] Alternatively, the current driving initialization stage and the magnitude data writing stage are both performed before the time data writing stage.

[0033] Alternatively, the current driving initialization stage and the magnitude data writing stage are both performed after the time data writing stage.

[0034] Optionally, if the driving method is a digital-analog hybrid driving method, before the light emitting stage, the method further comprises:

[0035] a time data writing stage, in which the time data voltages are written into the time driving modules row by row;

[0036] a magnitude data writing stage, in which the magnitude data voltages are written into the current driving modules row by row;

[0037] Preferably, the magnitude data writing stage is performed simultaneously with the time data writing stage.

[0038] Correspondingly, the application further provides a display device, comprising a control chip and a display panel, the display panel is provided with pixel circuits arranged in an array, and the control chip drives the pixel circuits by using the driving method of the pixel circuit according to any embodiment of the application.

[0039] The embodiment of the present application controls the light-emitting stage of the pixel circuit to include at least two sub-light-emitting stages, and the voltage of the ramp signal changes in a ramp manner in each sub-light-emitting stage to respectively adjust the light-emitting time of the light-emitting device in each sub-light-emitting stage, so that the inclination of the ramp signal is greater than that in the prior art. That is, the embodiment of the present application can change the voltage of the ramp signal in a shorter time, and therefore, the embodiment of the present application can accelerate the switching speed of the light-emitting device from the bright state to the dark state. In addition, the embodiment of the present application does not need to change the structure of the pixel circuit, does not need to increase the number of external driving signals, and does not need to change the preparation process of the transistor. By only adjusting the timing of the external driving signal of the pixel circuit, the bright-dark switching speed of the light-emitting device can be improved, the gray scale switching display problem can be improved, and the improvement effect is better when low gray scale display is performed. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A driving timing diagram of a current driving module in the prior art is shown;

[0041] Figure 2 A driving timing diagram of a current driving module provided by the embodiment of the present application is shown;

[0042] Figure 3 A comparison result diagram of the driving timing diagram of the current driving module provided by the embodiment of the present application and the driving timing diagram of the current driving module in the prior art is shown;

[0043] Figure 4 A structure diagram of a pixel circuit provided by the embodiment of the present application is shown;

[0044] Figure 5 A driving timing diagram of a pixel circuit provided by the embodiment of the present application is shown;

[0045] Figure 6 A structure diagram of a display panel provided by the embodiment of the present application is shown;

[0046] Figure 7 A timing diagram of another driving method of a pixel circuit provided by the embodiment of the present application is shown;

[0047] Figure 8 A timing diagram of another driving method of a pixel circuit provided by the embodiment of the present application is shown;

[0048] Figure 9 A timing diagram of another driving method of a pixel circuit provided by the embodiment of the present application is shown;

[0049] Figure 10 A timing diagram of another driving method of a pixel circuit provided by the embodiment of the present application is shown;

[0050] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0051] Figure 12 A timing diagram illustrating another driving method for a pixel circuit provided in an embodiment of the present invention;

[0052] Figure 13 A timing diagram illustrating another driving method for a pixel circuit provided in an embodiment of the present invention;

[0053] Figure 14 A timing diagram illustrating another driving method for a pixel circuit provided in an embodiment of the present invention;

[0054] Figure 15 A timing diagram illustrating another driving method for a pixel circuit provided in an embodiment of the present invention;

[0055] Figure 16 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0056] Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0057] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0058] As described in the background section, for pixel circuits that use ramp signals to control the emission time of light-emitting devices, there is a problem during the driving process: the switching speed of the light-emitting device from a bright state to a dark state is too slow. The inventors have discovered the cause of this problem as follows:

[0059] The pixel circuit includes a current driving module, which generates a driving current during the light emission phase to drive the light-emitting device to emit light. The duration of light emission driven by the current driving module within one frame is controlled by a ramp signal.

[0060] Figure 1 This is a schematic diagram of the driving timing of an existing current-driven module. See also... Figure 1In the light-emitting stage t3 of the pixel circuit, the voltage of the ramp signal Vsweep starts to decrease from V1, and the current control module generates a stable driving current Id1 before the voltage of the ramp signal Vsweep decreases to V01. When the voltage of the ramp signal Vsweep decreases to V01, the transistor in the current control module enters a sub-threshold state, the leakage current is large, the driving current Id1 gradually decreases, and until the voltage of the ramp signal Vsweep decreases to V02, the current control module is in a completely off state and no longer generates a driving current.

[0061] It can be seen that the light-emitting stage includes a light-emitting time (bright state time) and a non-light-emitting time (dark state time) of the light-emitting device, and the switching between the bright state and the dark state is controlled by the ramp signal Vsweep. The voltage of the ramp signal Vsweep changes from V01 to V02, the voltage change amount is ΔV, and the duration is Δt1, which is the switching time of the light-emitting device from the bright state to the dark state. Specifically, the pixel circuit is mainly composed of transistors, and it is generally believed that the switching time of the light-emitting device from the bright state to the dark state is determined by the sub-threshold characteristics of the transistor, and the sub-threshold characteristics of the transistor are determined by the transistor process. Therefore, in the prior art, if the switching time from the bright state to the dark state is to be shortened, the preparation process of the transistor needs to be improved, which has a high cost and poor improvement effect, and has poor practicability. If a general preparation process is used, there is a problem of slow switching speed of the light-emitting device from the bright state to the dark state, and further improvement cannot be achieved.

[0062] The inventors believe that if the switching time of the light-emitting device from the bright state to the dark state is shortened, it is beneficial to realize more accurate display control, and therefore the inventors have further researched this technical problem. It is found that the switching speed from the bright state to the dark state can be improved by increasing the slope of the ramp signal Vsweep. Specifically, Figure 2 A driving timing diagram of a current driving module provided for an embodiment of the present application is shown. Referring to Figure 2 , the light-emitting stage t3 includes at least two sub-light-emitting stages t31; in each sub-light-emitting stage t31, the voltage of the ramp signal Vsweep changes in a ramp shape to adjust the light-emitting time of the light-emitting device in each sub-light-emitting stage t31.

[0063] Figure 3 A driving timing diagram of a current driving module provided for an embodiment of the present application is shown. Referring to Figure 3The slope of the ramp signal Vsweep provided in this embodiment of the invention is greater than that of the ramp signal Vsweep in the prior art. This embodiment of the invention can change the voltage ΔV of the ramp signal Vsweep in a shorter time; therefore, it can accelerate the switching speed of the light-emitting device from a bright state to a dark state. Furthermore, this embodiment of the invention does not require changing the structure of the pixel circuit, increasing the number of external driving signals, or altering the transistor fabrication process. It only requires adjusting the timing of the external driving signals of the pixel circuit to improve the bright-dark switching speed of the light-emitting device, thereby improving the grayscale switching display problem, and the improvement effect is even better when performing low grayscale displays.

[0064] The above is the core inventive concept of this invention. The following description, in conjunction with specific pixel circuits, illustrates the embodiments of this invention, but is not intended to limit the scope of this invention.

[0065] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 4The pixel circuit includes a current driving module 110 and a time driving module 120. The current driving module 110, also known as the PAM driving module, generates a driving current Id1 under the control of the amplitude data voltage DataA. For example, the current driving module 110 has a threshold compensation function and includes a first driving transistor DT1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. The first driving transistor DT1 constitutes the driving unit of the current driving module 110. The first driving transistor DT1 generates a driving current Id1 in response to its gate voltage to drive the LED to emit light. The second transistor T2 and the third transistor T3 constitute the light-emitting control unit of the current driving module 110. The gate of the second transistor T2 is connected to the light-emitting control signal EM, the first terminal of the second transistor T2 is connected to the first power supply signal VDDA, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the first driving transistor DT1. The gate of the third transistor T3 is connected to the light-emitting control signal EM. The first terminal of the third transistor T3 is electrically connected to the second terminal of the first driving transistor DT1. The second terminal of the third transistor T3 is electrically connected to the anode of the light-emitting device LED. The cathode of the light-emitting device LED is connected to the second power supply signal VSS. The fourth transistor T4 constitutes the initialization unit of the current driving module 110. The gate of the fourth transistor T4 is connected to the first scan signal S1A. The first terminal of the fourth transistor T4 is connected to the first initialization signal Vinit1. The second terminal of the fourth transistor T4 is electrically connected to the gate of the first driving transistor DT1. The fifth transistor T5 and the sixth transistor T6 constitute the data writing unit of the current driving module 110. The gate of the fifth transistor T5 is connected to the second scan signal S2A. The first terminal of the fifth transistor T5 is connected to the amplitude data voltage DataA. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the first driving transistor DT1. The gate of the sixth transistor T6 is connected to the second scan signal S2A. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the first driving transistor DT1. The second terminal of the sixth transistor T6 is electrically connected to the gate of the first driving transistor DT1. The first capacitor C1 serves as the storage unit of the current drive module 110. The first terminal of the first capacitor C1 is connected to the first power supply signal VDDA, and the second terminal of the first capacitor C1 is electrically connected to the gate of the first drive transistor DT1.

[0066] The time-driven module 120, also known as a PWM drive module, generates a pulse width signal under the control of the time data voltage DataW and the ramp signal Vsweep, thereby controlling the generation time of the drive current Id1 to control the light-emitting time of the LED. For example, the time-driven module 120 has a threshold compensation function and includes: a second drive transistor DT7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a second capacitor C2. The second drive transistor DT7 constitutes the drive unit of the time-driven module 120. The eighth transistor T8 and the ninth transistor T9 constitute the light-emitting control unit of the time-driven module 120. The gate of the eighth transistor T8 is connected to the light-emitting control signal EM, the first terminal of the eighth transistor T8 is connected to the third power supply signal VDDW, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal of the second drive transistor DT7. The gate of the ninth transistor T9 is connected to the light-emitting control signal EM, the first terminal of the ninth transistor T9 is electrically connected to the second terminal of the second drive transistor DT7, and the second terminal of the ninth transistor T9 is electrically connected to the gate of the first drive transistor DT1. The tenth transistor T10 constitutes the initialization unit of the time drive module 120. The gate of the tenth transistor T10 is connected to the third scan signal S1W, the first terminal of the tenth transistor T10 is connected to the second initialization signal Vinit2, and the second terminal of the tenth transistor T10 is electrically connected to the gate of the second driving transistor DT7. The eleventh transistor T11 and the twelfth transistor T12 constitute the data writing unit of the time drive module 120. The gate of the eleventh transistor T11 is connected to the fourth scan signal S2W, the first terminal of the eleventh transistor T11 is connected to the time data voltage DataW, and the second terminal of the eleventh transistor T11 is electrically connected to the first terminal of the second driving transistor DT7. The gate of the twelfth transistor T12 is connected to the fourth scan signal S2W, and the first terminal of the twelfth transistor T12 is electrically connected to the second terminal of the second driving transistor DT7. The second capacitor C2 serves as the coupling unit of the time drive module 120. The first terminal of the second capacitor C2 is connected to the ramp signal Vsweep, and the second terminal of the second capacitor C2 is electrically connected to the gate of the second driving transistor DT7.

[0067] The ramp signal Vsweep can be considered as the time switch signal of the time drive module 120, and the time drive module 120 can be considered as the control switch of the current drive module 110. Therefore, the light emission time of the LED driven by the current drive module 110 within one frame is controlled by the ramp signal Vsweep.

[0068] See also Figure 4Optionally, the pixel circuit also includes a thirteenth transistor T13, which serves as the discharge unit for the LED. The gate of the thirteenth transistor T13 is connected to the fifth scan signal S5, the first terminal of the thirteenth transistor T13 is electrically connected to the cathode of the LED, and the second terminal of the thirteenth transistor T13 is electrically connected to the anode of the LED.

[0069] Figure 5 This is a schematic diagram illustrating the driving timing of a pixel circuit according to an embodiment of the present invention. (In conjunction with...) Figure 4 and Figure 5 The driving method provided in this embodiment of the invention will be described using the driving process of a pixel circuit as an example. The driving method includes: a current driving initialization stage t011, a time driving initialization stage t021, a time data writing stage t022, an amplitude data writing stage t012, and an emission stage t03.

[0070] During the current-driven initialization phase t011, the first scan signal S1A is low, the fourth transistor T4 is turned on, and the first initialization signal Vinit1 is written to the gate of the first driving transistor DT1, thus initializing the first driving transistor DT1. This initialization of the first driving transistor DT1 ensures that it remains on during the subsequent amplitude data writing phase t012, allowing the amplitude data signal DataA to be written to the gate of the first driving transistor DT1.

[0071] During the time-driven initialization phase t021, the third scan signal S1W is low, the tenth transistor T10 is turned on, and the second initialization signal Vinit2 is written to the gate of the second driving transistor DT7, thus initializing the second driving transistor DT7. This initialization of the second driving transistor DT7 ensures that it remains on during the subsequent time data writing phase t022, allowing the time data signal DataW to be written to its gate.

[0072] During the time data writing stage t022, the fourth scan signal S2W is at a low level, and the eleventh transistor T11 and the twelfth transistor T12 are turned on. The time data signal DataW is written to the gate of the second driving transistor DT7 through the turned-on eleventh transistor T11, the second driving transistor DT7, and the twelfth transistor T12. The specific writing value is DataW + Vth7, where Vth7 is the threshold voltage of the second driving transistor DT7.

[0073] During the amplitude data writing stage t012, the second scan signal S2A is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the amplitude data signal DataA is written to the gate of the first driving transistor DT1 through the turned-on fifth transistor T5, the first driving transistor DT1 and the sixth transistor T6. The specific written value is DataA+Vth1, where Vth1 is the threshold voltage of the first driving transistor DT1.

[0074] In the light-emitting stage t03, there are two sub-light-emitting stages t031, which respectively adjust the light-emitting time of the LED in each sub-light-emitting stage t031. In the sub-light-emitting stage t031, the voltage of the ramp signal Vsweep changes in a ramp shape. Compared with the light-emitting stage t03 without sub-light-emitting stages t031, the slope of the ramp signal Vsweep is larger, and the voltage of the ramp signal Vsweep gradually decreases from V1 to V2 at a faster rate. Taking the first sub-light-emitting stage t031 as an example, the light-emitting control signal EM is at a low level, and the second transistor T2, the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are turned on. Among them, the second transistor T2 and the third transistor T3 are turned on, and the path of the driving current Id1 is turned on. When the LED emits light, the first driving transistor DT1 generates the driving current Id1.

[0075]

[0076] In the formula, W1 is the channel width of the first driving transistor DT1, L1 is the channel length, and μ eff1 For electron mobility, C ox1 This represents the channel capacitance per unit area. Therefore, this embodiment of the invention achieves threshold voltage compensation for the first driving transistor DT1.

[0077] In the time-driven module 120, the eighth transistor T8 and the ninth transistor T9 are turned on, making it possible for the third power supply signal VDDW to conduct between the gate of the first driving transistor DT1. However, unlike the amplitude data signal DataA, which controls the first driving transistor DT1 to turn on, the time data signal DataW controls the second driving transistor DT7 to turn off. Therefore, at the beginning of the sub-light emission stage t031, the second driving transistor DT7 is in the off state, and the first driving transistor DT1 generates a driving current Id1 under the control of the amplitude data signal DataA.

[0078] Simultaneously, the voltage of the ramp signal Vsweep gradually decreases from V1. Due to the coupling effect of the second capacitor C2, the gate voltage of the second driving transistor DT7 gradually decreases from DataW+Vth7 until the gate voltage of the second driving transistor DT7 drops to VDDW+Vth7, at which point the second driving transistor DT7 begins to switch to the conducting state. The change in the gate voltage of the second driving transistor DT7 is DataW-VDDW, eliminating the influence of the threshold voltage of the second driving transistor DT7. Correspondingly, the voltage of the ramp signal Vsweep decreases from V1 to V3 (exemplarily, V3 is between V01 and V02), where V3 = V1 - (DataW - VDDW). Here, V01 is defined as the voltage of the ramp signal Vsweep when the second driving transistor DT7 begins to switch to the conducting state, and V02 is defined as the voltage of the ramp signal Vsweep when the second driving transistor DT7 is fully turned on. Ideally, when the voltage of the ramp signal Vsweep drops to V3, the second driving transistor DT7 switches to a fully conducting state, and the third power supply signal VDDW is written into the gate of the first driving transistor DT1, controlling the first driving transistor DT1 to turn off, and the LED switches from a bright state to a dark state. However, as the voltage of the ramp signal Vsweep decreases from V1 to V3, the voltage of Vsweep changes gradually, that is, the gate voltage of the second driving transistor DT7 gradually decreases from DataW+Vth7 to VDDW+Vth7. Due to the subthreshold characteristic of the second driving transistor DT7 (the interval defined by voltages V01 and V02 is the subthreshold region), before the second driving transistor DT7 is fully turned on, it enters the subthreshold region, resulting in a large leakage current. The presence of this leakage current causes the gate voltage of the first driving transistor DT1 to change gradually.

[0079] In this embodiment of the invention, by setting the light-emitting stage t03 to include at least two sub-light-emitting stages t031, the slope of the ramp signal Vsweep is increased, thereby shortening the time for the second driving transistor DT7 to enter the subthreshold region, and thus reducing the switching time of the light-emitting device LED from the bright state to the dark state, thereby improving the display effect of the display panel.

[0080] See also Figure 5 Based on the above embodiments, optionally, the driving method of the pixel circuit further includes a discharge stage t04. In the discharge stage t04, the fifth scan signal S5 is at a low level, the thirteenth transistor T13 is turned on, and the second power supply signal VSS is written into the anode of the light-emitting device LED, causing the light-emitting device LED to discharge, which helps to alleviate the voltage bias problem of the light-emitting device LED.

[0081] See also Figure 5Based on the above embodiments, optionally, in each sub-light-emitting stage t031, the ramp signal Vsweep changes from the first voltage V1 to the second voltage V2. Wherein, assuming the time data signal DataW remains unchanged, regardless of how the duration of each sub-light-emitting stage t031 changes, as long as the ramp signal Vsweep changes from the first voltage V1 to the second voltage V2, the ratio of the on-time to the off-time of the second driving transistor DT7 can be ensured to be equal, thereby ensuring that the light-emitting time of the LED device matches the time data signal DataW.

[0082] Based on the above embodiments, optionally, the first voltage V1 and the second voltage V2 are set to the same voltages as in the prior art. Therefore, the time data signal DataW can also adopt the values ​​in the prior art, so there is no need to recalculate the correspondence between the time data signal DataW and the grayscale of the LED display, which is beneficial to saving R&D costs.

[0083] See also Figure 5 Based on the above embodiments, optionally, the slope of the ramp signal Vsweep is the same in each sub-light-emitting stage t031. This setting ensures that the light-emitting time of the LED in each sub-light-emitting stage t031 is equal, and the switching time from bright to dark is equal, thereby improving the uniformity of the LED's brightness in each sub-light-emitting stage t031. Furthermore, this ramp signal Vsweep is easy to generate and implement.

[0084] See also Figure 5 Based on the above embodiments, optionally, a sub-data reset stage t032 is included between adjacent sub-light emission stages t031. In the sub-data reset stage t032, the gate of the first driving transistor DT1 in the current driving module 110 is reset. Specifically, at the end of the first sub-light emission stage t031, the gate voltage of the first driving transistor DT1 increases, making it impossible to drive the first driving transistor DT1 to generate the driving current Id1. This embodiment of the invention, through data reset, ensures that at the start of the next sub-light emission stage t031, the gate voltage of the first driving transistor DT1 recovers to the same voltage value as at the start of the first sub-light emission stage t031, thus ensuring that the LED emits light normally in the next sub-light emission stage t031.

[0085] See also Figure 5 Based on the above embodiments, the current drive module 110 optionally has a threshold voltage compensation function, and the sub-data reset stage t032 includes: sub-initialization stage tA and sub-data writing stage tB.

[0086] During the sub-initialization phase tA, the gate of the first driving transistor DT1 is initialized. For example, in conjunction with... Figure 4 and Figure 5 After the previous sub-light emission stage t031 ends, the gate voltage of the first driving transistor DT1 is high, and the first driving transistor DT1 is in the off state. Therefore, the first driving transistor DT1 needs to be initialized to ensure that the amplitude data signal DataA can be written to the gate of the first driving transistor DT1 during the sub-data writing stage tB. Specifically, the first scan signal S1A is at a low level, the fourth transistor T4 is turned on, and the lower voltage first initialization signal Vinit1 is written to the gate of the first driving transistor DT1 to initialize the first driving transistor DT1.

[0087] In the sub-data write stage tB, data is written to the gate of the first driving transistor DT1. For example, combined with... Figure 4 and Figure 5 Because the gate voltage of the first driving transistor DT1 is low, DT1 is turned on when the amplitude data signal DataA is written to its first terminal. Specifically, when the second scan signal S2A is low, the fifth transistor T5 and the sixth transistor T6 are turned on. The amplitude data signal DataA is written to the gate of the first driving transistor DT1 through the turned-on fifth transistor T5, the first driving transistor DT1, and the sixth transistor T6, with the written value being DataA + Vth1. Vth1 is eliminated in the calculation formula of the driving current Id1, thus achieving threshold voltage compensation for the first driving transistor DT1.

[0088] In the above embodiments, the driving methods are divided into digital driving and hybrid analog-digital driving, depending on the different ways in which the amplitude data voltage DataA and the time data voltage DataW are set. Specifically, if the driving method is digital driving, the amplitude data voltage DataA is a constant voltage value, while the time data voltage DataW is adjustable. That is, the driving current Id1 generated by the current driving module 110 remains constant, and the grayscale is adjusted only by adjusting the light-emitting time of the light-emitting device LED. If the driving method is hybrid analog-digital driving, both the amplitude data voltage DataA and the time data voltage DataW are adjustable. That is, the driving current Id1 generated by the current driving module 110 is adjustable, meaning that the grayscale can be adjusted by adjusting the light-emitting time of the light-emitting device LED, and also by adjusting the light-emitting brightness of the light-emitting device LED.

[0089] In the above embodiments, the driving method for a single pixel circuit has been described. The following describes the driving method for all pixel circuits in the display panel provided by the embodiments of the present invention.

[0090] Figure 6 This is a schematic diagram of a display panel provided in an embodiment of the present invention. See also... Figure 6 For example, the display panel includes pixel circuits 1 arranged in an array (m rows and n columns) and light-emitting devices connected to the pixel circuits 1. The pixel circuits 1 can be of any form, employing a ramp signal to control the emission time of the light-emitting devices. For example, the structure of the pixel circuits 1 is as follows: Figure 4 As shown.

[0091] Figure 7 This is a timing diagram illustrating another pixel circuit driving method provided in an embodiment of the present invention. (In conjunction with...) Figure 6 and Figure 7 In one embodiment of the present invention, optionally, the driving method is digital driving. The driving method includes a light emission stage t13, which includes at least two sub-light emission stages t131. Before the light emission stage t13, it further includes a time data writing stage t120 and an amplitude data writing stage t112.

[0092] During the time data writing stage t120, the time data voltage is written to the time drive module line by line. Since the time data voltage is adjustable in digital driving, the time data voltage corresponding to each pixel circuit may be different. Therefore, a line-by-line writing method is required to write the time data voltage to each time drive module separately. At this time, the third scan signal S1W corresponding to each line of the time drive module is shifted line by line, and the fourth scan signal S2W is shifted line by line.

[0093] Optionally, such as Figure 4 and Figure 6 As shown, the time-driven module 120 has a threshold voltage compensation function. Therefore, the driving method of the time-driven module 120 includes: the initialization process of the time-driven module 120 (refer to...). Figure 5 The time-driven initialization phase t021 and the process of writing the time data voltage DataW into the time-driven module 120 (see reference). Figure 5 In the time data writing phase t022, to simplify the driving timing, in this embodiment of the invention, during the execution of the time data writing phase t120, while writing the time data voltage DataW to the current row of time driving modules 120, the next row of time driving modules 120 is initialized. Specifically, while the first row of time driving modules 120 is executing the time data writing phase, the second row of time driving modules 120 is executing the time driving initialization phase; while the second row of time driving modules 120 is executing the time data writing phase, the third row of time driving modules 120 is executing the time driving initialization phase; and so on, until all the time data voltage DataW of the m rows of time driving modules 120 has been written.

[0094] The driving process of the time-driven module 120 is controlled by the third scan signal S1W and the fourth scan signal S2W. Combined with... Figure 6 The third scan signal S1W and the fourth scan signal S2W use the same scan driving circuit 2. The scan driving circuit 2 includes multiple cascaded shift registers 20, each shift register 20 shifting and outputting a scan signal. For example, the output signal of the first shift register 20 serves as the third scan signal S1W of the first row pixel circuit 1, and the output signal of the second shift register 20 serves as the fourth scan signal S2W of the first row pixel circuit 1. The output signal of the second shift register 20 is shifted backward by one clock cycle compared to the low level of the output signal of the first shift register 20; correspondingly, the fourth scan signal S2W corresponding to the first row pixel circuit 1 is shifted backward by one clock cycle compared to the low level of the third scan signal S1W. When the third scan signal S1W is low, the initialization phase of the time driving module 120 is executed; when the fourth scan signal S2W is low, the data writing phase of the time driving module 120 is executed. The specific execution process is described in the aforementioned embodiment and will not be repeated here. Furthermore, the output signal of the second shift register 20 is also used as the third scan signal S1W of the second row pixel circuit 1, so that while the first row time drive module 120 performs the data writing stage, the second row time drive module 120 performs the initialization stage.

[0095] During the amplitude data writing stage t112, the amplitude data voltage DataA is simultaneously written to the m-row current drive module 110. Since the amplitude data voltage DataA is a constant value in digital driving, and the value of the amplitude data voltage DataA corresponding to each pixel circuit is equal, the amplitude data voltage DataA can be written to the m-row current drive module 110 simultaneously. At this time, each row current drive module 110 corresponds to the same second scan signal S2A, which can be provided by the driver chip 3 without the need for a scan drive circuit.

[0096] Therefore, it can be seen that the driving timing of the digital driving method is simple, and there is no need to write the amplitude data signal line by line into the current driving module 110. Correspondingly, in the sub-data reset stage of the light emission stage t13, the amplitude data signal can also be written into all current driving modules 110 at the same time, which takes less time and is beneficial to improving the refresh rate of the display panel.

[0097] In another embodiment of the present invention, optionally, the amplitude data writing stage t112 and the time data writing stage t120 are executed simultaneously. As can be seen from the foregoing analysis, the amplitude data writing stage t112 has a shorter time, and the amplitude data writing stage t112 can be incorporated into the time data writing stage t120 to further reduce the driving time and improve the refresh rate of the display panel.

[0098] Combination Figure 6 and Figure 7 Based on the above embodiments, optionally, the current driving module 110 has a threshold voltage compensation function. Before the amplitude data writing stage t112, a current driving initialization stage t111 is also included. During the current driving initialization stage t111, the m-row current driving modules 110 are simultaneously initialized. The driving process of the current driving module 110 is controlled by a first scan signal S1A and a second scan signal S2A. Since all current driving modules 110 in the display panel can share a single first scan signal S1A and a single second scan signal S2A, the first scan signal S1A and the second scan signal S2A can be provided by the driving chip, eliminating the need for a scanning driving circuit.

[0099] In the above embodiments, the execution order of the current-driven initialization phase t111, the amplitude data writing phase t112, and the time data writing phase t120 can vary. For example... Figure 7 As shown, in one embodiment, optionally, the current-driven initialization phase t111 is executed before the time data writing phase t120, and the amplitude data writing phase t112 is executed after the time data writing phase t120. Figure 8 As shown, in one embodiment, optionally, the current-driven initialization phase t111 and the amplitude data writing phase t112 are both executed simultaneously with the time data writing phase t120. Figure 9 As shown, in one embodiment, optionally, both the current drive initialization phase t111 and the amplitude data writing phase t112 are executed before the time data writing phase t120. Figure 10 As shown, in one embodiment, optionally, the current drive initialization phase t111 and the amplitude data writing phase t112 are both executed after the time data writing phase t120.

[0100] See also Figure 7 - Figure 10Based on the above embodiments, optionally, the pixel circuit driving method further includes a discharge stage t14, which is executed after the light emission stage t13. In the discharge stage t14, the fifth scan signal S5 is at a low level, the thirteenth transistor is turned on, and the second power supply signal is written to the anode of the light-emitting device, causing the light-emitting device to discharge, which helps alleviate the voltage bias problem of the light-emitting device. In other embodiments, the discharge stage t14 can also be executed simultaneously with the current drive initialization stage t111; the discharge stage t14 can also be executed simultaneously with the amplitude data writing stage t112; the discharge stage t14 can also be executed before the current drive initialization stage t111; and the discharge stage t14 can also be executed simultaneously with the time data writing stage t120.

[0101] It should be noted that the above embodiments are exemplarily described in a digital-driven manner and are not intended to limit the present invention. Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. See also... Figure 11 For example, the display panel includes pixel circuits 1 arranged in an array (m rows and n columns) and light-emitting devices connected to the pixel circuits 1. The pixel circuits 1 can be of any form, employing a ramp signal to control the emission time of the light-emitting devices. For example, the structure of the pixel circuits 1 is as follows: Figure 4 As shown.

[0102] Figure 12 This is a timing diagram illustrating another pixel circuit driving method provided in an embodiment of the present invention. (Combined with...) Figure 11 and Figure 12 In one embodiment of the present invention, optionally, the driving method is a mixed-signal driving method. Before the light emission stage t13, the method further includes: a time data writing stage t120 and an amplitude data writing stage t110.

[0103] During the time data writing phase t120, the time data voltage is written to the time drive module line by line. The execution method of the time data writing phase is similar to that of the digital drive, and will not be described in detail here.

[0104] During the amplitude data writing stage t110, the amplitude data voltage is written to the current drive module row by row. Unlike digital drive, the amplitude data voltage is adjustable, and the amplitude data voltage corresponding to each pixel circuit may be different. Therefore, a row-by-row writing method is required to write the amplitude data voltage to each current drive module separately. At this time, the first scan signal S1A corresponding to each row of current drive modules is shifted row by row, and the second scan signal S2A is shifted row by row.

[0105] Optionally, similar to the time-driven module, the current-driven module has a threshold voltage compensation function. Therefore, the driving method for the current-driven module includes: the initialization process of the current-driven module (see reference). Figure 5 The current drive initialization phase t011 in the middle, and the process of writing the amplitude data voltage into the current drive module (refer to the following). Figure 5 In the amplitude data writing stage t012, optionally, to simplify the driving timing, in this embodiment of the invention, during the amplitude data writing stage, while writing the amplitude data voltage to the current driving module of the current row, the current driving module of the next row is initialized. Specifically, while the first row current driving module performs the data writing stage, the second row current driving module performs the initialization stage; while the second row current driving module performs the data writing stage, the third row current driving module performs the initialization stage; and so on, until the data writing of all rows of current driving modules is completed. Similar to the time driving module, the first scan signal S1A and the second scan signal S2A used to drive the current Id1 driving module use the same scan driving circuit 2. This achieves that while the first row current driving module performs the data writing stage, the second row current driving module performs the initialization stage.

[0106] Therefore, compared to digital driving, the driving timing of the hybrid analog-digital driving method is more complex. Besides writing the time data signal line by line into the time driving module, it also requires writing the amplitude data signal line by line into the current driving module. Correspondingly, the amplitude data signal also needs to be written line by line into the current driving module during the sub-data reset stage of the emission phase. However, the hybrid analog-digital driving method produces finer grayscale, offering advantages for small-sized display panels with short line-by-line scanning times. Therefore, in practical applications, either digital driving or hybrid analog-digital driving can be selected as needed.

[0107] In the above embodiments, the execution time order of the amplitude data writing stage t110 and the time data writing stage t120 can vary. For example... Figure 12 As shown, in one implementation, optionally, the amplitude data writing phase t110 is executed after the time data writing phase t120. Figure 13 As shown, in one implementation, optionally, the amplitude data writing phase t110 is executed before the time data writing phase t120. Figure 14 As shown, in one embodiment, optionally, the amplitude data writing stage t110 and the time data writing stage t120 are executed simultaneously. This configuration is equivalent to multiplexing the first scan signal S1A and the third scan signal S1W, and multiplexing the second scan signal S2A and the fourth scan signal S2W. These scan signals can be driven by a single scan driving circuit 2, which helps to simplify the circuit design of the display panel.

[0108] It should be noted that the above embodiments exemplify that the light emission stage includes only two sub-light emission stages, and are not intended to limit the invention. Figure 15 As shown, the light-emitting stage may also include four sub-light-emitting stages. In other embodiments, the light-emitting stage may also include three, five, or more sub-light-emitting stages. In practical applications, the number of sub-light-emitting stages can be determined as needed. It is understood that the more sub-light-emitting stages there are, the steeper the slope of the ramp signal, and the shorter the switching time of the light-emitting device from bright to dark; the fewer the sub-light-emitting stages there are, the fewer the number of sub-data reset stages, which is beneficial for shortening the driving timing duration while achieving the same light-emitting time.

[0109] It should also be noted that, such as Figure 4 As shown in the above embodiments, the structure of the pixel circuit is exemplary, wherein the current driving module 110 includes a first driving transistor DT1, and the driving current Id1 is generated by the first driving transistor DT1 in response to its gate voltage; the time driving module 120 controls the timing of the current driving module 110 generating the driving current Id1 by controlling the gate of the first driving transistor DT1. This is not a limitation of the present invention. Figure 16 A schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 16 In another embodiment of the invention, optionally, with Figure 4The difference lies in that the time-driven module 120 controls the current flow path of the first driving transistor DT1 to control the timing of the driving current Id1 generated by the current-driven module 110. This is equivalent to the time-driven module 120 and the current-driven module 110 being connected in series, with the current generated by the time-driven module 120 being equal to the driving current Id1 generated by the current-driven module 110. Therefore, it is necessary to adaptively adjust the values ​​of signals such as the time data voltage DataW, the slope of the ramp signal Vsweep, and the amplitude data voltage DataA to match changes in the pixel circuit structure. For example, in the aforementioned embodiments, under the control of the ramp signal Vsweep, the time-driven module 120 switches from an off state to a on state, causing the LED to switch from a bright state to a dark state. In this embodiment, however, it is necessary to adjust the ramp signal Vsweep and the time data voltage DataW to switch the time-driven module 120 from an on state to an off state, causing the LED to switch from a bright state to a dark state. Furthermore, in the aforementioned embodiments, the driving current Id1 remains constant when the LED is emitting light. In this embodiment, under the control of the ramp signal Vsweep, the driving current Id1 gradually changes, and it is necessary to adjust the values ​​of signals such as the time data voltage DataW, the slope of the ramp signal Vsweep, and the amplitude data voltage DataA to adapt to the display grayscale of the light-emitting device LED under changes in brightness.

[0110] It should also be noted that in the above embodiments, such as Figure 4 As shown, when both the current drive module 110 and the time drive module 120 require separate power signal inputs, the power signal input to the current drive module 110 can be set as the first power signal VDDA, and the power signal input to the time drive module 120 can be set as the third power signal VDDW. The voltage values ​​of the first power signal VDDA and the third power signal VDDW can be the same or different, and can be set as needed in practical applications. Figure 16 As shown, when the current drive module 110 and the time drive module 120 are connected to the same power signal, the first power signal VDDA and the third power signal VDDW are no longer distinguished and are collectively referred to as the power signal VDD.

[0111] It should also be noted that the above embodiments exemplify the switching of the LED from a bright state to a dark state in each sub-lighting stage, and are not intended to limit the invention. In other embodiments, the LED may also be configured to switch from a dark state to a bright state in each sub-lighting stage.

[0112] It should also be noted that, in the above embodiments, the current drive module 110 and the time drive module 120, which have threshold voltage compensation functions, are used as exemplary examples for description, and this is not intended to limit the present invention. In other embodiments, the current drive module 110 and / or the time drive module 120 may not have threshold voltage compensation functions. For example, Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also... Figure 17 In one embodiment of the present invention, optionally, the current driving module 110 includes a first driving transistor DT1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The first driving transistor DT1 constitutes the driving unit of the current driving module 110. The first driving transistor DT1 generates a driving current Id1 in response to its gate voltage to drive the light-emitting device LED to emit light. The second transistor T2 and the third transistor T3 constitute the light-emitting control unit of the current driving module 110. The gate of the second transistor T2 is connected to the light-emitting control signal EM, the first terminal of the second transistor T2 is connected to the first power supply signal VDDA, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the first driving transistor DT1. The gate of the third transistor T3 is connected to the light-emitting control signal EM, the first terminal of the third transistor T3 is electrically connected to the second terminal of the first driving transistor DT1, the second terminal of the third transistor T3 is electrically connected to the anode of the light-emitting device LED, and the cathode of the light-emitting device LED is connected to the second power supply signal VSS. The fourth transistor T4 constitutes the data writing unit of the current drive module 110. The gate of the fourth transistor T4 is connected to the first scan signal S1A, the first terminal of the fourth transistor T4 is connected to the amplitude data voltage DataA, and the second terminal of the fourth transistor T4 is electrically connected to the gate of the first drive transistor DT1. The first capacitor C1 serves as the storage unit of the current drive module 110. The first terminal of the first capacitor C1 is connected to the first power supply signal VDDA, and the second terminal of the first capacitor C1 is electrically connected to the gate of the first drive transistor DT1. Optionally, only one of the second transistor T2 and the third transistor T3 may be used.

[0113] The time-driving module 120 includes a second driving transistor DT7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The second driving transistor DT7 constitutes the driving unit of the time-driving module 120. The eighth transistor T8 and the ninth transistor T9 constitute the light-emitting control unit of the time-driving module 120. The gate of the eighth transistor T8 is connected to the light-emitting control signal EM, the first terminal of the eighth transistor T8 is connected to the third power supply signal VDDW, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal of the second driving transistor DT7. The gate of the ninth transistor T9 is connected to the light-emitting control signal EM, the first terminal of the ninth transistor T9 is electrically connected to the second terminal of the second driving transistor DT7, and the second terminal of the ninth transistor T9 is electrically connected to the gate of the first driving transistor DT1. The tenth transistor T10 constitutes the data writing unit of the time-driving module 120. The gate of the tenth transistor T10 is connected to the third scan signal S1W, the first terminal of the tenth transistor T10 is connected to the time data voltage DataW, and the second terminal of the tenth transistor T10 is electrically connected to the gate of the second driving transistor DT7. The second capacitor C2 serves as a coupling unit for the time-driven module 120. The first terminal of the second capacitor C2 is connected to the ramp signal Vsweep, and the second terminal of the second capacitor C2 is electrically connected to the gate of the second driving transistor DT7. Optionally, only one of the eighth transistor T8 and the ninth transistor T9 may be used.

[0114] Figure 17 The pixel circuit shown can employ the driving method provided in any embodiment of the present invention. For example, a digital driving method or a mixed-signal driving method, etc., are implemented in a manner similar to the foregoing embodiments and will not be described again.

[0115] It should also be noted that in the above embodiments, the example given is that all transistors in the pixel circuit are P-type transistors, and this is not intended to limit the present invention. Those skilled in the art will understand that at least some transistors in the pixel circuit can be configured as N-type transistors, and the pixel circuit provided by the present invention will still be applicable.

[0116] It should also be noted that the above embodiments are exemplified by including a current-driven module and a time-driven module in the pixel circuit, and are not intended to limit the invention. In other embodiments, the ramp signal can be set to directly act on the current-driven module, and this can be configured as needed in practical applications.

[0117] This invention also provides a display device. The display device may be, for example, a mobile phone, computer, tablet computer, wearable device, etc., and the light-emitting device in the display device may be a self-emissive device such as an organic light-emitting diode or a micro light-emitting diode. The display device includes a control chip and a display panel. The display panel has pixel circuits arranged in an array. The control chip drives the pixel circuits using the pixel circuit driving method provided in any embodiment of this invention; the technical principle and the resulting effect are similar and will not be described again.

[0118] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving method for a pixel circuit, characterized in that, The pixel circuit includes a current driving module, which generates a driving current during the light-emitting stage to drive the light-emitting device to emit light. The current driving module drives the light-emitting device to emit light for a frame for a duration controlled by a ramp signal; the driving method includes: The light-emitting stage includes at least two sub-light-emitting stages; in each sub-light-emitting stage, the voltage of the ramp signal changes in a ramp-like manner to adjust the light-emitting time of the light-emitting device in each sub-light-emitting stage respectively. The pixel circuit also includes a time-driving module, and the ramp signal controls the light emission time of the current-driving module by controlling the working state of the time-driving module. The time-driven module includes a data writing unit, wherein the data voltage written to the current-driven module is an amplitude data voltage, and the data voltage written to the time-driven module is a time data voltage; The driving method is digital driving; correspondingly, the amplitude data voltage is a constant voltage value, and the time data voltage is adjustable; Alternatively, the driving method is a hybrid analog-digital drive; correspondingly, both the amplitude data voltage and the time data voltage are adjustable. The time-driving module generates a pulse width signal under the control of the time data voltage and the ramp signal to control the light emission time of the light-emitting device; The time-driving module includes a second driving transistor and a second capacitor; the second driving transistor constitutes the driving unit of the time-driving module; the second capacitor serves as the coupling unit of the time-driving module, with the first terminal of the second capacitor connected to the ramp signal and the second terminal of the second capacitor connected to the gate of the second driving transistor. The current drive module includes a first drive transistor, and the drive current is generated by the first drive transistor in response to its gate voltage; The time-driven module controls the timing of the current-driven module generating the driving current by controlling the gate of the first driving transistor; or, the time-driven module controls the timing of the current-driven module generating the driving current by controlling the current flow path of the first driving transistor.

2. The driving method for the pixel circuit according to claim 1, characterized in that, In each of the sub-light emission stages, the ramp signal changes from a first voltage to a second voltage.

3. The driving method for the pixel circuit according to claim 1 or 2, characterized in that, In each of the sub-luminescence stages, the slope of the ramp signal is the same.

4. The driving method for the pixel circuit according to claim 1, characterized in that, Between adjacent sub-luminescence stages, the following is also included: During the sub-data reset phase, the gate of the first driving transistor in the current drive module is reset.

5. The driving method for the pixel circuit according to claim 4, characterized in that, The current drive module has a threshold voltage compensation function, and the sub-data reset stage includes: During the initialization phase, the gate of the first driving transistor is initialized; During the sub-data writing stage, data is written to the gate of the first driving transistor.

6. The driving method for the pixel circuit according to claim 1, characterized in that, If the driving method is digital driving, then before the light emission stage, it further includes: During the time data writing phase, the time data voltage is written to the time drive module line by line. During the amplitude data writing stage, the amplitude data voltage is simultaneously written to all the current drive modules.

7. The driving method for the pixel circuit according to claim 6, characterized in that, The amplitude data writing phase and the time data writing phase are executed simultaneously.

8. The driving method for the pixel circuit according to claim 6, characterized in that, The current drive module has a threshold voltage compensation function, and before the amplitude data writing stage, the current drive module further includes: During the current-driven initialization phase, all the aforementioned current-driven modules are initialized simultaneously. And / or, the time-driving module has a threshold voltage compensation function, and during the execution of the time data writing stage, while writing the time data voltage into the time-driving module of the current row, the time-driving module of the next row is initialized.

9. The driving method for the pixel circuit according to claim 8, characterized in that, The current drive initialization phase is executed before the time data writing phase, and the amplitude data writing phase is executed after the time data writing phase. Alternatively, the current-driven initialization phase and the amplitude data writing phase can both be executed simultaneously with the time data writing phase; Alternatively, both the current-driven initialization phase and the amplitude data writing phase are executed before the time data writing phase; Alternatively, both the current-driven initialization phase and the amplitude data writing phase may be executed after the time data writing phase.

10. The driving method for a pixel circuit according to claim 1, characterized in that, If the driving method is a mixed-signal driving method, then before the light emission stage, it further includes: During the time data writing phase, the time data voltage is written to the time drive module line by line. During the amplitude data writing stage, the amplitude data voltage is written to the current drive module line by line.

11. The driving method for a pixel circuit according to claim 10, characterized in that, The amplitude data writing phase and the time data writing phase are executed simultaneously.

12. A display device, characterized in that, The device includes a control chip and a display panel, wherein the display panel is provided with pixel circuits arranged in an array, and the control chip drives the pixel circuits using the pixel circuit driving method as described in any one of claims 1-11.

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