A SARADC capacitor array calibration method and circuit

Abstract

A SARADC capacitor array calibration method and circuit, relating to the field of semiconductor integrated circuits. The calibration method of the present invention comprises the following steps: (1) in the calibration mode, the high-order capacitor of the capacitor array DAC in the SARADC samples the reference voltage, and then the low-order capacitor quantizes the high-order capacitor, and the weight error of the high-order capacitor is calculated as the error compensation code according to the quantization result, and stored; (2) in the normal working mode, the SARADC completes the sampling and quantization of the input analog signal, extracts the error compensation code of the weight position that needs to be compensated for the weight error according to the comparator result in the SARADC, calculates the total compensation value, and adds it to the uncalibrated output result output by the SARADC to obtain the calibrated output result. The present invention can accurately measure the weight error of the capacitor array DAC without measuring the comparator noise.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a SARADC capacitance array calibration method and circuit. Background Art

[0002] Compared with analog circuits, digital circuits have the characteristics of strong anti-interference ability, high reliability, and high integration, so digital circuits are widely used in the field of signal processing. Digital circuits process digital signals, while most signals in nature are analog signals. The module that converts analog signals into digital signals is called an analog-to-digital converter (hereinafter referred to as ADC). Common ADCs are divided into flash ADCs, pipeline ADCs, Σ-Δ ADCs, and successive approximation register (SAR) ADCs. Users can choose the appropriate ADC according to speed and accuracy requirements. Among high-precision, low-speed ADCs, the more commonly used types are usually Σ-Δ ADCs and successive approximation register (SAR) ADCs. High-precision SAR ADCs are being used more and more widely because of their low power consumption.

[0003] The linearity of SARADC is mainly determined by the linearity of the DAC. Currently, most common SARADCs use a charge redistributed capacitor array DAC structure. The matching error between different capacitors caused by processing technology causes errors in the weight of the capacitor array, which leads to poor linearity of the capacitor array DAC, which directly limits the linearity of the SARADC. In order to improve linearity, it is necessary to correct the capacitor weight error in the capacitor array DAC. Currently, there are two widely used methods for correcting capacitor weight errors: analog domain calibration and digital domain calibration. Analog domain calibration is to calibrate the capacitor weight error of the main capacitor array DAC through a special calibration DAC. This calibration DAC can be a resistor DAC or a capacitor DAC. Analog domain calibration has the following disadvantages. First, the different effects of process gradient error and packaging stress on the accuracy of the calibration DAC and the main capacitor array DAC will lead to a decrease in calibration accuracy. Second, as the ADC resolution increases, the resolution of the calibration DAC also increases accordingly, resulting in a significant increase in the number and area of ​​capacitors in the calibration DAC, and the area will not decrease as the processing size decreases. Third, during normal conversion, the calibration DAC must dynamically perform charge calibration compensation for the main capacitor array DAC based on the results of the comparator. This action will introduce noise into the analog circuit and increase the dynamic load of the reference voltage, thereby affecting the conversion accuracy.

[0004] Digital domain calibration is to first calculate or measure the weight error of the capacitor, and then compensate the weight error in the digital domain. There are two disadvantages in the existing digital domain calibration technology. First, when measuring the weight error, the measurement accuracy of each weight error is 1 least significant bit, that is, 1LSB. If multiple weight errors need to be compensated, the measurement errors will be accumulated, resulting in the nonlinear error still being greater than 1LSB after the weight error is compensated in the digital domain, and the accuracy after calibration is limited. Second, when measuring the weight error, the noise of the comparator will cause the comparison result of the comparator to be a probability distribution of logic "0" or logic "1" for a smaller input signal, and the probability distribution curve conforms to the Gaussian probability distribution. The existing technology uses the method of measuring the weight error multiple times to find the average value to reduce the influence of the comparator noise, but this method has limited accuracy, because even if the comparator input voltage remains unchanged, the comparator noise is different, which will also cause the probability of the comparator comparison result to be logic "0" (or logic "1") to be different. Summary of the invention

[0005] Based on the above problems, the first object of the present invention is to provide a SARADC capacitor array calibration method, which can be used to accurately calibrate the weight error of the capacitor array DAC in the digital domain, thereby improving the linearity of the charge redistributed capacitor array DAC in the SARADC and solving the capacitor mismatch problem caused by process deviation in the high-precision capacitor array used in the high-precision SARADC.

[0006] The technical solution adopted by the present invention to achieve the first invention object is a SARADC capacitor array calibration method, the steps of which include:

[0007] (1) In the calibration mode, the high-order capacitor of the capacitor array DAC in the SAR ADC samples the reference voltage, and then the low-order capacitor quantizes the high-order capacitor. The weight error of the high-order capacitor is calculated based on the quantization result as the error compensation code and stored;

[0008] (2) In normal working mode, SARADC completes the sampling and quantization of the input analog signal, extracts the error compensation code of the weight bit that needs to be compensated for the weight error according to the comparator result in SARADC, calculates the total compensation value, and adds it to the uncalibrated output result output by SARADC to obtain the calibrated output result.

[0009] Furthermore, the kth capacitor C k The weight is 2 k-1 ,E k is the weight error of the kth capacitor, k = 3 ~ N, assuming C2, C 2r ,C1 and C 1r The weight error of C can be ignored. 2r and C 1rare redundant bits, with weights of 2 1 and 2 0 ; The step (1) specifically comprises the following sub-steps:

[0010] (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C k+1 , C k The bottom plate of the capacitor is connected to VREF; C k-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND;

[0011] (1.b) The top plate of the capacitor is disconnected from GND;

[0012] (1.c)C k The bottom plate is connected to GND;

[0013] (1.d) for C k-1 Conduct the experiment, C k-1 The bottom board is connected to VREF, and the comparator compares n times continuously, where n is greater than 1. The higher the measurement accuracy requirement, the larger the value of n, for example, n is 50, 100, etc. If the n comparison results are consistent, continue to test the next capacitor. When the comparison results are all logic "0", C k-1 The bottom board remains connected to VREF. When the comparison results are all logic "1", C k-1 Connect the bottom board back to GND; if the results of n comparisons are partly logical "0" and partly logical "1", stop the test, calculate the probability of the comparison result being logical "0", and find the refined weight value W from the refined weight-probability lookup table fine ;

[0014] (1.e) respectively for C k-2 , ..., C2, C 2r ,C1,C 1r Repeat the experiment in step (1.d);

[0015] (1.f) Calculate C based on the comparison results of steps (1.d) and (1.e) k The weight error is:

[0016] C m When conducting an experiment, if the results of n comparisons are consistent, C m When connected to VREF, b m =1, C m When connected to GND, b m = 0; if the results of n comparisons are partly logical "0" and partly logical "1", then b m =1,b m-1=0,……,b2=0,b1=0,b 2r =0,b 1r =0

[0017] Where: m = 1 ~ (k-1) or 1r or 2r, b m is the capacitance C m The switch signal;

[0018] Calculate C k The weight error is:

[0019] E k = coarse quantization weight + fine quantization weight - ideal weight

[0020] Where:

[0021] E k C k The weight error,

[0022] Coarse quantization weight = b k-1 ×2 k-2 +b k-2 ×2 k-3 +……+b1×2 1 +b 2r ×2 1 +b 1r ×2 0 ,

[0023] The quantization weight is W fine ,

[0024] Ideal weight = 2 k-1 ;

[0025] Repeat steps (1.a) to (1.f) to measure C3~C N The weight error E3~E N , the weight error E3~E N as an error compensation code.

[0026] Furthermore, the process of establishing the refined quantization weight-probability lookup table includes:

[0027] (1) The comparator inputs a positive voltage or zero voltage and performs the following steps:

[0028] (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND;

[0029] (1.b) The top plate of the capacitor is disconnected from GND;

[0030] (1.c) Switching signal of capacitor array b N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 00...000000 to 11...111111, a total of 2 N+4 Select one code value that has not been selected from the code values ​​to control the capacitor array;

[0031] Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND;

[0032] Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4;

[0033] (1.d) The comparator compares n times continuously, where n is greater than 1. The higher the measurement accuracy requirement, the larger the value of n needs to be, and the more weight capacitor bits less than 1 are needed. For example, n is 50, 100, and the number of weight capacitor bits less than 1 is 4, 6, and so on. If part of the results of the n comparisons are logic "0" and the other part are logic "1", calculate the probability of the comparison results showing logic "0" and go to step (1.c); if the results of the n comparisons are consistent, go to step (1.e);

[0034] (1.e) The precise weight-probability lookup table of the comparator input positive direction voltage or zero voltage is established;

[0035] (2) The comparator inputs a negative voltage and performs the following steps:

[0036] (2.a) The top plate of the capacitor is connected to VREF; C N , C N-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to VREF;

[0037] (2.b) The top plate of the capacitor is disconnected from VREF;

[0038] (2.c) Switching signal b of capacitor array N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 11...111110 to 00...000000, a total of 2 N+4 -1 code values ​​are selected in turn to control the capacitor array;

[0039] Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND;

[0040] Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4;

[0041] (2.d) The comparator compares n times continuously, where n is greater than 1. The higher the measurement accuracy requirement, the larger the value of n needs to be, and the more weight capacitor bits less than 1 are needed. For example, n is 50, 100, and the number of weight capacitor bits less than 1 is 4, 6, and so on. If part of the results of the n comparisons are logic "0" and the other part are logic "1", calculate the probability of the comparison results showing logic "0" and go to step (2.c); if the results of the n comparisons are consistent, go to step (2.e);

[0042] (2.e) The precise weight-probability lookup table of the negative direction voltage of the comparator input is established.

[0043] Furthermore, the specific calculation method of the calibrated output result DOUT_correted in the normal working mode is:

[0044] D OUT correted =D OUT +Weight compensation value

[0045] Where: D OUT =b N b N-1 ……b4b3b2b 2r b1b 1r

[0046] Weight compensation value = b N-1 ×E N-1 +b N-2 ×E N-2 +……+b4×E4+b3×E3

[0047] Where: D OUT It is the uncalibrated output result of SARADC.

[0048] The second object of the present invention is to provide a SARADC circuit with a capacitor array calibration function, which can achieve accurate calibration of capacitor array DAC weight errors and improve the output result accuracy of the SARADC.

[0049] The technical solution adopted by the present invention to achieve its second invention purpose is: a SARADC circuit with a capacitor array calibration function, used in a SARADC capacitor array calibration method, composed of a SARADC circuit and a calibration circuit, wherein the SARADC circuit is composed of a capacitor array DAC, a comparator and a successive approximation register, and the calibration circuit is composed of a read-only register, a weight compensation module and an adder, the read-only register is used to receive and store the weight error calculated by a test machine connected to the SARADC circuit, the weight compensation module is used to extract the error compensation code of the weight bit that needs to be compensated for the weight error from the read-only register according to the comparator result and calculate the weight compensation value, and the adder is used to add the weight compensation value output by the weight compensation module to the uncalibrated output result of the SARADC to generate a calibrated output result.

[0050] The beneficial effects of the present invention are:

[0051] The present invention can accurately measure the weight error of the capacitor array DAC without measuring the comparator noise, and realize accurate calibration of the weight error of the capacitor array DAC in the digital domain, thereby improving the linearity and output result accuracy of the SARADC. Compared with the existing digital domain calibration method, it has the advantages of simple circuit implementation and high calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a circuit structure block diagram of the present invention;

[0053] Figure 2 This is a structural diagram of the capacitor array DAC circuit of the present invention. DETAILED DESCRIPTION

[0054] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Figure 1 and Figure 2 It is shown that a specific implementation of the present invention is a SARADC capacitor array calibration method, comprising the following steps:

[0056] (1) In the calibration mode, the high-order capacitor of the capacitor array DAC in the SAR ADC samples the reference voltage, and then the low-order capacitor quantizes the high-order capacitor. The weight error of the high-order capacitor is calculated based on the quantization result as the error compensation code and stored;

[0057] (2) In normal working mode, SARADC completes the sampling and quantization of the input analog signal, extracts the error compensation code of the weight bit that needs to be compensated for the weight error according to the comparator result in SARADC, calculates the total compensation value, and adds it to the uncalibrated output result output by SARADC to obtain the calibrated output result.

[0058] Figure 2 The capacitor array DAC with N-bit resolution and redundant bits is shown. k The weight is 2 k-1 ,E k is the weight error of the kth capacitor, k = 3 ~ N, assuming C2, C 2r ,C1 and C 1r The weight error of C can be ignored. 2r and C 1r are redundant bits, with weights of 2 1 and 2 0 .

[0059] The step (1) specifically comprises the following sub-steps:

[0060] (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C k+1 , C k The bottom plate of the capacitor is connected to VREF; C k-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND;

[0061] (1.b) The top plate of the capacitor is disconnected from GND;

[0062] (1.c)C k The bottom plate is connected to GND;

[0063] (1.d) for C k-1 Conduct the experiment, C k-1 The bottom board is connected to VREF, and the comparator compares n times continuously, where n is greater than 1. If the comparison results are consistent, the next capacitor is tested. When the comparison results are all logic "0", C k-1 The bottom board remains connected to VREF. When the comparison results are all logic "1", C k-1 Connect the bottom board back to GND; if the results of n comparisons are partly logical "0" and partly logical "1", stop the test, calculate the probability of the comparison result being logical "0", and find the refined weight value W from the refined weight-probability lookup table fine ;

[0064] (1.e) respectively for C k-2, ..., C2, C 2r ,C1,C 1r Repeat the experiment in step (1.d);

[0065] (1.f) Calculate C based on the comparison results of steps (1.d) and (1.e) k The weight error is:

[0066] C m When conducting an experiment, if the results of n comparisons are consistent, C m When connected to VREF, b m =1, C m When connected to GND, b m = 0; if the results of n comparisons are partly logical "0" and partly logical "1", then b m =1,b m-1 =0,……,b2=0,b1=0,b 2r =0,b 1r =0

[0067] Where: m = 1 ~ (k-1) or 1r or 2r, b m is the capacitance C m The switch signal;

[0068] Calculate C k The weight error is:

[0069] E k = coarse quantization weight + fine quantization weight - ideal weight

[0070] Where:

[0071] E k C k The weight error,

[0072] Coarse quantization weight = b k-1 ×2 k-2 +b k-2 ×2 k-3 +……+b1×2 1 +b 2r ×2 1 +b 1r ×2 0 ,

[0073] The quantization weight is W fine ,

[0074] Ideal weight = 2 k-1 ;

[0075] Repeat steps (1.a) to (1.f) to measure C3~C N The weight error E3~E N, the weight error E3~E N as an error compensation code.

[0076] The process of establishing the refined quantization weight-probability lookup table includes:

[0077] (1) The comparator inputs a positive voltage or zero voltage and performs the following steps:

[0078] (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND;

[0079] (1.b) The top plate of the capacitor is disconnected from GND;

[0080] (1.c) Switching signal of capacitor array b N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 00...000000 to 11...111111, a total of 2 N+4 Select one code value that has not been selected from the code values ​​to control the capacitor array;

[0081] Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND;

[0082] Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4;

[0083] (1.d) The comparator compares n times in succession, where n is greater than 1. If part of the results of the n comparisons are logic "0" and the other part are logic "1", the probability of the comparison result being logic "0" is calculated, and the process goes to step (1.c); if the results of the n comparisons are consistent, the process goes to step (1.e);

[0084] (1.e) The precise weight-probability lookup table of the comparator input positive direction voltage or zero voltage is established;

[0085] (2) The comparator inputs a negative voltage and performs the following steps:

[0086] (2.a) The top plate of the capacitor is connected to VREF; C N , C N-1 , ..., C2, C 2r ,C1,C 1rThe bottom plate of the capacitor is connected to VREF;

[0087] (2.b) The top plate of the capacitor is disconnected from VREF;

[0088] (2.c) Switching signal b of capacitor array N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 11...111110 to 00...000000, a total of 2 N+4 -1 code values ​​are selected in turn to control the capacitor array;

[0089] Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND;

[0090] Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4;

[0091] (2.d) The comparator compares n times in succession, where n is greater than 1. If part of the results of the n comparisons are logic "0" and the other part are logic "1", the probability of the comparison result being logic "0" is calculated, and the process goes to step (2.c); if the results of the n comparisons are consistent, the process goes to step (2.e);

[0092] (2.e) The precise weight-probability lookup table of the negative direction voltage of the comparator input is established.

[0093] In normal working mode, the analog input signal V IN The SARADC quantizes the data bit by bit and outputs the rough, uncalibrated conversion digital result D bit by bit. OUT .

[0094] The output result after calibration is D OUT_correted The specific calculation method is:

[0095] D OUT_correted =D OUT +Weight compensation value

[0096] Where: D OUT =b N b N-1 ……b4b3b2b 2r b1b 1r

[0097] Weight compensation value = b N-1 ×E N-1 +bN-2 ×E N-2 +……+b4×E4+b3×E3

[0098] Figure 1 A specific implementation of the SARADC circuit with a capacitor array calibration function provided by the present invention is shown: it is used in a SARADC capacitor array calibration method, and is composed of a SARADC circuit and a calibration circuit, wherein the SARADC circuit is composed of a capacitor array DAC, a comparator and a successive approximation register, and the calibration circuit is composed of a read-only register ROM, a weight compensation module and an adder, wherein the read-only register ROM is used to receive and store a weight error calculated by a test machine connected to the SARADC circuit, the weight compensation module is used to extract an error compensation code of a weight bit that needs to be compensated for weight error from the read-only register according to a comparator result and calculate a weight compensation value, and the adder is used to compare the weight compensation value output by the weight compensation module with the uncalibrated output result D of the SARADC. OUT The addition produces the calibrated output D OUT_correted .

[0099] The above embodiments of the present invention are merely examples for illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes and modifications can be made based on the above description. It is impossible to list all the embodiments here. Any obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A SARADC capacitance array calibration method, characterized in that: The steps include: (1) In the calibration mode, the high-order capacitor of the capacitor array DAC in the SAR ADC samples the reference voltage, and then the low-order capacitor quantizes the high-order capacitor. The weight error of the high-order capacitor is calculated based on the quantization result as the error compensation code and stored; (2) In normal working mode, SARADC completes sampling and quantization of the input analog signal, extracts the error compensation code of the weight bit that needs to be compensated for weight error according to the comparator result in SARADC, calculates the total compensation value, and adds it to the uncalibrated output result output by SARADC to obtain the calibrated output result; The step (1) specifically comprises the following sub-steps: (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C k+1 , C k The bottom plate of the capacitor is connected to VREF; C k-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND; (1.b) The top plate of the capacitor is disconnected from GND; (1.c)C k The bottom plate is connected to GND; (1.d) for C k-1 Conduct the experiment, C k-1 The bottom board is connected to VREF, and the comparator compares n times continuously, where n is greater than 1. If the comparison results of n times are consistent, the next capacitor is tested. When the comparison results are all logic "0", C k-1 The base plate remains connected to VREF. When the comparison results are all logic "1", C k-1 Connect the bottom board back to GND; if part of the results of n comparisons are logic "0" and the other part are logic "1", stop the test, calculate the probability of the comparison result being logic "0", and find the refined weight value W from the refined weight-probability lookup table fine ; (1.e) respectively for C k-2 , ..., C2, C 2r ,C1,C 1r Repeat the experiment in step (1.d); (1.f) Calculate C based on the comparison results of steps (1.d) and (1.e) k The weight error is: C m When conducting an experiment, if the results of n comparisons are consistent, C m When connected to VREF, b m =1, C m When connected to GND, b m = 0; if the results of n comparisons are partly logical "0" and partly logical "1", then b m =1,b m-1 =0,……,b2=0,b1=0,b 2r =0,b 1r =0 Where: m = 1 ~ (k-1) or 1r or 2r, b m is the capacitance C m The switch signal; Calculate C k The weight error is: E k = coarse quantization weight + fine quantization weight - ideal weight Where: E k C k The weight error, Coarse quantization weight = b k-1 ×2 k-2 +b k-2 ×2 k-3 +……+b1×2 1 +b 2r ×2 1 +b 1r ×2 0 , The quantization weight is W fine , Ideal weight = 2 k-1 ; Repeat steps (1.a) to (1.f) to measure C3~C N The weight error E3~E N , the weight error E3~E N as an error compensation code.

2. A SARADC capacitance array calibration method according to claim 1, characterized in that: The process of establishing the refined quantization weight-probability lookup table includes: (1) The comparator inputs a positive voltage or zero voltage and performs the following steps: (1.a) The top plate of the capacitor is connected to GND; C N , C N-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to GND; (1.b) The top plate of the capacitor is disconnected from GND; (1.c) Switching signal of capacitor array b N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 00...000000 to 11...111111, a total of 2 N+4 Select one code value that has not been selected from the code values ​​to control the capacitor array; Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND; Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4; (1.d) The comparator compares n times in succession, where n is greater than 1. If part of the results of the n comparisons are logic "0" and the other part are logic "1", the probability of the comparison result being logic "0" is calculated, and the process goes to step (1.c); if the results of the n comparisons are consistent, the process goes to step (1.e); (1.e) The precise weight-probability lookup table of the comparator input positive direction voltage or zero voltage is established; (2) The comparator inputs a negative voltage and performs the following steps: (2.a) The top plate of the capacitor is connected to VREF; C N , C N-1 , ..., C2, C 2r ,C1,C 1r The bottom plate of the capacitor is connected to VREF; (2.b) The top plate of the capacitor is disconnected from VREF; (2.c) Switching signal b of capacitor array N b N-1 ...b2b1b f1 b f2 b f3 b f4 From 11...111110 to 00...000000, a total of 2 N+4 -1 code values ​​are selected in turn to control the capacitor array; Where: When the capacitor C i When the switching signal bi=1, it means the capacitor C i The bottom plate is connected to VREF. When bi=0, it represents the capacitor C i The bottom plate is connected to GND; Wherein: i = 1 to N or 1r or 2r or f1 or f2 or f3 or f4; (2.d) The comparator compares n times in succession, where n is greater than 1. If part of the results of the n comparisons are logic "0" and the other part are logic "1", the probability of the comparison result being logic "0" is calculated, and the process goes to step (2.c); if the results of the n comparisons are consistent, the process goes to step (2.e); (2.e) The precise weight-probability lookup table of the negative direction voltage of the comparator input is established.

3. A SARADC capacitance array calibration method according to claim 2, characterized in that: Output result after calibration in normal working mode D OUT_correted The specific calculation method is: D OUT_correted =D OUT +Weight compensation value Where: D OUT =b N b N-1 ...b4b3b2b 2r b1b 1r Weight compensation value = b N-1 ×E N-1 +b N-2 ×E N-2 +……+b4×E4+b3×E3 Where: D OUT It is the uncalibrated output result of SARADC.

Images