A hierarchical order preservation method for multi-source requests based on PCIE interface

Abstract

The present invention provides a multi-source request hierarchical order preservation method based on a PCIE interface. A data instruction carries an instruction body, a channel number, a configuration, a read / write flag, and selectively carries an RO flag. The RO flag is a flag defined in the PCIE specification. The PCIE interface divides the data instruction into a read request, a write request, a read response, and a write response according to the read / write flag; the PCIE interface hierarchically processes the data instruction according to the read / write flag and the RO flag. A three-level order preservation process is performed for the data instruction carrying the RO flag; a second-level order preservation process is performed for the write request and the write response in the data instruction without the RO flag; and a first-level order preservation process is performed for the read request and the read response in the data instruction without the RO flag. The request and response method based on the PCIE interface of the present invention performs hierarchical order preservation on multi-source requests and improves the response speed of the PCIE interface.

Description

Technical Field

[0001] The present invention relates to a request and response method based on a PCIE interface, and in particular to a multi-source request hierarchical order preservation method based on a PCIE interface. Background Art

[0002] PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard and a widely used bus protocol for interconnecting CPUs and various devices. PCIE is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions. The PCIE specification stipulates strict requirements for the order of various request responses.

[0003] In the design of implementing the PCIE interface, in addition to implementing the sequence requirements specified in the PCIE specification, it is also necessary to meet the sequence requirements of IP functions and logical functions to implement multiple requests.

[0004] Currently, there are few specific technical details for the implementation of PCIE sequences.

[0005] The PCIE interface adopts the AXI (Advanced eXtensible Interface) bus protocol design model and is generally implemented using a standard interface. There is almost no description in public information about how the sequence is processed internally. Summary of the invention

[0006] The purpose of the present invention is to provide a request and response method based on a PCIE interface, which performs hierarchical order preservation on multi-source requests and improves the response speed of the PCIE interface.

[0007] The invention discloses a multi-source request hierarchical order preservation method based on a PCIE interface. The data instruction carries an instruction body, a channel number (Chanel), a configuration (Type), a read / write flag, and selectively carries an RO flag. The RO flag is a flag defined in the PCIE specification. The PCIE interface classifies the data instruction into a read request, a write request, a read response, and a write response according to the read / write flag. The PCIE interface hierarchically processes the data instruction according to the read / write flag and the RO flag.

[0008] The PCIE interface is equipped with a sequence buffer, a reorder buffer, and a receive buffer;

[0009] For data instructions with RO mark, three-level order preservation is performed, for write request and write response in data instructions without RO mark, two-level order preservation is performed, for read request and read response in data instructions without RO mark, one-level order preservation is performed;

[0010] For data instructions carrying the RO flag, three-level order preservation processing is performed in the following manner:

[0011] The order-preserving buffer is used to temporarily store and process data instructions with the RO flag, where:

[0012] Read / write requests with the RO flag are directly stored in the order-preserving buffer;

[0013] The read / write response carrying the RO mark directly enters the order-preserving buffer and is matched with the read / write instructions temporarily stored in the order-preserving buffer. This method enables the read / write response carrying the RO mark to be transmitted efficiently and enables the data instructions carrying the RO mark to be processed quickly.

[0014] For write requests and write responses in data instructions without the RO flag, secondary order preservation is performed in the following manner:

[0015] The reorder buffer is used to temporarily store and process write requests and write responses in data instructions without RO flags;

[0016] Write requests without RO flags are written into the reordering buffer according to the channel number and configuration, and carry the current tail mark of the reordering buffer (reordering buffer flag). The write request is unpacked, and the number of unpacked packets is recorded in the corresponding entry of the reordering buffer;

[0017] The write response without RO flag is written into the reordering buffer according to the channel number and configuration, until the unpacked write request in the reordering buffer is completed with the write response, and the write response in the reordering buffer is activated and can be sent;

[0018] For read requests and read responses in data instructions without the RO flag, the first-level order preservation is performed in the following manner:

[0019] The read request without RO flag is written into the receiving buffer according to the channel number and carries the channel flag flag, sets the channel flag tag + 1, prepares to receive the next read request, and issues a read request carrying the channel flag flag;

[0020] The read response without the RO flag is written into the receiving buffer according to the channel number. The read response carries the channel flag flag. The read response is matched with the read request in the receiving buffer. From the channel flag flag = 0 to the last channel flag, the matched read responses are sent in sequence, and the channel flag tag + 1 is set to prepare for receiving the next read response.

[0021] Preferably, during the first-level order preservation processing, the read request and the read response are matched in the following manner:

[0022] The read request of the receiving buffer is split into multiple requests according to the request address and length, and the buffers are suspended separately. Each read request carries the channel flag and the suspended buffer number.

[0023] The read response received from the buffer carries the channel flag and the suspended buffer number, and the read response is matched with the read request based on the channel flag and the suspended buffer number.

[0024] More preferably, the maximum value of the read request length is set to 2KB. Within the PCIE IP, setting the maximum value of the read request length can improve transmission performance. Since the memory access request within the chip is set to 64B / 128B according to the cache line size, setting the maximum value of the read request length to 2KB can obtain optimal transmission performance.

[0025] More preferably, the PCIE interface is provided with a configuration register, the first-level order preservation process is provided with a configuration logic, and the configuration logic is stored in the configuration register and is used to record whether different types of read requests are subjected to the first-level order preservation process;

[0026] When different types of read requests are sent from different channels, the read requests carry different channel numbers. The configuration logic selects the read requests that meet the preservation conditions and performs first-level order preservation processing.

[0027] The read responses corresponding to the read requests that do not meet the storage conditions can be returned after all are collected.

[0028] Preferably, the reordering buffer is a trigger FIFO. Since not much information is needed to maintain the order, the use of the trigger fifo can respond quickly compared to other triggering methods.

[0029] Preferably, the RO flag is a 1-bit flag, which is implemented using 1 bit in the PCIE IP manual. The RO flag is more universal. The RO flag is 1 bit and is implemented using a flip-flop because the number of control information bits required is small and a memory array is not required.

[0030] Preferably, the RO flag is random and can be configured according to application requirements. For less stringent requirements on order preservation, relaxing the order preservation requirements can increase the transmission speed.

[0031] Preferably, the PCIE interface is provided with an order-preserving buffer, and the order-preserving buffer is provided with a buffer depth, and the buffer depth is set according to the memory access delay; since all read / write requests carrying the RO flag enter the buffer, if the order-preserving buffer queue is full, it will form a blockage, and setting the buffer depth according to the memory access delay can ensure the pipeline sending of the memory access requests.

[0032] More preferably, the optional value of the RO flag is 0 or 1. During the three-level order preservation processing, the read / write request and the read / write response are matched in the following manner:

[0033] Identify the read / write request with RO flag 0 as strong order preservation. The read / write request with RO flag 0 must be issued at the head of the order preservation buffer queue. The read / write request with RO flag 0 can be dequeued from the order preservation buffer queue only after the corresponding read / write response is received.

[0034] The read / write request with RO flag of 1 is identified as loose order. The read / write request with RO flag of 1 can be issued immediately after the preceding read / write request is issued. The read / write request with RO of 1 can be immediately dequeued from the order-preserving buffer queue if the packet has been sent and the preceding request does not block the unfinished RO of 0. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A hierarchical order preservation processing schematic diagram of a multi-source request hierarchical order preservation method based on a PCIE interface of the present invention

[0036] Figure 2 Schematic diagram of several data instruction structures

[0037] Figure 3 Schematic diagram for classifying data instructions

[0038] Figure 4 Instruction 5 for writing data before fifo

[0039] Figure 5 Instruction 6 for writing data into fifo DETAILED DESCRIPTION

[0040] In order to clearly describe the present invention, a multi-source request hierarchical order preservation method based on a PCIE interface of the present invention is further illustrated with reference to the accompanying drawings and examples.

[0041] like Figure 1 As shown, it is a schematic diagram of hierarchical order preservation processing of a multi-source request hierarchical order preservation method based on a PCIE interface of the present invention.

[0042] like Figure 2As shown, there are several data instruction examples. The data instruction carries the instruction body, channel number (Chanel), configuration (Type), read / write flag, and optionally carries the RO flag. The RO flag is a random 1-bit flag defined in the PCIE specification. The maximum value of the read request length is set to 2KB.

[0043] like Figure 3 As shown in the figure, it is a schematic diagram of data instruction classification. The PCIE interface classifies data instructions into read request, write request, read response, and write response according to the read / write flag; the PCIE interface processes data instructions in a hierarchical manner according to the read / write flag and the RO flag. Among them:

[0044] For data instructions carrying the RO flag, three-level order preservation processing is performed in the following manner:

[0045] The PCIE interface is equipped with an order-preserving buffer for temporarily storing and processing data instructions carrying the RO flag, among which:

[0046] Read / write requests with the RO flag are directly stored in the order-preserving buffer, and the buffer depth of the order-preserving buffer is 6;

[0047] The read / write response carrying the RO flag directly enters the order-preserving buffer and is matched with the read / write instructions temporarily stored in the order-preserving buffer. This method enables the read / write response carrying the RO flag to be transmitted efficiently and enables the data instructions carrying the RO flag to be processed quickly.

[0048] For example, there are the following 6 requests, the RO flag can be 0 or 1. The read / write request with the RO flag of 0 is strongly order-preserving, and the read / write request with the RO flag of 1 is loose order:

[0049] 1) Write request 0, RO = 1;

[0050] 2) Write request 1, RO = 0;

[0051] 3) Write request 2, RO=1;

[0052] 4) Read request 0, RO = 1;

[0053] 5) Write request 3, RO=1;

[0054] 6) Read request 1, RO = 0;

[0055] The first) write request 0 is loosely ordered, the head of the queue has no pre-order blocking, and is sent and dequeued;

[0056] The updated queue status is:

[0057] 1) Write request 1, RO = 0;

[0058] 2) Write request 2, RO=1;

[0059] 3) Read request 0, RO = 1;

[0060] 4) Write request 3, RO=1;

[0061] 5) Read request 1, RO = 0;

[0062] The current 1st) is the upper surface, i.e. the 2nd) of the original data;

[0063] Currently, the first write request 0 is strongly sequenced and is at the head of the queue, but the corresponding write response has not been received. Write request 1 is sent and does not leave the queue;

[0064] The updated queue status is:

[0065] 1) Write request 1, RO = 0; has been sent

[0066] 2) Write request 2, RO = 1; Head of queue

[0067] 3) Read request 0, RO = 1;

[0068] 4) Write request 3, RO=1;

[0069] 5) Read request 1, RO = 0;

[0070] Currently, the second write request 2 is in loose order, at the head of the queue, sent, and cannot be dequeued;

[0071] The updated queue status is:

[0072] 1) Write request 1, RO = 0; send, not out of queue

[0073] 2) Write request 2, RO = 1; sent, unable to dequeue

[0074] 3) Read request 0, RO = 1; head of the queue

[0075] 4) Write request 3, RO=1;

[0076] 5) Read request 1, RO = 0;

[0077] Currently, the 3rd read request 0 is in loose order, at the head of the queue, sent, and cannot be dequeued;

[0078] The updated queue status is:

[0079] 1) Write request 1, RO = 0; send, not out of queue

[0080] 2) Write request 2, RO = 1; sent, unable to dequeue

[0081] 3) Read request 0, RO = 1; sent, unable to dequeue

[0082] 4) Write request 3, RO = 1; head of the queue

[0083] 5) Read request 1, RO = 0;

[0084] Currently, the 4th write request 3 is in loose order, at the head of the queue, sent, and cannot be dequeued;

[0085] The updated queue status is:

[0086] 1) Write request 1, RO = 0; send, not out of queue

[0087] 2) Write request 2, RO = 1; sent, unable to dequeue

[0088] 3) Read request 0, RO = 1; sent, unable to dequeue

[0089] 4) Write request 3, RO=1; sent, cannot be dequeued

[0090] 5) Read request 1, RO = 0; head of line

[0091] The current read request 1 (5th) is a strong order-preserving request, not a real head of queue, and is not sent or dequeued;

[0092] Waiting 1) After all the write responses matching write request 1 are received, write request 1 is dequeued, write request 2, read request 0, and write request 3 are all sent, and RO is 1, and all are dequeued. At this time, the queue status is:

[0093] 1) Read request 1, RO = 0; head of the queue

[0094] The current read request 1 is the real head of the queue and can be sent, and it will be dequeued after waiting for the response to return.

[0095] A multi-source request hierarchical order preservation method based on a PCIE interface of the present invention performs secondary order preservation processing on write requests and write responses in data instructions without an RO flag in the following manner:

[0096] Write the write request without RO mark into the reordering buffer according to the channel number and configuration. The reordering buffer is a FIFO memory. The write request carries the current tail mark (reordering buffer flag) of the reordering buffer. The write request is unpacked and the number of unpacked requests is recorded in the corresponding entry of the reordering buffer.

[0097] Write the write response without RO mark into the reordering buffer according to the channel number and configuration, until all the unpacked write requests in the reordering buffer correspond to the write response, and the write response in the reordering buffer is activated and can be sent.

[0098] For example, a write request 1 is received from Channel 0 (such as Figure 4As shown in the data instruction 5 before writing into the fifo, at this time, the tail pointer of Chanel 0 reordering buffer is 0, and the write request 1 carries the tail pointer tp=0 (as shown in the Figure 5 As shown, after writing the data instruction 6 into the fifo, the data instruction 6 has no Tp flag, TP is the tail pointer of the control queue), the write request 1 enters the subsequent logic, the tail pointer of the Channel 0 reordering buffer is increased by 1, tp = 1;

[0099] Afterwards, a write request 2 is received from Chanel 0. At this time, the tail pointer of Chanel 0 reordering buffer is 2. Write request 2 carries tail pointer tp=1. Write request 1 enters the subsequent logic. The tail pointer of Channel 0 reordering buffer is increased by 1, tp=2.

[0100] The above write request is split and sent out, and the write response is received out of order after the write is completed:

[0101] First, the write response of write request 2 of Channel 0 is collected. However, at this time, write request 2 carries tail pointer tp=1, which is not at the head of the queue of the reordering buffer and cannot be dequeued, that is, it cannot be sent.

[0102] Afterwards, the write responses of Channel0's write request 1 are collected. At this time, write request 1 carries tail pointer tp=0 and can be dequeued at the head of the reordering buffer queue. Write response 1 is issued and the queue head pointer +1;

[0103] Finally, the write request 2 of Channel 0 carries the tail pointer tp=1, which is the queue head of the reordering buffer and can be dequeued, and the write response 2 is issued.

[0104] A multi-source request hierarchical order preservation method based on a PCIE interface of the present invention performs a first-level order preservation process on a read request and a read response in a data instruction without an RO flag in the following manner:

[0105] Write the read request without RO flag into the receiving buffer according to the channel number. According to the request address and length, the read request is split into multiple requests and suspended in the buffer respectively. Each read request carries the channel flag flag and the suspended buffer number. Set the channel flag tag + 1, prepare to receive the next read request, and issue a read request carrying the channel flag flag.

[0106] Write the read response without RO flag into the receiving buffer according to the channel number. The read response carries the channel flag flag and the suspended buffer number. The read response is matched with the read request according to the channel flag flag and the suspended buffer number. From the channel flag flag = 0 to the last channel flag, the matched read responses are sent in sequence, and the channel flag tag + 1 is set to prepare for receiving the next read response.

[0107] When the channel flag of the channel number is 0, the channel is idle.

[0108] For example, in the initial state, channel 0 requests flag to be 0. After Chanel 0 inputs read request 1, read request 1 carries flag = 0 and enters the subsequent logic. Chanel 0 requests flag + 1. At this time, Chanel 0 requests flag to be updated to 1.

[0109] In the subsequent logic, the read request 1 of Chanel 0 is split into: read request 1-0, read request 1-1, etc. The flags carried by this group of read requests 1 are all 0;

[0110] Chanel 0 continues to input read request 2, which carries flag = 1 and is sent to the subsequent logic. Chanel 0 requests flag to be increased by 1. At this time, Chanel 0 requests flag to be updated to 2.

[0111] In the subsequent logic, the read request 2 of Chanel 0 is split into: read request 2-0, read request 2-1, etc. The flags carried by this group of read requests 1 are all 1;

[0112] Afterwards, read responses are returned out of order:

[0113] Chanel 0 read request 2-1

[0114] Chanel 0 read request 1-0

[0115] …

[0116] Chanel 0 read request 2-0, so far, the read response 2 matching Chanel 0's read request 2 is collected before the read response 1. Because the matched read responses need to be sent in order from flag = 0 to the last channel flag, currently channel 0 can only send the read response 1 with flag 0, so the read response 2 matching Chanel 0 read request 2 (flags are all 1) cannot be sent, and must wait for the read response 1 matching Chanel 0 read request 1 to be collected and sent before sending;

[0117] The read response continues to return:

[0118] Chanel 0 read request 1-2

[0119] Chanel 0 read request 1-0

[0120] At this time, the read response 1 of Chanel 0 read request 1 is collected and sent, the read response flag of Chanel 0 + 1 matches the response flag of Chanel 0 request 1, and the Chanel 0 request 1 response is sent.

[0121] The first-level order preservation process can also be further logically configured. The PCIE interface is provided with a configuration register. The first-level order preservation process is provided with a configuration logic. The configuration logic is stored in the configuration register and is used to record whether different types of read requests are subjected to the first-level order preservation process.

[0122] When different types of read requests are sent from different channels, the read requests carry different channel numbers. The configuration logic selects the read requests that meet the preservation conditions and performs first-level order preservation processing.

[0123] The read responses corresponding to the read requests that do not meet the storage conditions can be returned after all are collected.

Claims

1. A multi-source request hierarchical order preservation method based on PCIE interface, characterized in that: The data instruction carries the instruction body, channel number Chanel, configuration Type, read / write flag, and optionally carries the RO flag. The RO flag is a flag defined in the PCIE specification. The PCIE interface divides the data instruction into read request, write request, read response, and write response based on the read / write flag. The PCIE interface processes data instructions in a hierarchical manner according to the read / write flag and the RO flag; The PCIE interface is equipped with a sequence buffer, a reorder buffer, and a receive buffer; For data instructions with RO mark, three-level order preservation is performed, for write request and write response in data instructions without RO mark, two-level order preservation is performed, for read request and read response in data instructions without RO mark, one-level order preservation is performed; For data instructions carrying the RO flag, three-level order preservation processing is performed in the following manner: The order-preserving buffer is used to temporarily store and process data instructions with the RO flag, where: Read / write requests with the RO flag are directly stored in the order-preserving buffer; The read / write response carrying the RO flag directly enters the order-preserving buffer and is matched with the read / write instructions temporarily stored in the order-preserving buffer. This method enables the read / write response carrying the RO flag to be transmitted efficiently and enables the data instructions carrying the RO flag to be processed quickly. For write requests and write responses in data instructions without the RO flag, secondary order preservation is performed in the following manner: The reorder buffer is used to temporarily store and process write requests and write responses in data instructions without RO flags; Write requests without RO flags are written into the reordering buffer according to the channel number and configuration, and carry the current tail mark of the reordering buffer. The write request is unpacked, and the number of unpacked packets is recorded in the corresponding entry of the reordering buffer; The write response without RO flag is written into the reordering buffer according to the channel number and configuration, until the unpacked write request in the reordering buffer is completed with the write response, and the write response in the reordering buffer is activated and can be sent; For read requests and read responses in data instructions without the RO flag, the first-level order preservation is performed in the following manner: The read request without RO flag is written into the receiving buffer according to the channel number and carries the channel flag flag, sets the channel flag tag + 1, prepares to receive the next read request, and issues a read request carrying the channel flag flag; The read response without the RO flag is written into the receiving buffer according to the channel number. The read response carries the channel flag flag. The read response is matched with the read request in the receiving buffer. From the channel flag flag = 0 to the last channel flag, the matched read responses are sent in sequence, and the channel flag tag + 1 is set to prepare for receiving the next read response.

2. The multi-source request hierarchical order preservation method based on PCIE interface as claimed in claim 1, characterized in that: During the first-level order preservation process, read requests and read responses are matched in the following way: The read request of the receiving buffer is split into multiple requests according to the request address and length, and the buffers are suspended separately. Each read request carries the channel flag and the suspended buffer number. The read response received from the buffer carries the channel flag and the suspended buffer number, and the read response is matched with the read request based on the channel flag and the suspended buffer number.

3. The multi-source request hierarchical order preservation method based on PCIE interface as claimed in claim 1, characterized in that: The PCIE interface is provided with a configuration register, and the first-level order preservation processing is provided with a configuration logic, and the configuration logic is stored in the configuration register and is used to record whether different types of read requests are subjected to the first-level order preservation processing; When different types of read requests are sent from different channels, the read requests carry different channel numbers. The configuration logic selects the read requests that meet the preservation conditions and performs first-level order preservation processing. The read responses corresponding to the read requests that do not meet the storage conditions can be returned after all are collected.

4. The PCIE interface-based multi-source request hierarchical order preservation method according to claim 1, characterized in that: The reorder buffer is a flip-flop FIFO.

5. The multi-source request hierarchical order preservation method based on PCIE interface as claimed in claim 1, characterized in that: The maximum value of the read request length is 2KB.

6. The PCIE interface-based multi-source request hierarchical order preservation method according to claim 1, characterized in that: The PCIE interface is provided with an order-preserving buffer, and the order-preserving buffer is provided with a buffer depth, and the buffer depth is set according to the emulated memory delay.

7. The multi-source request hierarchical order preservation method based on PCIE interface as claimed in claim 1, characterized in that: The RO flag is a 1-bit flag.

8. The PCIE interface-based multi-source request hierarchical order preservation method according to claim 1, characterized in that: The RO flag is random and can be configured according to application requirements.

9. The PCIE interface-based multi-source request hierarchical order preservation method according to claim 1, characterized in that: The optional values ​​of the RO flag are 0 and 1. During the three-level order preservation processing, the read / write request and the read / write response are matched in the following manner: Identify the read / write request with RO flag 0 as strong order preservation. The read / write request with RO flag 0 must be issued at the head of the order preservation buffer queue. The read / write request with RO flag 0 can be dequeued from the order preservation buffer queue only after the corresponding read / write response is received. The read / write request with RO flag of 1 is identified as loose order. The read / write request with RO flag of 1 can be issued immediately after the preceding read / write request is issued. The read / write request with RO of 1 can be immediately dequeued from the order-preserving buffer queue if the packet has been sent and the preceding request does not block the unfinished RO of 0.

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