Method and system for controlling wafer gate oxide thickness

Abstract

The application discloses a method and system for controlling wafer gate oxide layer thickness, wherein the method comprises the following steps: forming a hard mask layer on each wafer in the same processing batch; obtaining processing position information of each wafer in the same processing batch; determining a wafer at a preset processing position according to the processing position information of each wafer in the same processing batch; removing the hard mask layer on the wafer back of the wafer at the preset processing position; and forming a gate oxide layer on the wafer surface of each wafer in the same processing batch. The above scheme can improve the wafer gate oxide layer thickness consistency in the same processing batch.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor technology, and in particular to a method and system for controlling the thickness of a wafer gate oxide layer. Background Technology

[0002] In the manufacturing process of metal-oxide-semiconductor (MOS) devices, the gate oxide layer is a very important dielectric layer, and its thickness has a significant impact on the threshold voltage and saturation current of MOS devices.

[0003] During the process of forming the gate oxide layer on the wafer, it was found that the thickness of the gate oxide layer on the wafers of the same processing batch sometimes did not meet the requirements, and the thickness of the gate oxide layer formed on some wafers was too small.

[0004] Currently, the thickness variation of the gate oxide layer formed on the wafer surface is usually reduced by adjusting the process parameters for forming the gate oxide layer or by extending the time for removing the hard mask layer.

[0005] However, both of the above methods have certain limitations. For example, adjusting the process parameters for forming the gate oxide layer can affect the growth of gate oxide layers on other wafer surfaces; extending the time for removing the hard mask layer may result in over-etching, affecting the performance of the final device.

[0006] In summary, how to improve the consistency of wafer gate oxide layer thickness in the same processing batch is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, embodiments of this specification provide a method and system for controlling the thickness of a wafer gate oxide layer, which can improve the consistency of the wafer gate oxide layer thickness in the same processing batch.

[0008] First, embodiments of this specification provide a method for controlling the thickness of a wafer gate oxide layer, including:

[0009] A hard mask layer is formed on each wafer in the same processing batch;

[0010] Obtain the actual processing location information of each wafer in the same processing batch;

[0011] Based on the actual processing position information of each wafer in the same processing batch, the wafer in the preset processing position is determined, and the hard mask layer on the back of the wafer in the preset processing position is removed.

[0012] Gate oxide layers are formed on the crystal surfaces of each wafer in the same processing batch.

[0013] Optionally, obtaining the actual processing position information of each wafer in the same processing batch includes: obtaining the actual processing position information of the corresponding wafer in the same processing batch according to the identification information of the wafer transfer box, wherein the wafer transfer box is used to transfer the wafers loaded on it to the process equipment, and the identification information of the wafer transfer box is used to characterize the processing position of the wafer transfer box on the process equipment.

[0014] Optionally, the process equipment includes a chemical vapor deposition furnace tube;

[0015] The formation of a hard mask layer on a wafer in the same processing batch includes: obtaining the hard mask layer on each wafer using a furnace tube low-pressure chemical deposition process.

[0016] Optionally, removing the hard mask layer on the back of the wafer at the preset processing position includes: removing a hard mask layer of a preset thickness on the back of the wafer at the preset processing position.

[0017] Optionally, removing the hard mask layer on the corresponding wafer backplane includes:

[0018] A wet etching process is used to remove the hard mask layer of a predetermined thickness on the back of the wafer at the predetermined processing position.

[0019] Optionally, the parameters of the wet etching process include: the etching solution is obtained by mixing a 40%-49% hydrogen fluoride solution and a 40%-60% nitric acid solution in a ratio of 1:5 to 1:200, and the process temperature is 20°C to 50°C.

[0020] Optionally, the parameters of the wet etching process include: the etching solution is obtained by mixing a 70%-85% phosphoric acid solution and water in a ratio of 1:0 to 1:100, and the process temperature is 80°C to 160°C.

[0021] Optionally, before removing the hard mask layer on the back of the wafer at the preset processing position, the method includes: forming trenches in the hard mask layer on the wafer surface of each wafer in the same processing batch, wherein the bottom of the trench is located inside the wafer;

[0022] The groove is filled and then annealed.

[0023] Optionally, forming a gate oxide layer on the crystal surface of each wafer in the same processing batch includes: first forming a gate oxide layer on the crystal surface of each wafer in the same processing batch that is not in the preset processing position; and then forming a gate oxide layer on the crystal surface of each wafer in the same processing batch that is in the preset processing position.

[0024] Optionally, forming a gate oxide layer on the crystal surface of each wafer in the same processing batch includes: removing the hard mask layer on the crystal surface and back surface of each wafer in the same processing batch; performing a trap implantation process on the crystal surface of each wafer in the same processing batch; and forming a gate oxide layer on the crystal surface of each wafer in the same processing batch.

[0025] Accordingly, embodiments of this specification also provide a system for controlling the thickness of a wafer gate oxide layer, comprising: a control device, and a first deposition device, a gate oxide layer formation subsystem, and a first etching device, respectively coupled to the control device, wherein:

[0026] The first deposition apparatus is adapted to form a hard mask layer on each wafer in the same processing batch;

[0027] The control device is adapted to acquire the actual processing position information of each wafer in the same processing batch; and to determine the wafer in the preset processing position based on the actual processing position information of each wafer.

[0028] The first etching apparatus is adapted to remove the hard mask layer on the back of the wafer at the preset processing position;

[0029] The gate oxide layer forming subsystem is adapted to form gate oxide layers on the crystal faces of each wafer in the same processing batch.

[0030] Optionally, the gate oxide layer formation subsystem includes: a second etching apparatus adapted to remove the hard mask layer on the crystal face and back face of each wafer in the same processing batch;

[0031] A trap implantation device suitable for performing trap implantation processes on the crystal faces of each wafer in the same processing batch;

[0032] The second deposition apparatus is adapted to form gate oxide layers on the crystal surfaces of each wafer in the same processing batch.

[0033] By employing the scheme for controlling the thickness of the wafer gate oxide layer provided in the embodiments of this specification, based on the actual processing position information of each wafer in the same processing batch, the wafer at the preset processing position can be determined, and the hard mask layer on the back of the wafer at the preset processing position can be removed. In this way, the gate oxide layer is formed on the crystal surface of each wafer in the same processing batch. This can reduce the impact of the residual hard mask layer on the back of the wafer at the preset processing position on the growth of the gate oxide layer on the crystal surface of other wafers in the same processing batch, thereby improving the consistency of the wafer gate oxide layer thickness in the same processing batch.

[0034] Furthermore, since the identification information of the wafer transfer box can characterize the processing position of the wafer transfer box on the process equipment, the actual processing position information of the corresponding wafer in the same processing batch can be obtained based on the identification information of the wafer transfer box. In this way, the correspondence between the actual processing position of the corresponding wafer in the same processing batch and the processing position inside the process equipment can be established. It is not necessary to set up special detection equipment in the equipment to obtain the actual processing position information of the corresponding wafer in the same processing batch, thereby reducing detection costs and improving production efficiency.

[0035] Furthermore, by removing the hard mask layer of a predetermined thickness on the back of the wafer at the predetermined processing position, it is possible to obtain a wafer back with uniformity after completely removing the hard mask layer of each wafer back in the same processing batch. This allows for the formation of a gate oxide layer with uniform thickness in subsequent processes, thereby improving the performance of the final semiconductor device.

[0036] Furthermore, when forming gate oxide layers on the crystal surfaces of each wafer in the same processing batch, the gate oxide layers are first formed on the crystal surfaces of each wafer in the same processing batch that are not in the preset processing position, and then the gate oxide layers are formed on the crystal surfaces of each wafer in the same processing batch that are in the preset processing position. Through such a step-by-step processing sequence, the continuity of the gate oxide layer formation steps on the crystal surfaces of each wafer in the same processing batch can be improved, thereby improving the overall production efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1A and Figure 1B A schematic diagram of the semiconductor structure formed in the same processing batch is shown;

[0039] Figure 2 A flowchart illustrating a method for controlling the thickness of a wafer gate oxide layer according to an embodiment of this specification is shown;

[0040] Figure 3 A flowchart is shown illustrating a method for controlling the thickness of a wafer gate oxide layer in a specific application scenario according to an embodiment of this specification.

[0041] Figures 4 to 13 This specification illustrates a method for forming a gate oxide layer according to an embodiment.

[0042] Figure 14 A schematic diagram of a control system for controlling the thickness of a wafer gate oxide layer is shown in an embodiment of this specification. Detailed Implementation

[0043] As described in the background art, currently, when forming a gate oxide layer on a wafer, the thickness of the gate oxide layer on wafers in the same processing batch sometimes does not meet the requirements, and the thickness of the gate oxide layer formed on some wafers is too small.

[0044] After analysis, the inventors discovered that during the formation of the gate oxide layer, when using Chemical Vapor Deposition (CVD) to form the hard mask layer, hard mask layers are formed on both the crystal face and the back face of the wafer. However, during actual processing, the etching rate of the hard mask layer on the back face of some wafers decreases, and the hard mask layer on the back face cannot be completely removed. In the final step of forming the gate oxide layer, the hard mask layer remaining on the back face of the wafer absorbs some heat, which in turn affects the growth of the gate oxide layer on other wafers. This results in a thinner gate oxide layer on other wafers, causing inconsistent gate oxide layer thicknesses on the crystal faces of wafers in the same batch of processing, thus affecting the performance of semiconductor devices.

[0045] When a gate oxide layer is formed on the top of each wafer substrate 10 in the same processing batch, there may be mutual interference between different wafers. For example, refer to Figure 1A and Figure 1B ,in, Figure 1A The diagram shows some semiconductor structures in the same processing batch that are in the process of formation. Figure 1B This diagram shows schematic representations of other semiconductor structures in the same processing batch that are still in the process of formation. Figure 1A The bottom of the intermediate substrate 10 still has a hard mask layer 12. The residual hard mask layer 12 will absorb heat, thus affecting... Figure 1B The growth of the gate oxide layer 15B on the upper part of the substrate 10 enables... Figure 1B The thickness of the 15B oxide layer in the middle gate is less than Figure 1A The thickness of the 15A gate oxide layer.

[0046] Continue to refer to Figure 1A and Figure 1B The semiconductor structure also includes an isolation trap 14.

[0047] To address the aforementioned technical problems, embodiments of this specification provide a method for controlling the thickness of a wafer gate oxide layer. Based on the actual processing position information of each wafer in the same processing batch, wafers at preset processing positions can be identified, and the hard mask layer on the back of the wafer at the preset processing position is removed. This allows gate oxide layers to be formed on the crystal surfaces of each wafer in the same processing batch. This reduces the impact of the residual hard mask layer on the back of the wafer at the preset processing position on the growth of gate oxide layers on the crystal surfaces of other wafers, thereby improving the consistency of the wafer gate oxide layer thickness in the same processing batch.

[0048] To enable those skilled in the art to have a clearer understanding of the technical concepts, principles, advantages, etc. contained in the embodiments of the present invention, the following detailed description is provided with reference to the accompanying drawings, through specific embodiments, and in conjunction with specific application scenarios.

[0049] Reference Figure 2 The flowchart shown in this embodiment illustrates a method for controlling the thickness of a wafer gate oxide layer. Specifically, in this embodiment, the gate oxide layer can be formed on the wafer according to the following steps:

[0050] S21, a hard mask layer is formed on each wafer in the same processing batch.

[0051] In practical implementation, different deposition processes can be used to form hard mask layers on each wafer in the same processing batch, depending on the actual application scenario.

[0052] As an optional example, in the embodiments of this specification, a hard mask layer can be formed on the crystal face and crystal back of each wafer in the same processing batch using a chemical vapor deposition process. Here, the crystal face of the wafer refers to the side where the gate oxide layer will ultimately be formed, and the crystal back refers to the side opposite to the crystal face.

[0053] S22, Obtain the actual processing position information of each wafer in the same processing batch.

[0054] Specifically, during the process of forming the gate oxide layer on the wafer, different wafers are located at different processing positions on the machine.

[0055] S23, based on the actual processing position information of each wafer, determine the wafer in the preset processing position, and remove the hard mask layer on the back of the wafer in the preset processing position.

[0056] In practice, due to the structure of the wafer-holding device (e.g., furnace tube) in the wafer processing machine, the thickness of the hard mask layer on the back of the wafer at different processing positions may vary. For example, the thickness of the hard mask layer on the back of a wafer at a specific position may be thicker than the thickness of the hard mask layer on the back of wafers at other positions in the same batch. Therefore, when a wafer is identified as being at a predetermined processing position, the hard mask layer on the back of the wafer at that predetermined processing position can be removed first.

[0057] As an optional example, a hard mask layer of a predetermined thickness on the back of the wafer at the predetermined processing position can be removed.

[0058] S24, a gate oxide layer is formed on the crystal surface of each wafer in the same processing batch.

[0059] In practice, depending on the actual application scenario, different oxidation processes can be used to form gate oxide layers on each wafer in the same processing batch.

[0060] As an alternative example, a furnace tube thermal oxidation process or a rapid thermal oxidation process can be used to form a gate oxide layer on the crystal surface of each wafer in the same processing batch.

[0061] It should be noted that, provided there is no conflict between the above steps, steps S21 and S22 can be executed simultaneously, or step S22 can be executed first, followed by step S21. The embodiments in this specification do not limit the execution order of steps S21 and S22, as long as steps S21 and S22 are executed before step S23.

[0062] Therefore, by removing the hard mask layer on the back of the wafer at the preset processing position, the influence of the residual hard mask layer on the back of the wafer at the preset processing position on the growth of the gate oxide layer on the surface of other wafers in the same processing batch can be reduced, thus improving the consistency of the gate oxide layer thickness in the same processing batch.

[0063] To enable those skilled in the art to better understand and implement the methods for controlling the thickness of the wafer gate oxide layer in the embodiments of this specification, the methods for controlling the thickness of the wafer gate oxide layer in the embodiments of this specification will be described in detail below with reference to the accompanying drawings. (Refer to...) Figure 3 The flowchart of a method for controlling the thickness of a wafer gate oxide layer in a specific application scenario described in the embodiments of this specification is shown. In some embodiments of this specification, the gate oxide layer can be formed on the wafer according to the following steps:

[0064] S31, a hard mask layer is formed on each wafer in the same processing batch.

[0065] In actual production and manufacturing processes, process equipment including chemical vapor deposition furnace tubes can be used. Accordingly, the formation process of hard mask layers on each wafer in the same processing batch can be carried out in chemical vapor deposition furnace tubes.

[0066] Using low-pressure chemical vapor deposition in a chemical vapor deposition furnace tube can deposit a hard mask layer of uniform thickness on both the back and face of the wafer.

[0067] In some embodiments of this specification, the material forming the hard mask layer may include silicon nitride. S32, trenches are formed on the hard mask layer on each wafer face in the same processing batch.

[0068] The bottom of the trench is located inside the wafer.

[0069] In a specific implementation, when forming trenches on the hard mask layer on each wafer crystal surface in the same processing batch, a mask layer can first be formed above the hard mask layer on the wafer crystal surface. The mask layer has an opening that exposes the hard mask layer above the wafer crystal surface. Using the mask layer as a mask, the hard mask layer and the wafer crystal surface are etched sequentially to obtain the trenches.

[0070] S33, fill the groove and perform an annealing process.

[0071] In practice, different deposition methods can be used to fill the trenches, depending on the usage of the process equipment and the actual processing requirements. For example, as optional examples, atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes can be used to fill the trenches. Afterward, the trenches undergo an annealing process, wherein, in some optional examples, the annealing temperature is between 1000°C and 1200°C.

[0072] After in-depth analysis, the inventors discovered that the etching rate of the hard mask layer on the back of some wafers slows down after the annealing process. This is due to the structure of the deposition equipment (e.g., chemical vapor deposition furnace tube). After annealing, the etching rate of the hard mask layer on the back of wafers located at specific locations on the deposition equipment is lower than that on wafers located at other locations on the deposition equipment.

[0073] Table 1 shows the etching rate changes of the hard mask layer on the wafer backside at different locations on the deposition equipment before and after the annealing process. Table 1 illustrates the etching rate changes of the hard mask layer on the wafer backside at three different locations (location A, location B, and location C) on the deposition equipment before and after the annealing process. Before annealing, the etching rates of the hard mask layer on the wafer backside at locations A, B, and C are 1, 0.99, and 0.99, respectively, showing a relatively consistent etching rate. After annealing, the etching rates of the hard mask layer on the wafer backside at locations A, B, and C all decrease, but the decrease is greatest at location C, significantly less than at locations A and B. This means that when the hard mask layer on the wafer backside is removed, some residue remains at location C, thus affecting the growth of the gate oxide layer on other wafer surfaces.

[0074] Processing position in the deposition machine Etching rate before annealing process Etching rate after annealing process A 1 0.76 B 0.99 0.73 C 0.99 0.65

[0075] Table 1

[0076] To avoid the residual hard mask on the back of the wafer affecting the growth of the gate oxide layer on the surface of other wafers, in the embodiments of this specification, the wafers can be processed differently based on the actual processing position information of each wafer in the same processing batch. An optional example is given below.

[0077] Continue to refer to Figure 3 Then, execute step S34 to obtain the actual processing position information of each wafer in the same processing batch.

[0078] In practice, since wafers are transported between different process equipment (e.g., deposition equipment, etching equipment, lithography equipment, etc.) via wafer transport boxes, the processing position of each wafer in the same batch can be determined by setting the processing position of the wafer transport box on the process equipment.

[0079] In some embodiments of this specification, the actual processing position information of the corresponding wafer in the same processing batch can be obtained based on the identification information of the wafer transfer box. The wafer transfer box is used to transfer the wafers it carries to the process equipment, and the identification information of the wafer transfer box is used to characterize the processing position of the wafer transfer box on the process equipment.

[0080] Specifically, since the identification information of the wafer transfer box is used to characterize the processing position of the wafer transfer box on the process equipment, once the identification information of the wafer transfer box is determined, the processing position of the wafer loaded inside it on the process equipment can be determined. In other words, the identification information of the wafer transfer box can establish a correspondence between the actual processing position of the corresponding wafer in the same processing batch and its processing position inside the process equipment. This eliminates the need for dedicated detection equipment on the equipment to obtain the actual processing position information of the corresponding wafer in the same processing batch, thereby reducing detection costs and improving production efficiency.

[0081] Step S35: Determine whether there is a wafer in the same processing batch that is in a preset processing position. If yes, proceed to step S36; otherwise, proceed to step S37.

[0082] Specifically, in step S34, the actual processing position of each wafer in the same processing batch can be determined by the identification information of the wafer transfer box.

[0083] As a specific example, wafer transfer boxes can be numbered, for example, 1, 2, 3, 4, 5, wherein wafer transfer box numbered 1 is located at processing position 1 in the process equipment, wafer transfer box numbered 2 is located at processing position 2 in the process equipment, and so on, wafer transfer box numbered 5 is located at processing position 5 in the process equipment.

[0084] If processing position 4 of the process equipment is the preset processing position, it means that the etching rate of the hard mask layer on the back of the wafer at processing position 4, after the annealing process, is less than the etching rate of the hard mask layer on the back of the wafer at processing positions 1-3 and processing position 5. Therefore, step S36 is executed for the wafer in wafer transport box number 4, and step S37 is executed directly for the wafers in wafer transport boxes numbered 1-3 and 5.

[0085] Step S36: Remove the hard mask layer of a preset thickness on the back of the wafer at the preset processing position in the same processing batch.

[0086] As mentioned earlier, due to the low etching rate of the hard mask layer on the back of the wafer at the preset processing position within the same processing batch, it is difficult to completely remove the hard mask layer on the back of the wafer at the preset processing position in subsequent processes, affecting the consistency of the gate oxide layer thickness on the wafers within the same processing batch. Therefore, a hard mask layer of a preset thickness can be removed from the back of the wafer at the preset processing position, wherein the preset thickness can be set according to the actual thickness of the hard mask layer formed. In specific implementation, a wet etching process can be used to remove the hard mask layer of the preset thickness on the back of the wafer at the preset processing position.

[0087] In the embodiments of this specification, according to the process requirements of the actual processing and manufacturing process, wet etching processes with different process parameters can be used to remove the hard mask layer of a preset thickness on the back of the wafer at the preset processing position.

[0088] As a specific example, the parameters of a wet etching process may include: the etching solution is prepared by mixing a 40%-49% hydrogen fluoride solution and a 40%-60% nitric acid solution in a ratio of 1:5 to 1:200, and the process temperature is 20°C to 50°C.

[0089] As another specific example, the parameters of a wet etching process may include: the etching solution is prepared by mixing a 70%-85% phosphoric acid solution and water in a ratio of 1:0 to 1:100, and the process temperature is 80°C to 160°C.

[0090] Therefore, by removing a hard mask layer of a predetermined thickness from the back of the wafer at a predetermined processing position, a consistent wafer back can be obtained after completely removing the hard mask layers from the backs of all wafers in the same processing batch. This results in a gate oxide layer of uniform thickness in subsequent processes, thereby improving the performance of the final semiconductor device.

[0091] In some other examples in this specification, a dry etching process can also be used to remove the hard mask layer on the wafer backside at a predetermined processing location. Using a dry etching process allows for precise control of the thickness of the hard mask layer removed from the wafer backside and reduces damage to other film layers.

[0092] By using steps S34 to S36 above, the wafer at the preset processing position can be determined, and the hard mask layer on the back of the wafer at the preset processing position can be removed. Then, the process continues as described above. Figure 3 Step S37 can be executed, in which gate oxide layers can be formed on the crystal surfaces of each wafer (including wafers in the preset processing position and wafers not in the preset processing position) in the same processing batch.

[0093] In specific implementation, since step S36 is only performed on wafers at the preset processing position, although a gate oxide layer is formed on the crystal surface of the wafer when step S37 is performed, in the actual manufacturing process, the gate oxide layer can be formed sequentially on wafers that have not performed step S36 and wafers that have performed step S36. That is, the gate oxide layer is first formed on the crystal surface of each wafer in the same processing batch that is not at the preset processing position, and then the gate oxide layer is formed on the crystal surface of each wafer in the same processing batch that is at the preset processing position.

[0094] Therefore, when forming gate oxide layers on the crystal surfaces of each wafer in the same processing batch, gate oxide layers are first formed on the crystal surfaces of each wafer in the same processing batch that are not in the preset processing position, and then gate oxide layers are formed on the crystal surfaces of each wafer in the same processing batch that are in the preset processing position. Through such a step-by-step processing sequence, the continuity of the steps for forming gate oxide layers on the crystal surfaces of each wafer in the same processing batch can be improved, thereby improving the overall production efficiency.

[0095] It is understandable that, in specific implementations, step S37 can be performed on wafers of the same processing batch together after the hard mask layer of a certain thickness on the back of the wafer at the preset processing position has been removed.

[0096] Continue to refer to Figure 3 In specific implementation, step S37 may include steps S371, S372 and S373.

[0097] First, step S371 can be performed to remove the hard mask layer on the crystal face and back face of each wafer in the same processing batch. Next, step S372 is performed to perform a trap implantation process on the crystal face of each wafer in the same processing batch. Then, step S373 is performed to form a gate oxide layer on the crystal face of each wafer in the same processing batch.

[0098] In step S371, in some embodiments of this specification, a wet etching process can be used to remove the hard mask layer on the crystal face and back of each wafer in the same processing batch.

[0099] For step S372, different types of isolation traps can be obtained through the trap injection process.

[0100] As an alternative example, a PMOS isolation trap can be obtained when the implanted ions are N-type ions, such as P ions, As ions, or Sb ions.

[0101] As another alternative example, an NMOS isolation trap can be obtained when the implanted ions are P-type ions, such as B ions, Ga ions, or In ions.

[0102] For step S373, in a specific implementation, a gate oxide layer can be formed on the crystal surface of each wafer in the same processing batch using a furnace tube thermal oxidation process or a rapid thermal oxidation process. Depending on the actual processing requirements, the gate oxide layer can be formed using a furnace tube dry thermal oxidation process or a furnace tube wet thermal oxidation process.

[0103] To enable those skilled in the art to better understand and implement the embodiments of this specification, the following is combined with Figures 3 to 13 The process of forming a gate oxide layer on a wafer in the embodiments of this specification is illustrated by example.

[0104] For step S31, please refer to Figure 4 and Figure 5 The process shown forms a hard mask layer on each wafer in the same processing batch.

[0105] Reference Figure 4 A substrate 100 is provided, which serves as a process platform for the subsequent formation of MOS devices.

[0106] In some embodiments of this specification, the substrate 100 has an active region ( Figure 4 (Not indicated), wherein the active region is used to form different types of isolation traps in subsequent processes.

[0107] In a specific embodiment, the substrate 100 may include a silicon substrate. In other embodiments, the substrate 100 may also include substrates of other materials such as germanium substrates, silicon germanide substrates, silicon carbide substrates, gallium arsenide substrates, or indium gallium dihydrogen phosphate substrates. The substrate may also include other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0108] It should be noted that, in the embodiments of this specification, the substrate 100 may be a part of a wafer, wherein the upper part of the substrate 100 corresponds to the crystal face of the wafer, and the bottom part of the substrate 100 corresponds to the crystal back of the wafer.

[0109] Reference Figure 5 Hard mask layers 102 are formed on the upper and lower parts of the substrate 100.

[0110] In practice, a furnace tube low-pressure chemical deposition process can be used to form a hard mask layer 102 on the upper and lower parts of the substrate 100.

[0111] In the embodiments described in this specification, the material of the hard mask layer 102 may include silicon nitride.

[0112] It should be noted that, continuing to refer to Figure 5 When forming a hard mask layer 102 on the upper and lower parts of the substrate 100, an interlayer dielectric layer 101 may optionally be formed on the upper and lower parts of the substrate 100, and then the hard mask layer 102 is formed on the interlayer dielectric layer 101.

[0113] In the embodiments described in this specification, the material of the interlayer dielectric layer 101 can be an insulating material. Specifically, the material of the interlayer dielectric layer 101 may include silicon dioxide. Silicon dioxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and implementation cost of forming the interlayer dielectric layer 101.

[0114] For step S32, please refer to Figure 6 and Figure 7 The process shown forms trenches on the hard mask layer on the crystal surface of each wafer in the same processing batch.

[0115] Reference Figure 6 A mask layer 103 is formed above a hard mask layer 102 located on the upper part of the substrate 100. The mask layer 103 has an opening 104 that exposes the hard mask layer 102 located on the upper part of the substrate 100.

[0116] In specific implementation, the mask layer 103 can be formed using a chemical vapor deposition process.

[0117] In some embodiments of this specification, the mask layer 103 needs to be removed subsequently; therefore, the mask layer 103 can be made of a material that is easily removed. Spin-on carbon (SOC) materials are low in cost, have a simple formation process, high process compatibility, and good filling performance, making them easy to remove. Therefore, the material of the mask layer 103 may include SOC materials.

[0118] In other embodiments, the material of the mask layer 103 may also be an organic dielectric layer (ODL), a deep UV light absorbing oxide (DUO), a dielectric anti-reflective coating (DARC), or a photoresist.

[0119] Reference Figure 7 Using the mask layer 103 as a mask, the hard mask layer 102 and the interlayer dielectric layer 101 located on the substrate 100 and the substrate 100 are etched sequentially to form a trench 105, the bottom of the trench 105 being located inside the substrate 100.

[0120] It should be noted that after the trench 105 is formed, the mask layer 103 needs to be removed. During the removal of the mask layer 103, a portion of the hard mask layer 102 located on the upper part of the substrate 100 will be consumed, resulting in the thickness of the hard mask layer 102 located on the upper part of the substrate 100 being less than the thickness of the hard mask layer 102 located at the bottom of the substrate 100.

[0121] For step S33, refer to Figure 8 and Figure 9 The groove is filled to form a filling layer 106.

[0122] Reference Figure 8An atomic layer deposition process is used to deposit a filling material over the trench, above the hard mask layer 102 located on the substrate 100.

[0123] The filling material is the same as that of the interlayer dielectric layer 101, which is silicon dioxide.

[0124] Reference Figure 9 Using the hard mask layer 102 located on the substrate 100 as the etching stop layer, the filling material is planarized to obtain the filling layer 106.

[0125] As mentioned earlier, when forming a hard mask layer using a furnace tube low-pressure chemical deposition process, the hard mask layer on the back of the wafer at the preset processing position is difficult to completely remove in subsequent etching processes, thus affecting the consistency of the gate oxide layer thickness of other wafers in the same processing batch. Therefore, when executing steps S34 and S35, it is determined that there are wafers at the preset processing position in the same processing batch, which can be referred to... Figure 10 Step S36 is executed to remove the hard mask layer 102 of a preset thickness located at the bottom of the substrate 100; when steps S34 and S35 are executed, and it is determined that there is no wafer in the same processing batch at the preset processing position, or after step S36 is executed, reference can be made to Figures 11 to 13 A gate oxide layer 110 is formed on the crystal surface of the wafer.

[0126] Reference Figure 10 A wet etching process is used to remove the hard mask layer 102 of a preset thickness at the bottom of the substrate 100 of the wafer located at a preset processing position.

[0127] As a specific example, the parameters of a wet etching process may include: the etching solution is prepared by mixing a 40%-49% hydrogen fluoride solution and a 40%-60% nitric acid solution in a ratio of 1:5 to 1:200, and the process temperature is 20°C to 50°C.

[0128] As another specific example, the parameters of a wet etching process may include: the etching solution is prepared by mixing a 70%-85% phosphoric acid solution and water in a ratio of 1:0 to 1:100, and the process temperature is 80°C to 160°C.

[0129] Continue to refer to Figure 10 By using a wet etching process to remove the hard mask layer 102 of a preset thickness located on the bottom substrate 100, the thickness of the hard mask layer at the bottom of the substrate 100 is less than the thickness of the hard mask layer located on the top of the substrate 100.

[0130] Reference Figure 11 Remove the interlayer dielectric layer and hard mask layer at the bottom and top of the substrate 100.

[0131] In the embodiments described in this specification, a wet etching process can be used to remove the interlayer dielectric layer 101 and the hard mask layer 102 at the bottom and top of the substrate 100. Specifically, a hot phosphoric acid solution and a front and back process can be used to remove the interlayer dielectric layer 101 and the hard mask layer 102 at the bottom and top of the substrate 100 simultaneously.

[0132] Continue to refer to Figure 11 Removing the hard mask layer 102 and interlayer dielectric layer 101 on the substrate 100 will consume a portion of the substrate 100, causing the top height of the substrate 100 to be lower than the height of the filler layer 106.

[0133] Reference Figure 12 A trap implantation process was performed on substrate 100.

[0134] Depending on the type of ions implanted, a corresponding type of isolation trap 107 can be formed inside the substrate 100.

[0135] For example, when the implanted ions are N-type ions, such as P ions, As ions, or Sb ions, a PMOS isolation trap can be obtained; when the implanted ions are P-type ions, such as B ions, Ga ions, or In ions, an NMOS isolation trap can be obtained.

[0136] In a specific implementation, at least one isolation well can be formed inside the substrate 100. For example, a PMOS isolation well or an NMOS isolation well can be formed inside the substrate 100, or both a PMOS isolation well and an NMOS isolation well can be formed simultaneously.

[0137] It should be noted that, Figure 12 Only a portion of the isolation trap is shown.

[0138] Reference Figure 13 A gate oxide layer 110 is formed on the substrate 100.

[0139] In a specific implementation, a furnace tube thermal oxidation process can be used to form a gate oxide layer 110 on the substrate 100 shown.

[0140] The height of the top of the gate oxide layer 110 is lower than the height of the top of the fill layer 106.

[0141] The embodiments in this specification also provide a control system capable of controlling the thickness of the wafer gate oxide layer as described above. To enable those skilled in the art to better understand and implement this system, a corresponding description is provided below in conjunction with the accompanying drawings.

[0142] Reference Figure 14 The schematic diagram of the control system shown is illustrated in some embodiments of this specification, such as... Figure 14As shown, the control system 140 may include a control device 141, and a first deposition device 142, a first etching device 143, and a gate oxide formation subsystem 144, all coupled to the control device 141, wherein:

[0143] The first deposition apparatus 142 is adapted to form a hard mask layer on each wafer in the same processing batch;

[0144] The control device 141 is adapted to acquire the actual processing position information of each wafer in the same processing batch; and to determine the wafer in the preset processing position based on the actual processing position information of each wafer.

[0145] The first etching apparatus 143 is adapted to remove the hard mask layer on the back of the wafer at the preset processing position;

[0146] The gate oxide layer forming subsystem 144 is adapted to form gate oxide layers on the crystal faces of each wafer in the same processing batch.

[0147] The following combination Figure 14 This section introduces the working principle of the control system 140.

[0148] Under the control of the control device 141, the first deposition device 142 can form a hard mask layer on each wafer in the same processing batch. Before forming the hard mask layer on each wafer in the same processing batch using the first deposition device 142, the control device 141 can obtain the actual processing position information of each wafer in the same processing batch, and determine the wafer in the preset processing position based on the actual processing position information of each wafer in the same processing batch, and output the processing position information of the wafer in the preset processing position to the first etching device 143. The etching device 143 can perform the process of removing the hard mask layer on the back of the wafer in the preset processing position. When the control device 141 receives the completion of removing the hard mask layer on the back of the wafer in the preset processing position, it controls the gate oxide layer formation subsystem 144 to form a gate oxide layer on the crystal surface of each wafer in the same processing batch.

[0149] Therefore, by removing the hard mask layer on the back of the wafer at the preset processing position, the growth of the gate oxide layer on other wafer surfaces can be reduced due to the residual hard mask layer on the back of the wafer at the preset processing position, thereby improving the consistency of the gate oxide layer thickness in the same processing batch.

[0150] In some embodiments of this specification, the control device can obtain the actual processing position information of the corresponding wafer in the same processing batch based on the identification information of the wafer transfer box.

[0151] Specifically, the control equipment selects the appropriate process equipment based on the operating status and production plan information of the process equipment (e.g., the first deposition equipment, the first etching equipment, and the gate oxide layer formation subsystem). Within the same processing batch, it identifies the wafer transport cassette loaded with wafers. The identification information of the wafer transport cassette characterizes its processing position within the process equipment. In other words, the control equipment can associate the identification information of the wafer transport cassette with the processing position within the process equipment. Furthermore, the wafer transport cassette can transport the wafers it carries to the process equipment. Therefore, based on the identification information of the wafer transport cassette, the control equipment can establish a correspondence between the actual processing position of the corresponding wafer within the same processing batch and the processing position within the process equipment. By judging the identification information of the wafer transport cassette, it can determine whether the actual processing position of the wafer is the preset processing position.

[0152] In some embodiments of this specification, the control device may be a machine automation processing module.

[0153] When the control equipment determines that there is a wafer at a preset processing position, the first etching equipment can remove a hard mask layer of a preset thickness on the back of the wafer at the preset processing position. For details, please refer to [link to relevant documentation]. Figure 10 This will not be elaborated upon here.

[0154] Subsequently, the gate oxide layer formation subsystem can form gate oxide layers on the crystal surfaces of each wafer (including wafers at preset processing positions and wafers not at preset processing positions) within the same processing batch. During the formation of the gate oxide layer, multiple different processing techniques are required. (Continue referring to...) Figure 14 The gate oxide layer formation subsystem 144 may include: a second etching apparatus 1441, adapted to remove the hard mask layer on the crystal face and back of each wafer in the same processing batch; a trap implantation apparatus 1442, adapted to perform a trap implantation process on the crystal face of each wafer in the same processing batch; and a second deposition apparatus 1443, adapted to form a gate oxide layer on the crystal face of each wafer in the same processing batch.

[0155] The process of forming a gate oxide layer on the crystal surface of a wafer using a gate oxide layer formation subsystem can be found in [reference needed]. Figures 11 to 13 The description of that will not be elaborated here.

[0156] It is understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with terms such as "first" and "second" may explicitly or implicitly include one or more of that feature. Furthermore, terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance. It is understood that such terms can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein.

[0157] While the embodiments disclosed in this specification are as described above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this invention; therefore, the scope of protection of this invention should be determined by the scope defined in the claims.

Claims

1. A method for controlling the thickness of a wafer gate oxide layer, characterized in that, include: A hard mask layer is formed on each wafer in the same processing batch; In the same processing batch, trenches are formed on the hard mask layer on the crystal surface of each wafer, wherein the bottom of the trench is located inside the wafer; The grooves are filled and then annealed. Obtain the actual processing location information of each wafer in the same processing batch; Based on the actual processing position information of each wafer in the same processing batch, wafers at preset processing positions are determined, and a hard mask layer of preset thickness is removed from the back of the wafer at the preset processing position. The preset processing position is defined as the processing position where, after the annealing process, the etching rate of the hard mask layer on the back of the wafer at the preset processing position is lower than the etching rate of the hard mask layer on the back of the wafer at other processing positions. Remove the hard mask layer from the crystal face and back of each wafer in the same processing batch; Trap implantation process is performed on the crystal faces of each wafer in the same processing batch; Gate oxide layers are formed on the crystal surfaces of each wafer in the same processing batch.

2. The method for controlling the thickness of the wafer gate oxide layer according to claim 1, characterized in that, The step of obtaining the actual processing position information of each wafer in the same processing batch includes: Based on the identification information of the wafer transfer box, the actual processing position information of the corresponding wafer in the same processing batch is obtained. The wafer transfer box is used to transfer the wafer it carries to the process equipment, and the identification information of the wafer transfer box is used to characterize the processing position of the wafer transfer box on the process equipment.

3. The method for controlling the thickness of the wafer gate oxide layer according to claim 2, characterized in that, The process equipment includes a chemical vapor deposition furnace tube; The formation of a hard mask layer on the wafer in the same processing batch includes: The hard mask layer on each wafer is obtained by a furnace tube low-pressure chemical deposition process.

4. The method for controlling the thickness of the wafer gate oxide layer according to claim 1, characterized in that, The step of pre-removing the hard mask layer of a predetermined thickness on the back of the wafer at the predetermined processing position includes: A wet etching process is used to remove the hard mask layer of a predetermined thickness on the back of the wafer at the predetermined processing position.

5. The method for controlling the thickness of the wafer gate oxide layer according to claim 4, characterized in that, The parameters of the wet etching process include: The etching solution is prepared by mixing a 40%-49% hydrogen fluoride solution and a 40%-60% nitric acid solution in a ratio of 1:5 to 1:200, and the process temperature is 20℃ to 50℃.

6. The method for controlling the thickness of the wafer gate oxide layer according to claim 4, characterized in that, The parameters of the wet etching process include: The etching solution is prepared by mixing a 70%-85% phosphoric acid solution and water in a ratio of 1:0 to 1:100, and the process temperature is 80℃ to 160℃.

7. The method for controlling the thickness of the wafer gate oxide layer according to claim 1, characterized in that, The formation of gate oxide layers on the crystal surfaces of each wafer in the same processing batch includes: First, a gate oxide layer is formed on the crystal surface of each wafer that is not in the preset processing position in the same processing batch; Then, a gate oxide layer is formed on the crystal surface of each wafer located at the preset processing position in the same processing batch.

8. A system for controlling the thickness of a wafer gate oxide layer, characterized in that, The method for controlling the thickness of a wafer gate oxide layer according to any one of claims 1 to 7, wherein the system for controlling the thickness of the wafer gate oxide layer comprises: a control device, and a first deposition device, a gate oxide layer formation subsystem, and a first etching device respectively coupled to the control device, wherein: The first deposition apparatus is adapted to form a hard mask layer on each wafer in the same processing batch; The control device is adapted to acquire the actual processing position information of each wafer in the same processing batch; and to determine the wafer in the preset processing position based on the actual processing position information of each wafer. The first etching apparatus is adapted to remove the hard mask layer on the back of the wafer at the preset processing position; The gate oxide layer forming subsystem is adapted to form gate oxide layers on the crystal faces of each wafer in the same processing batch; wherein: the gate oxide layer forming subsystem includes: a second etching apparatus, adapted to remove hard mask layers on the crystal faces and back faces of each wafer in the same processing batch; A trap implantation device suitable for performing trap implantation processes on the crystal faces of each wafer in the same processing batch; The second deposition apparatus is adapted to form gate oxide layers on the crystal surfaces of each wafer in the same processing batch.

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