A compound semiconductor circuit isolation structure and a compound semiconductor device containing the same

Abstract

The present invention relates to a compound semiconductor circuit isolation structure comprising an isolation trench, a barrier region formed below the isolation trench, and a contact layer. The bottom of the isolation trench is located in a substrate, and the barrier regions comprise at least two rows, each located adjacent to a compound device on either side. The barrier regions form a PN junction with the substrate, and the orthographic projection of the barrier regions from the bottom of the isolation trench to the top is located within the bottom region of the isolation trench. The orthographic projection of the contact layer from the top of the isolation trench to the bottom is located between the two rows of barrier regions or their orthographic projections, and its doping type is opposite to that of the barrier regions. The PN junction structure is electrically connected to a separate isolation potential and a ground potential, and isolation between two adjacent compound devices is achieved through the isolation trench and the PN junction. In this structure, the high-resistance space charge region generated by the PN junction does not change with changes in the potential within the circuit, thus stably blocking crosstalk paths between various circuit components. Furthermore, the potential used to achieve isolation is confined within the isolation trench by the barrier region, preventing it from affecting other circuit components.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a compound semiconductor circuit isolation structure and a compound semiconductor device containing the structure. Background Art

[0002] In order to further increase system frequency, reduce system size and lower system cost, compound semiconductor technology is developing towards monolithic integration. Effective device isolation is a prerequisite for the integration of high and low voltage circuits in circuits, and is of great significance to the development of power electronics technology based on compound semiconductors.

[0003] Existing compound semiconductor integrated circuit isolation schemes are mostly based on the following two principles: (1) using an insulating layer to block the high-side voltage path; (2) using the depletion region generated by the reverse bias of the PN junction to block the high-side voltage path. The former significantly changes the structure of the compound semiconductor substrate, causing problems with epitaxial quality and cost, and cannot achieve transient voltage suppression through the PN junction in the substrate; the latter, as a semiconductor electrical connection method, requires a specific structure and electrical topology to achieve blocking, and its inherent voltage-current characteristics and frequency characteristics make it difficult to block electrical signals in time under high electrical stress and high frequency conditions.

[0004] In addition, when the PN junction is reverse biased, it is necessary to extract carriers on both sides of the PN junction to establish a space charge region to withstand the reverse bias. During this process, the reverse bias voltage across the PN junction will not be established immediately, and the potential of the circuit node connected to the PN junction will be clamped. In the existing Backsurface technology (see Figure 1 ) and EBUS techniques (see Figure 2 ), the half-bridge connection node SW is the source of the high-side switch tube, which is directly connected to the unilateral mutation PN junction (or NP junction) below it. Theoretically, by reverse-biasing the PN junction (or NP junction), the high potential of the SW node can be prevented from causing crosstalk to the low-side switch tube when the high-side tube is turned on. However, when the voltage swing on the SW node causes the PN junction (or NP junction) to reverse bias, the SW node is affected by the clamping of the PN junction structure and will not immediately reach the connection level of the switch tube on the turned-on side. At this time, high voltage exists at both ends of the turned-on switch tube and it is subjected to short-circuit stress. If the short-circuit stress continues to accumulate, the switch tube will be damaged.

[0005] Therefore, it is of great significance to improve the PN junction isolation structure to overcome the above-mentioned problems in the prior art. Summary of the Invention

[0006] Based on the above description, the present invention provides a compound semiconductor circuit isolation structure, in which part of the high-resistance space charge region generated by the PN junction is connected to an independent isolation potential, does not change with the potential change in the circuit, can stably block the crosstalk path between the various parts of the circuit, and the potential used to achieve isolation is limited to the isolation groove by the blocking area, preventing it from affecting other parts of the circuit.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: a compound semiconductor circuit isolation structure, comprising an isolation trench and a barrier region and a contact layer formed below the isolation trench;

[0008] The bottom of the isolation trench is located in the substrate, the blocking areas have at least two columns and are respectively arranged close to the compound devices on both sides, the blocking areas form a PN junction with the substrate, the orthographic projection of the blocking areas along the bottom of the isolation trench to the top is located in the bottom area of ​​the isolation trench, the orthographic projection of the contact layer along the top of the isolation trench to the bottom is located between the two columns of blocking areas or their orthographic projections, and its doping type is opposite to the doping type of the blocking areas, the PN junction structures are electrically connected to a separate isolation potential and a ground potential through the blocking areas and the contact layer; the isolation structure achieves isolation of two adjacent compound devices through the isolation trench and the PN junction.

[0009] As a preferred embodiment, the substrate comprises a lightly doped layer, a high resistance layer, and a heavily doped layer in sequence from the bottom to the top of the isolation trench, and the isolation trench runs through all the heavily doped layers, the high resistance layer, and part of the lightly doped layers.

[0010] Specifically, the substrate includes N - Silicon layer, intrinsic silicon layer and N + silicon layer, the isolation trench penetrates all N + Silicon layer, all intrinsic silicon layer and part of N - Silicon layer; or, the substrate includes P - Silicon layer, intrinsic silicon layer and P + silicon layer, the isolation trench penetrates the entire P + Silicon layer, all intrinsic silicon layer and part of P - Silicon layer.

[0011] As a preferred embodiment, when the substrate is N-type doped, the barrier region is P+ doped, the contact layer is N+ doped, the barrier region is electrically connected to the ground potential, and the contact layer is electrically connected to the isolation potential.

[0012] As a preferred embodiment, when the substrate is P-type doped, the barrier region is N+-type doped, the contact layer is P+-type doped, the barrier region is electrically connected to the isolation potential, and the contact layer is electrically connected to the ground potential.

[0013] As a preferred embodiment, the barrier region and / or the contact layer are formed at the bottom of the isolation trench and extend toward the bottom of the substrate; or, the barrier region and / or the contact layer are formed at the bottom of the substrate and extend toward the bottom of the isolation trench.

[0014] As a preferred embodiment, the blocking areas are formed in four columns, and the four columns of blocking areas are symmetrically arranged in pairs, wherein one column of each pair of blocking areas is arranged at the bottom of the isolation groove and extends toward the substrate, and the other column is arranged at the edge of the substrate and extends toward the bottom of the isolation groove.

[0015] Another object of the present invention is to provide a compound semiconductor device, which includes a plurality of semiconductor devices based on the same substrate and the above-mentioned circuit isolation structure, wherein the circuit isolation structure is used for electrical isolation between adjacent semiconductor devices.

[0016] As a preferred embodiment, the device also includes a buffer layer, a channel layer and a barrier layer sequentially fabricated on the substrate, the isolation trench sequentially passes through the barrier layer, the channel layer and the buffer layer and extends to the substrate, the surface of the barrier layer and the isolation trench are filled with dielectric material; the semiconductor devices are respectively fabricated on both sides of the isolation trench.

[0017] As a preferred embodiment, the substrate is composed of a lightly doped layer, a high resistance layer, and a heavily doped layer in sequence from the bottom to the top of the isolation groove. The isolation groove runs through all the heavily doped layers, the high resistance layer, and part of the lightly doped layers. The source of the semiconductor device is electrically connected to the heavily doped layer in the substrate.

[0018] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0019] First, unlike the previous PN junction isolation method, which places the reverse-biased PN junction blocking structure below the compound device and connects one end of the PN junction (the heavily doped side) to the source of the compound device, this application places the PN junction structure that plays an isolation role in the isolation trench, keeping it away from the compound device, thereby reducing the impact of the PN junction switching process on the compound device;

[0020] Second, a bias voltage is used to keep the barrier region and the contact layer junction in a reverse bias state, forming a fixed space charge region in the crosstalk channel. This high-resistance space charge region does not change with the potential in the circuit, stably blocking the crosstalk path between various parts of the circuit;

[0021] Third, the potential V used to achieve isolation block The blocked area is confined to the isolation trench, preventing it from affecting other parts of the circuit;

[0022] Fourth, the PN junction between the barrier region and the contact layer is kept in a reverse bias state. When a space charge region is established between the source of the device and the barrier region, the PN junction between the barrier region and the contact layer can act as a charge channel, using the high electric field in the reverse biased PN junction to quickly extract minority carriers, thereby reducing the reverse recovery time.

[0023] Fifth, there is a certain potential drop on the high-resistance layer, which reduces the voltage borne by the blocking structure in the isolation trench; when the PN junction is in the reverse recovery process, the lower reverse bias voltage can reduce the time required for the reverse recovery process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural diagram of the Backsurface technology in the prior art;

[0025] Figure 2 It is a structural diagram of EBUS technology in the prior art;

[0026] Figure 3 is a cross-sectional view of a device having the isolation structure of the present invention;

[0027] Figure 4 are cross-sectional views of several other devices having the isolation structure according to the present invention;

[0028] Figure 5 Schematic diagram of the longitudinal section structure of the barrier zone with different structures;

[0029] Figure 6 is a horizontal cross-sectional view of the isolation trench, barrier region, and contact layer;

[0030] Figure 7 This is a process flow chart of an isolation structure according to an embodiment of the present invention.

[0031] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0032] 1 isolation trench, 2 barrier region, 3 contact layer, 4 substrate, 41 lightly doped layer, 42 intrinsic silicon layer, 43 heavily doped layer. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0035] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc., if the connected circuits, modules, units, etc. can transmit electrical signals or data to each other.

[0036] like Figure 3 As shown, a compound semiconductor circuit isolation structure includes an isolation trench 1 and a barrier region 2 and a contact layer 3 formed below the isolation trench 1. The bottom of the isolation trench 1 is located in a substrate 4. The barrier regions 2 have at least two columns and are arranged close to the compound devices on both sides. The barrier regions 2 form a PN junction with the substrate 4. The orthographic projection of the barrier regions 2 along the bottom to the top of the isolation trench 1 is located in the bottom area of ​​the isolation trench 1. The orthographic projection of the contact layer 3 along the top to the bottom of the isolation trench 1 is located between the two columns of barrier regions 2 or their orthographic projections, and its doping type is opposite to that of the barrier regions 2. The PN junction structures are electrically connected to a separate isolation potential and a ground potential through the barrier regions 2 and the contact layer 3. The isolation structure isolates two adjacent compound devices through the isolation trench 1 and the PN junction.

[0037] The compound semiconductor circuit isolation device provided by the present invention has at least the following advantages:

[0038] (1) Different from the previous PN junction isolation method that places the reverse biased PN junction blocking structure below the compound device and connects one end of the PN junction (the heavily doped end) to the source of the compound device, this method places the PN junction structure that plays an isolation role below the isolation trench, keeping it away from the compound device, thereby reducing the impact of the PN junction switching process on the compound device;

[0039] (2) A bias voltage is used to keep the PN junction in a reverse bias state, forming a fixed space charge region in the crosstalk channel. This high-resistance space charge region does not change with the potential change in the circuit, stably blocking the crosstalk path between the various circuit paths;

[0040] (3) Potential V used to achieve isolation block The blocked area is confined to the isolation trench, preventing it from affecting other parts of the circuit;

[0041] (4) The PN junction remains in a reverse biased state. When a space charge region is established between the source and the barrier region of the device, the barrier region and the contact layer can serve as a charge channel, using the high electric field in the reverse biased PN junction to quickly extract minority carriers and reduce the reverse recovery time.

[0042] In this isolation structure, the substrate 4 can be either an N-type substrate or a P-type substrate, and the doping types of the barrier region 2 and the contact layer 3 can be adjusted according to the doping type of the substrate 4 .

[0043] Specifically, if the substrate 4 is an N-type substrate, the barrier region 2 is doped with P-type and the contact layer 3 is doped with N-type; if the substrate 4 is a P-type substrate, the barrier region 2 is doped with N-type and the contact layer 3 is doped with P-type.

[0044] Furthermore, the substrate 4 may adopt a three-layer structure with different doping concentrations, wherein the middle layer may be a high-resistance layer 42, the upper layer may be a heavily doped layer 43, and the lower layer may be a lightly doped layer 41. For example, the substrate 4 may include N - Silicon layer, intrinsic silicon layer and N + silicon layer, the isolation trench penetrates all N + Silicon layer, all intrinsic silicon layer and part of N - or the substrate 4 includes P along the bottom of the isolation trench to the top direction in sequence - Silicon layer, intrinsic silicon layer and P + silicon layer, the isolation trench penetrates the entire P + Silicon layer, all intrinsic silicon layer and part of P - Silicon layer.

[0045] The advantage of using the high resistance layer 42 is that there is a certain potential drop on the high resistance layer 42, which reduces the reverse bias voltage borne by the blocking structure in the isolation trench. When the PN junction is in the reverse recovery process, the lower reverse bias voltage can reduce the time required for the reverse recovery process.

[0046] It can be understood that when the substrate 4 includes N - Silicon layer, intrinsic silicon layer and N + The silicon layer, the barrier region 2 is P+ doped, the contact layer 3 is N+ doped, the barrier region 2 is electrically connected to the ground potential through the electrode, and the contact layer 3 is electrically connected to the isolation potential V block Electrical connection.

[0047] When the substrate 4 includes P - Silicon layer, intrinsic silicon layer and P + The silicon layer, the barrier region 2 is N+ doped, the contact layer 3 is P+ doped, and the barrier region 2 is connected to the isolation potential V block Electrical connection: the contact layer 3 is electrically connected to the ground potential through the electrode.

[0048] Furthermore, the blocking area 2 can be made at the bottom of the isolation trench 1 and extend toward the bottom of the substrate 4, or it can be made at the bottom of the substrate 4 and extend toward the bottom of the isolation trench 1. Similarly, the contact layer 3 can be made at the bottom of the isolation trench 1 and extend toward the bottom of the substrate 4, or it can be made at the bottom of the substrate 4 and extend toward the bottom of the isolation trench 1. That is, in the solution of the present application, the horizontal relative position relationship between the blocking area 2 and the contact layer 3 is fixed, that is, the blocking area 2 is located on both sides below the isolation trench close to the isolated devices (circuits), and the contact layer 3 is located between the blocking areas 2, but there does not need to be strict central symmetry between the two. The contact layer can be biased toward a certain isolated area according to design requirements, and the vertical relationship between the blocking area 2 and the contact layer 3 can exist in various ways, for details, please refer to. Figure 4 .

[0049] Furthermore, in the isolation structure, the blocking areas can be made into two columns or multiple columns, such as four columns. When four columns are made, the four columns of blocking areas 2 are symmetrically arranged in pairs, wherein one column of each pair of blocking areas 2 is arranged at the bottom of the isolation groove 1 and extends toward the refrigerator substrate 4, and the other column is arranged at the edge of the substrate 4 and extends toward the bottom of the isolation groove 1.

[0050] It is understandable that the above-mentioned isolation structure is not only applicable to the combination of gallium oxide semiconductor material and substrate material, but also to the combination of gallium nitride semiconductor material and substrate material, and the devices above it are not limited to power HMET, but are also applicable to other types of power rectifiers, power switching tubes or integrated circuits.

[0051] It is also understood that the barrier region 2 can be formed in a variety of shapes and processes, such as a columnar structure formed by injection, a multi-level trench structure formed by etching multi-level trench injection, and the like. Figure 5 .

[0052] It can also be understood that, from the perspective of the planar layout of the formed structure, the barrier region 2 and the contact layer 3 can be either a continuous ring or a number of discrete regions connected by electrical connections. Figure 6 .

[0053] The present invention also provides a compound semiconductor device, which includes a plurality of semiconductor devices based on the same substrate and the above-mentioned circuit isolation structure, and the circuit isolation structure is used for electrical isolation between adjacent semiconductor devices.

[0054] Furthermore, it also includes a buffer layer, a channel layer and a barrier layer sequentially formed on the substrate 4, the isolation trench 1 sequentially penetrates the barrier layer, the channel layer and the buffer layer and extends into the substrate 4, the surface of the barrier layer and the isolation trench 1 are filled with dielectric material, and semiconductor devices are respectively formed on both sides of the isolation trench 1.

[0055] Furthermore, when the substrate 4 is composed of a lightly doped layer 41, a high resistance layer 42, and a heavily doped layer 43 along the bottom to the top of the isolation groove, the isolation groove 1 passes through the entire heavily doped layer 43, the high resistance layer 42 and part of the lightly doped layer 41, and the source of the semiconductor device is electrically connected to the heavily doped layer 43 in the substrate.

[0056] The following is a detailed description of the half-bridge circuit structure composed of AlGaO / GaO heterojunction devices based on GaO-on-Si, so as to make the technical solution of this application clearer. It can be understood that the same is applicable to epitaxial wafers composed of other compound semiconductor materials (GaN, GaAs, SiC) with planar structure devices and corresponding epitaxial substrates (Si, GaN, GaO, SiC, Diamond). In addition, the devices in this solution should not be limited to heterojunction devices (or certain electrical connection methods), and the situation where similar effects need to be eliminated is also applicable to this application. For the specific preparation process, see Figure 7 , the detailed steps are as follows:

[0057] (1) Prepare a lightly doped N - Silicon substrate;

[0058] (2)N - Preparation of intrinsic Si layer and N layer from bottom to top on silicon substrate + Silicon layer, which can be grown by secondary epitaxy or ion implantation, wherein the intrinsic Si layer thickness is 10 to 30 μm, N + The silicon layer is 1 to 3 μm;

[0059] (3) Depositing device-related epitaxial structures such as GaO buffer layer, GaO channel layer, AlGaO barrier layer on the surface of the substrate using compound semiconductor deposition equipment such as HPVE or MOCVD. The specific epitaxial structure is determined by the device structure.

[0060] (4) Form an isolation groove by compound etching and Si etching, the depth of which needs to penetrate the substrate compound material and the intrinsic Si layer, N + The function of the isolation trench is to cut off the lateral electrical connection between the device and the circuit parts, and between the compound material and the low-resistance layer in the substrate. The trench width can be designed according to the device's withstand voltage.

[0061] (5) Prepare P by ion implantation in the isolation trench near the device side + Barrier area, and prepare P + barrier region electrode;

[0062] (6) preparing a compound switch tube structure and filling the isolation groove with an isolation medium;

[0063] (7) Counter substrate N -The silicon layer is thinned to a thickness that satisfies P + Blocking area and N - g until a depletion region is formed between the silicon layers sufficient to completely shut off the isolation trench;

[0064] (8) Prepare P on the back of the thinned substrate + Blocking area and N + contact layer and corresponding electrodes.

[0065] An important feature of this solution is that the PN junction that plays an isolating role is not located directly below the compound switch tube, but directly below the isolation trench. In the channel formed below the isolation trench, a P-type barrier region with a certain depth is formed on each side of the compound device by particle implantation. It is connected to the ground potential (Ground) through electrical connection. An N-type contact layer is prepared between the P-type barrier regions and the corresponding ohmic contact is made to make its potential equal to the blocking potential V block Connected, V block The voltage is positive and its magnitude should be such that the depletion region formed by it and the P-type barrier region shuts off the entire bottom of the trench. Another important feature of this solution is that the substrate has heavily doped N-type Si / intrinsic Si / lightly doped Si (N + Silicon layer / intrinsic silicon layer / N - The device source is connected to the heavily doped N-type Si through a through-hole and the metal therein to ensure that the substrate potential is consistent with the device source potential.

[0066] When crosstalk blocking is performed, the PN junction structure in the trench maintains a reverse potential bias, forming a large resistance. When a high potential appears at the source of the high-side switch tube, a depletion region is formed due to the existing isolation structure, and high-frequency signals cannot pass through. A new depletion region is formed from the P-type blocking region to the bottom of the device, further increasing the resistance on the crosstalk path.

[0067] In order to solve the clamping problem caused by the reverse recovery of the PN junction, when a high potential appears at the source of the high-side switch tube, the PN junction between the P-type barrier region and the N-layer begins to reverse recover. Due to the intrinsic Si barrier, the PN junction is clamped at the N-layer, and has little effect on the N+ layer connected to the source. In addition, since the time required for the PN junction to establish a reverse bias is related to the magnitude of its reverse bias voltage, the intrinsic Si layer voltage divider reduces the reverse bias voltage on the PN junction, thereby reducing the clamping time. At the same time, due to the N in the channel - The silicon layer is at V block Under bias, the carriers required to be extracted during the formation of the PN junction depletion region between the device source and the P-type barrier region are quickly extracted by the reverse-biased PN junction in the isolation groove, which improves the reverse bias establishment speed and reduces the clamping time.

[0068] It should be noted that in the description of this application, the drawings and descriptions of the embodiments are illustrative rather than restrictive, and the same drawings throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. In addition, "on..." refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity. The terms "upper", "lower", "top", "bottom", "inside", "outside", "both sides", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting this application.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A compound semiconductor circuit isolation structure, characterized in that: It comprises an isolation groove (1), a barrier region (2) and a contact layer (3) formed below the isolation groove (1); The bottom of the isolation trench (1) is located in the substrate (4); the barrier region (2) has at least two columns and is respectively arranged close to the compound devices on both sides; the barrier region (2) forms a PN junction with the substrate (4); the orthographic projection of the barrier region (2) along the bottom of the isolation trench (1) to the top is located in the bottom area of ​​the isolation trench (1); the orthographic projection of the contact layer (3) along the top of the isolation trench (1) to the bottom is located between the two columns of barrier regions (2) or their orthographic projections, and its doping type is opposite to that of the barrier region (2); the PN junction structure is electrically connected to a separate isolation potential and a ground potential through the barrier region (2) and the contact layer (3); The isolation structure achieves isolation between two adjacent compound devices through the isolation trench (1) and the PN junction; The substrate (4) comprises a lightly doped layer (41), a high-resistance layer (42), and a heavily doped layer (43) in sequence from the bottom of the isolation trench to the top, and the isolation trench (1) passes through all of the heavily doped layer (43), the high-resistance layer (42), and part of the lightly doped layer (41).

2. The compound semiconductor circuit isolation structure according to claim 1, characterized in that: The substrate (4) includes an N-silicon layer, an intrinsic silicon layer and an N+ silicon layer in sequence from bottom to top, and the isolation groove passes through all the N+ silicon layers, all the intrinsic silicon layers and part of the N-silicon layer; or, the substrate (4) includes a P-silicon layer, an intrinsic silicon layer and a P+ silicon layer in sequence from bottom to top, and the isolation groove passes through all the P+ silicon layers, all the intrinsic silicon layers and part of the P-silicon layer.

3. The compound semiconductor circuit isolation structure according to claim 1 or 2, characterized in that: When the substrate is N-type doped, the barrier region (2) is P+-type doped, the contact layer (3) is N+-type doped, the barrier region (2) is electrically connected to the ground potential, and the contact layer (3) is electrically connected to the isolation potential.

4. The compound semiconductor circuit isolation structure according to claim 1 or 2, characterized in that: When the substrate is P-type doped, the barrier region (2) is N+-type doped, the contact layer (3) is P+-type doped, the barrier region (2) is electrically connected to an isolation potential, and the contact layer (3) is electrically connected to a ground potential.

5. The compound semiconductor circuit isolation structure according to claim 1 or 2, characterized in that: The blocking region (2) and / or the contact layer (3) are formed at the bottom of the isolation trench (1) and extend toward the bottom of the substrate (4); or, The blocking region (2) and / or the contact layer (3) are formed at the bottom of the substrate (4) and extend towards the bottom of the isolation trench (1).

6. The compound semiconductor circuit isolation structure according to claim 5, characterized in that: The blocking areas (2) are formed into four columns, and the four columns of blocking areas (2) are symmetrically arranged in pairs, wherein one column of each pair of blocking areas (2) is arranged at the bottom of the isolation groove (1) and extends toward the substrate (4), and the other column is arranged at the edge of the substrate (4) and extends toward the bottom of the isolation groove (1).

7. A compound semiconductor device, characterized in that The compound semiconductor device includes a plurality of semiconductor devices based on the same substrate and the circuit isolation structure according to any one of claims 1 to 6, wherein the circuit isolation structure is used for electrically isolating adjacent semiconductor devices.

8. The compound semiconductor device according to claim 7, wherein It also includes a buffer layer, a channel layer, and a barrier layer sequentially formed on a substrate (4); the isolation trench (1) sequentially penetrates the barrier layer, the channel layer, and the buffer layer and extends to the substrate (4); the surface of the barrier layer and the isolation trench (1) are filled with dielectric material; and the semiconductor devices are respectively formed on both sides of the isolation trench (1).

9. The compound semiconductor device according to claim 8, wherein The substrate (4) comprises a lightly doped layer (41), a high-resistance layer (42), and a heavily doped layer (43) in sequence from the bottom of the isolation trench to the top; the isolation trench (1) passes through the entire heavily doped layer (43), the high-resistance layer (42), and a portion of the lightly doped layer (41); and the source of the semiconductor device is electrically connected to the heavily doped layer (43) in the substrate.

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