Data processing method and system applied to simd computing architecture

Abstract

The application discloses a data processing method and system applied to a SIMD computing architecture, and the method comprises the following steps: carrying out block division on data to be processed; reading the divided data block from the memory corresponding to the processor into a first-level cache, and using a vectorization instruction to pre-process the data in the data block; using repeat and stride parameters in the vector instruction to replace the loop control statement during non-continuous reading, carrying and other processing operations; generating a mask matrix at the beginning of the computing process and saving the mask matrix in the first-level cache for reuse; loading the pre-processed data block into a zero-level cache; the zero-level cache is a storage space directly accessed by a matrix computing unit in the corresponding SIMD architecture processor; loading the computing result into the first-level cache, and using the vectorization instruction to post-process the result; and writing the post-processed result back into the memory corresponding to the processor. The application can provide higher efficiency of data processing capacity under the SIMD computing architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence, and in particular to a data processing method and system applied to SIMD computing architecture, computer equipment and computer readable storage medium. BACKGROUND

[0002] With the rapid development of computer technology, the demand for processing large-scale data sets and high-performance computing in the field of artificial intelligence is also increasing. One of the commonly used execution models for AI accelerators is the SIMT computing architecture represented by GPU. In the field of deep learning, matrix computation accounts for the most time-consuming part. In such computationally intensive applications, SIMD computing architecture has significant power consumption and performance advantages compared to SIMT. Since the processing units of the architecture share the instruction stream, the hardware cost for instruction decoding and scheduling is significantly reduced. In addition, some operations may depend on the results of previous operations, and SIMD computing architecture can avoid the waiting and synchronization overhead caused by data dependency compared to SIMT. SIMD usually provides a rich set of operation instructions, has larger vector registers and caches.

[0003] SIMD computing architecture has become one of the effective ways to process parallel data. By operating multiple data elements simultaneously in a single instruction, highly parallelized data processing can be achieved, improving computing efficiency and throughput. The disadvantage of SIMD architecture compared to SIMT is the loss of flexibility in logical implementation. The existing large-scale parallel SIMD data processing method still needs to improve the utilization rate of hardware resources and parallel performance when facing complex data flow and processing logic. When processing complex matrix, it is difficult to directly rely on vector instructions to efficiently separate the real and imaginary parts. How to utilize the efficient computing performance of SIMD computing architecture and vectorize complex computing logic has become a research focus. SUMMARY

[0004] Therefore, the present application provides a data processing method and system applied to SIMD computing architecture, computer equipment and computer readable storage medium, aiming to overcome the limitations of the prior art and provide more efficient data processing capabilities.

[0005] The first object of the present application is to provide a data processing method applied to SIMD computing architecture.

[0006] The second object of the present application is to provide a data processing system applied to SIMD computing architecture.

[0007] The third object of the present application is to provide a computer equipment.

[0008] The fourth object of the present application is to provide a computer readable storage medium.

[0009] The first object of the present application can be achieved by adopting the following technical solution:

[0010] A data processing method applied to a SIMD computing architecture, the method comprising:

[0011] performing block division on the data to be processed; the data to be processed is a complex matrix;

[0012] reading the divided data block from the memory corresponding to the processor into the level-1 cache, using a vector instruction to pre-process the data in the data block; in non-continuous reading, using the repeat and stride parameters in the vector instruction to replace the loop control statement to reduce the number of instruction transmissions; generating a mask matrix at the beginning of the calculation process, and saving the mask matrix in the level-1 cache to reuse it unlimited times before the task is completed;

[0013] loading the pre-processed data block into the level-0 cache; the level-0 cache is a storage space directly accessed by the matrix calculation unit in the SIMD architecture processor;

[0014] loading the result of the matrix calculation unit into the level-1 cache, and using a vector instruction to post-process the result;

[0015] writing the post-processed result from the level-1 cache back to the memory corresponding to the processor to complete the calculation of the data block.

[0016] Further, the pre-processing includes separating the imaginary part and the real part of the complex number, and at least one operation including but not limited to normalization operation, padding operation, and truncation operation.

[0017] Further, the separation of the imaginary part and the real part of the complex number is completed using a mask vector, or the stride in the instruction is used to obtain the target on a processor with a finer granularity of operation unit, and the interval in the same type of data is eliminated to realize the separation of the imaginary part and the real part, wherein the separated imaginary part and real part are adjacent on the HBM.

[0018] Further, the post-processing includes recombination, format restoration, or accumulation operation.

[0019] Further, the mask matrix is used for element-by-element multiplication to realize triangular zeroing.

[0020] Further, the size and shape of the divided data block are determined according to the cache size on the SIMD computing architecture processor to fully utilize the cache; and using shapes with close dimensions can effectively improve the calculation memory access ratio.

[0021] Further, the calculation flow of different data blocks is overlapped by opening double buffering to solve the problem of low parallelism of the overall architecture caused by the idle matrix units during the time of writing back the calculation result and loading the next data block.

[0022] The second object of the present application can be achieved by adopting the following technical solution:

[0023] A data processing system applied to a SIMD calculation architecture, the system comprises:

[0024] A division module for dividing the data to be processed into blocks; the data to be processed is a complex matrix;

[0025] A preprocessing module for reading the divided data blocks from the memory corresponding to the processor into the level one cache, and pre-processing the data in the data blocks using the vectorization instruction; when reading discontinuously, the repeat and stride parameters in the vector instruction are used to replace the loop control statement to reduce the number of instruction emission; a mask matrix is generated at the beginning of the calculation flow, and the mask matrix is saved in the level one cache to be reused infinitely before the task is completed;

[0026] A calculation module for loading the data blocks after preprocessing into the level zero cache; the level zero cache is a storage space directly accessed by the matrix calculation unit in the SIMD architecture processor;

[0027] A post-processing module for loading the results of the matrix calculation unit into the level one cache, and post-processing the results using the vectorization instruction;

[0028] A write-back module for writing the post-processing results from the level one cache back to the memory corresponding to the processor to complete the calculation of the data blocks.

[0029] The third object of the present application can be achieved by adopting the following technical solution:

[0030] A computer device comprising a processor and a memory for storing programs executable by the processor, when the processor executes the programs stored in the memory, the data processing method described above is realized.

[0031] The fourth object of the present application can be achieved by adopting the following technical solution:

[0032] A computer readable storage medium storing a program, when the program is executed by a processor, the data processing method described above is realized.

[0033] The present application has the following beneficial effects relative to the prior art:

[0034] The application provides a data processing method and system applied to a SIMD computing architecture, a computer device and a computer readable storage medium. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, a brief introduction will be given to the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the drawings shown.

[0036] Figure 1 The schematic diagram of single iteration data flow of the base block of embodiment 1 of the present application;

[0037] Figure 2 The flowchart of the data processing method applied to the SIMD computing architecture of embodiment 1 of the present application;

[0038] Figure 3 The multi-core task schematic diagram of embodiment 1 of the present application;

[0039] Figure 4 The format conversion schematic diagram of embodiment 1 of the present application;

[0040] Figure 5 The multiplication schematic diagram between matrices of embodiment 1 of the present application;

[0041] Figure 6 This is a schematic diagram of the lower triangular matrix processing method according to Embodiment 1 of the present invention;

[0042] Figure 7 Here are the interface names and schematic diagrams for Embodiment 1 of the present invention;

[0043] Figure 8 This is a schematic diagram illustrating the separation of the real and imaginary parts of a complex number in Embodiment 1 of the present invention;

[0044] Figure 9 Here are the interface names and schematic diagrams for Embodiment 1 of the present invention;

[0045] Figure 10 This is a schematic diagram illustrating indexing in a multi-core task according to Embodiment 1 of the present invention;

[0046] Figure 11 This is a schematic diagram illustrating the operation process of an untransposed matrix in Embodiment 1 of the present invention;

[0047] Figure 12 , 13 This is a schematic diagram of the large model test report of Embodiment 1 of the present invention;

[0048] Figure 14 This is a structural block diagram of a data processing system applied to a SIMD computing architecture according to Embodiment 2 of the present invention;

[0049] Figure 15 This is a structural block diagram of the computer device according to Embodiment 3 of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be understood that the specific embodiments described are merely used to explain this application and are not intended to limit this application.

[0051] Example 1:

[0052] This embodiment further details the invention by using an Ascend BLAS library built on HACL to support key BLAS functions for the Pengcheng HPL+AI scenario, thus achieving the readiness of related technologies. The data processing method provided by this invention, applicable to SIMD computing architectures, is fully applicable to NPU processors, calculating complex matrix multiplication based on complex multiplication formulas:

[0053] Result = (a + bi)(c + di) = (ac - bd) + (ad + bc)i

[0054] Implement column priority high-performance general-purpose half-precision complex matrix multiplication on NPU processor, for each base block of single iteration data stream as shown in Figure 1 , at the same time, a series of specific for BLAS API is set to improve the performance of NPU, such as Hgemm, Htrmm, Hsysk, Ctrmv, Sgemv, etc.

[0055] As shown in Figure 2 , the embodiment provides a data processing method applied to a SIMD computing architecture, which specifically comprises the following steps:

[0056] S101, data preprocessing.

[0057] The complex matrix calculation result C is divided into blocks. Based on the idea of divide and conquer, the data to be processed is divided into blocks, each block can be scheduled to a different AI core on the NPU, and each processing core of the SIMD processor polls each data block. The size of each data block depends on the size of the L0 cache on the NPU.

[0058] Specifically, in the process of NPU processing multi-core tasks, the tasks can be divided according to the tasks, as shown in Figure 3 . The matrix C is task divided, assuming that the divided data blocks are matrix A and matrix B, and the load is distributed to each core in a loop. Each AI Core reads the block data from the matrix C, and then reads a row block of A and a column block of B in a loop, and calls cube to complete the matrix operation. The cube performs preprocessing as shown in Figure 4 、 5 , and after the operation, the conversion steps of the matrix A and the matrix B only differ in the transpose of all fractal matrices. At the same time, since the calculation result is a symmetric matrix, the interface specifies the storage of the upper triangular or lower triangular part by passing in the parameter. Taking the lower triangular as an example, refer to Figure 6 , the C matrix is divided into n×n base blocks, and then a limited number of AI cores are mapped to the base blocks in turn to obtain sufficient load balancing. The mmad interface base block is used for calculation inside the AI core. Since the two base blocks for matrix multiplication are derived from the same memory area, the functions in the hgemm operator are used, which are:

[0059] hablas_load_matrix

[0060] hablas_load_matrix_transpose

[0061] Specifically, in the loading of the matrix A and the matrix B, if op = transA, the matrix A is loaded using hablas_load_matrix_transpose, and the matrix B is loaded using hablas_load_matrix, as shown in Figure 7 Through the processing of the data, the chip has a higher degree of fit for the data, and is more conducive to speeding up the processing speed of the data.

[0062] S102, data enters the NPU chip.

[0063] The to-be-processed matrix blocks A and B are carried from the global memory to the unified buffer, and a virtual-real separation preprocessing operation is performed on the matrix A and the matrix B. Specifically, the complex calculation needs to separate the virtual part and the real part for calculation, and the virtual part and the real part are adjacent on the HBM. The efficiency of separating the real part and the virtual part by using the scalar operation will be very low. In this embodiment, the virtual-real separation is completed by using a mask vector, or the stride in the instruction is used to obtain the target on a processor having a more fine-grained operation unit, and the interval in the same type of data is eliminated to realize the virtual-real separation. Figure 8 The virtual-real separation scheme shown avoids a large number of scalar operations, and an additional matrix data reading is performed, which is still better than the scalar method as a whole. Through specific operations, the NPU chip is more efficient and more accurate in the triangular processing mode.

[0064] This embodiment uses a lower triangular coordinate calculation mode for NPU performance improvement. When the input parameter specifies the upper triangular storage, the row number and the column number in the result of the lower triangular base block coordinate calculation formula are exchanged to obtain an equivalent task division result. Since the calculation result is a triangular matrix, when writing, the upper and lower triangular parts of the diagonal base block need to be selectively written. In order to maintain the data of other positions on the GM, the mask matrix of the upper and lower triangles is used to take the upper or lower triangular part of the calculation result, and specific parameters L and T are called as shown in Figure 9

[0065] L = hablas_store_matrix

[0066] T = hablas_store_triangle_transpose

[0067] S103, vec_mul specific internal format conversion.

[0068] ​Specifically, two parameters repeat and stride and their extensions are set, and then the vector scalar multiplication instruction vec_mul is used to perform the format conversion of the four input matrices on the unified buffer to achieve the effect of converting the ND format into the nZ format, and the converted matrix is stored in L1. The real matrix and the imaginary matrix of the matrix B finally need to be in the zZ format, and when the matrix B on the L1 is moved to the L0, the transpose operation is performed on each fractal of the matrix B obtained in S102 using the hardware parameters to obtain the zZ matrix B format.

[0069] S104, if there are still matrix blocks to be processed in the row direction of the matrix A and the column direction of the matrix B, return to S102; otherwise, the real matrix and the imaginary matrix of the calculation result are combined to obtain a complex matrix.

[0070] The number of instruction emission is reduced as much as possible when the instruction is called. The manual pipeline is used to make the matrix A and the matrix B move and calculate at the same time. The base block coordinate operation is also considered. In the traditional matrix, the calculation method of obtaining the row number and the column number from the one-dimensional index is very simple, referring to Figure 10 However, it is difficult to achieve by an independent expression in the triangular matrix. Therefore, the embodiment is calculated by using a step-by-step expression, which is described below by taking the triangular matrix as an example.

[0071] 1. First, given the row number i and the column number j, then

[0072] 2. Given id, calculate the serial number of the first element in the same row as id:

[0073]

[0074] 3. Solve the equation: i 2 +i-2x=0, and the root formula is solved

[0075] 4. Then calculate

[0076] S105, triangular zero optimization scheme.

[0077] The triangular zero optimization scheme is designed in the embodiment, and the mask matrix is used to perform element-by-element multiplication to realize triangular zero. If the original scalar operation is used to set the triangular part to zero, the calculation efficiency will be greatly affected.

[0078] The mask matrix is generated at the cpu end and transmitted to the HBM during calculation. Referring to Figure 11The cyclic block strategy is adopted, and the calculation block is cyclically distributed to each calculation core based on 8 calculation cores. At the same time, the calculation is generated in advance before the calculation starts, although there is a certain overhead and occupies a certain size space, but it is improved for the overall running efficiency. And try to ensure load balancing, the calculation amount of block 0 is the largest, because it determines the overall running time. The calculation result is converted from zN to ND using vec_trans_scatter on the unified buffer, and the C matrix is loaded into the unified buffer from the global memory, and is added to the previous calculation result, and is written back to the global memory. If there are still matrix blocks to be calculated, return to step three. Otherwise, the calculation process is ended.

[0079] Taking the specified NPU optimization as an example, in the case of full use of 32 cores, full play of the computing power m*n>=1024*1024*2, and basic block size of 256x128x256, the NPU is tested by using the method provided in the embodiment, and a satisfactory result is obtained, as follows:

[0080] In the calculation of a series of large models, such as GLM-10B, Llama-13B, Xunfei large model (same as shape-8k) and the like Figure 12 、 13 By using the method provided in the embodiment, the specific performance of TBE can be compared, and it can be seen that the ability of the chip to process data is obviously improved:

[0081] In the proportion of performance≥80%, TBE_GEMN(1980) is as high as 92.33%, Cublas(1980) is as high as 96.53%, TBE_GEMN(1951) is 96.12%, Cublas(1951) is 93.15%, which is much higher than the required target of 90%;

[0082] In the proportion of performance≥100%, TBE_GEMN(1980) is as high as 80.15%, Cublas(1980) is as high as 89.80%, TBE_GEMN(1951) is 87.93%, Cublas(1951) is 53.4%;

[0083] In the proportion of performance≥115%, TBE_GEMN(1980) is as high as 70.6%, Cublas(1980) is as high as 83.61%, TBE_GEMN(1951) is 78.18%, Cublas(1951) is 30.25%. Much higher than the required target of 70%.

[0084] Meanwhile, a series of large models such as GLM-10B, Llama-13B, and Xunfei large model (same as shape-8k) are tested by using the method provided in the embodiment, and the total time of the operators trained by each large model is based on 150100*tbe / hablas and fluctuates up and down, the rate is obviously improved, and the efficiency of the chip in processing data is significantly enhanced.

[0085] Those skilled in the art can understand that all or part of the steps in the method of the above embodiment can be instructed by a program to relevant hardware, and the corresponding program can be stored in a computer readable storage medium.

[0086] It should be noted that although the method operations of the above embodiments are described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in this specific order, or that all of the shown operations must be performed to achieve the desired result. On the contrary, the steps depicted can change the order of execution. Additionally or alternatively, certain steps can be omitted, combined into one step, and / or divided into multiple steps.

[0087] Embodiment 2:

[0088] As shown in Figure 14 The embodiment provides a data processing system applied to a SIMD computing architecture, which comprises a division module 1401, a preprocessing module 1402, a calculation module 1403, a post-processing module 1404 and a write-back module 1405, wherein:

[0089] The division module 1401 is used for block division of the data to be processed; the data to be processed is a complex matrix;

[0090] The preprocessing module 1402 is used for reading the divided data block from the memory corresponding to the processor into the level-1 cache, and pre-processing the data in the data block by using the vectorization instruction; when reading discontinuously, the repeat and stride parameters in the vector instruction are used to replace the loop control statement to reduce the number of instruction emission times; a mask matrix is generated at the beginning of the calculation process, and the mask matrix is saved in the level-1 cache, so as to be reused infinitely before the task is completed;

[0091] The calculation module 1403 is used for loading the data block after preprocessing into the level-0 cache; the level-0 cache is a storage space directly accessed by the matrix calculation unit in the SIMD architecture processor;

[0092] The post-processing module 1404 is used for loading the result of the matrix calculation unit into the level-1 cache, and post-processing the result by using the vectorization instruction;

[0093] The write-back module 1405 is configured to write back the post-processing result from the level-1 cache to the memory corresponding to the processor, so as to complete the calculation of the data block.

[0094] The specific implementation of each module in this embodiment can refer to the above-described embodiment 1, which will not be repeated here; it should be noted that the system provided in this embodiment is only used as an example for the division of the above-mentioned functional modules, and in actual application, the above-mentioned functions can be completed by different functional modules according to needs, that is, the internal structure is divided into different functional modules to complete all or part of the functions described above.

[0095] Embodiment 3

[0096] The embodiment provides a computer device, which can be a computer, such as Figure 15 As shown in the figure, the processor 1502, the memory, the input device 1503, the display 1504 and the network interface 1505 connected through the system bus 1501, the processor is used to provide calculation and control ability, the memory includes a non-volatile storage medium 1506 and an internal memory 1507, the non-volatile storage medium 1506 stores an operating system, a computer program and a database, the internal memory 1507 provides an environment for the running of the operating system and the computer program in the non-volatile storage medium, when the processor 1502 executes the computer program stored in the memory, the data processing method of the above-mentioned embodiment 1 is realized, as follows:

[0097] The data to be processed is divided into blocks; the data to be processed is a complex matrix;

[0098] The divided data block is read into the level-1 cache from the memory corresponding to the processor, and the data in the data block is preprocessed using the vectorization instruction; in the non-continuous reading, the repeat and stride parameters in the vector instruction are used instead of the loop control statement to reduce the number of instruction emission times; in the initial generation of the calculation process, the mask matrix is generated, and the mask matrix is saved in the level-1 cache, so as to be reused infinitely before the task is completed;

[0099] The preprocessed data block is loaded into the zero-level cache; the zero-level cache is a storage space directly accessed by the matrix calculation unit in the SIMD architecture processor;

[0100] The result of the matrix calculation unit is loaded into the level-1 cache, and the result is post-processed using the vectorization instruction;

[0101] The write-back module 1405 is configured to write back the post-processing result from the level-1 cache to the memory corresponding to the processor, so as to complete the calculation of the data block.

[0102] Embodiment 4

[0103] The embodiment provides a computer readable storage medium which stores a computer program, and the computer program is executed by a processor to realize the data processing method in the embodiment 1, as follows:

[0104] The data to be processed is divided into blocks; the data to be processed is a complex matrix;

[0105] The divided data block is read from the memory corresponding to the processor into a level one cache, and the data in the data block is preprocessed by using a vectorization instruction; in non-continuous reading, the repeat and stride parameters in the vector instruction are used to replace the loop control statement to reduce the number of instruction emission times; a mask matrix is generated at the beginning of the calculation process, and the mask matrix is saved in the level one cache, so that the mask matrix is reused unlimited times before the task is completed;

[0106] The preprocessed data block is loaded into a zero-level cache; the zero-level cache is a storage space directly accessed by a matrix calculation unit in the SIMD architecture processor;

[0107] The result of the matrix calculation unit is loaded into the level one cache, and the result is post-processed by using the vectorization instruction;

[0108] The post-processed result is written back from the level one cache to the memory corresponding to the processor, and the calculation of the data block is completed.

[0109] It should be noted that the computer readable storage medium of the embodiment can be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer readable storage media can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0110] The above is only a preferred embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can make equivalent replacements or changes to the technical scheme and the inventive concept of the present application within the scope disclosed by the present application, and all of them belong to the protection scope of the present application.

Claims

1. A data processing method applied to a SIMD computing architecture, characterized in that, The method comprises: block division is performed on the data to be processed; the data to be processed is a complex matrix, and the size and shape of the divided data block are determined according to the cache size on a single instruction multiple data stream (SIMD) calculation architecture processor; the divided data block is read from the memory corresponding to the processor into a level-1 cache, and the data in the data block is preprocessed using a vectorization instruction; in non-continuous reading, the iteration repeat and step length stride parameters in the vector instruction are used to replace the loop control statement to reduce the number of instruction transmissions; a mask matrix is generated at the beginning of the calculation process, and the mask matrix is saved in the level-1 cache to be reused unlimited times before the task is completed; the preprocessed data block is loaded into a level-0 cache; the level-0 cache is a storage space directly accessed by a matrix calculation unit in the SIMD architecture processor; the result of the matrix calculation unit is loaded into the level-1 cache, and the result is post-processed using a vectorization instruction; the post-processed result is written back from the level-1 cache to the memory corresponding to the processor, and the calculation of the data block is completed.

2. The data processing method according to claim 1, characterized in that, The preprocessing includes separation of the imaginary part and the real part of the complex number, and at least one of the normalization operation, the padding operation and the truncation operation.

3. The data processing method according to claim 2, characterized in that, The separation of the imaginary part and the real part of the complex number is completed using a mask vector, or the stride in the instruction is used to obtain a target and eliminate the interval in the same type of data to realize the separation of the imaginary part and the real part, wherein the separated imaginary part and real part are adjacent on the HBM.

4. The data processing method of claim 1, wherein, The post-processing includes recombination, format restoration or accumulation operation.

5. The data processing method of claim 1, wherein, Element-wise multiplication is performed using the mask matrix to realize triangular zeroing.

6. The data processing method according to any one of claims 1 to 5, characterized in that, The calculation processes of different data blocks are overlapped by opening double buffering.

7. A data processing system for application to a SIMD computing architecture, characterized in that, The system comprises: a division module configured to perform block division on the data to be processed; the data to be processed is a complex matrix, and the size and shape of the divided data block are determined according to the cache size on a single instruction multiple data stream (SIMD) calculation architecture processor; a preprocessing module configured to read the divided data block from the memory corresponding to the processor into a level-1 cache, and preprocess the data in the data block using a vectorization instruction; in non-continuous reading, the iteration repeat and step length stride parameters in the vector instruction are used to replace the loop control statement to reduce the number of instruction transmissions; a mask matrix is generated at the beginning of the calculation process, and the mask matrix is saved in the level-1 cache to be reused unlimited times before the task is completed; a calculation module configured to load the preprocessed data block into a level-0 cache; the level-0 cache is a storage space directly accessed by a matrix calculation unit in the SIMD architecture processor; a post-processing module configured to load the result of the matrix calculation unit into the level-1 cache, and post-process the result using a vectorization instruction; a write-back module configured to write the post-processed result from the level-1 cache back to the memory corresponding to the processor, and complete the calculation of the data block.

8. A computer device comprising a processor and a memory for storing a processor executable program, characterized in that, The processor executes a program stored in the memory to implement the data processing method in any one of claims 1-6.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the data processing method of any one of claims 1-6.

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