Ferroelectric nonvolatile memory and preparation method thereof

Abstract

The present invention provides a ferroelectric non-volatile memory and a preparation method thereof, wherein the memory comprises a substrate, a source side control gate, a storage gate and a drain side control gate sequentially arranged above the substrate; wherein a source electrode and a drain electrode are arranged on the substrate, and a substrate region between the source electrode and the drain electrode forms a channel for isolating the source electrode and the drain electrode; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the source side control gate and the drain side control gate are used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source electrode, the source side control gate, the drain side control gate and the drain electrode. The above invention can improve storage density, reduce power consumption and enhance reliability.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and more specifically, to a ferroelectric non-volatile memory and a preparation method thereof. Background Art

[0002] Nonvolatile memory devices have the characteristic of not losing data after power failure and can be found everywhere in the contemporary information society. With the development of the semiconductor industry and the popularization of embedded applications such as specialized hardware and the Internet of Things, the industry has also put forward higher requirements for the performance of nonvolatile memory such as power consumption, speed, storage density, reliability, and endurance.

[0003] At present, ferroelectric field effect transistors (FeFETs) use ferroelectric thin films to replace the gate oxide in the MOSFET structure, so as to use the polarization of the ferroelectric thin film to adjust the on and off states of the channel; by applying voltages of different polarities to the gate, the residual polarization of the ferroelectric layer can be controlled to switch between two directions to achieve the purpose of storing "0" and "1", which has the advantages of fast erase speed, low operating voltage, high storage density, non-destructive readout and strong repeated erase and write capabilities. However, there are still some problems with the traditional structure of FeFET.

[0004] First, the traditional 1T structure FeFET memory has storage density and reliability problems due to the existence of write crosstalk. The traditional memory array programming operation requires the gate (word line) and drain (bit line) to apply voltage at the same time, so the storage cells at the intersection of specific word lines and bit lines can be selected and programmed individually in the cross array structure. In contrast, the 1T structure FeFET cannot achieve cross selection by itself because the programming operation is only controlled by the voltage of the gate relative to the channel. When constructing the cross array structure, additional gating devices are required, resulting in reduced integration density.

[0005] Secondly, potential leakage current reduces the reliability of memory data and increases power consumption. Since the threshold voltage of FeFET fluctuates strongly and the threshold voltage of the device is low when the ferroelectric layer is polarized downward, the threshold voltage offset may cause the threshold voltage of FeFET with polarization downward to be lower than 0V, and remain in the on state when not selected, which significantly increases the leakage current, resulting in poor reliability and increased power consumption. In order to reduce the impact of leakage current, a higher threshold voltage is often used in FeFET memory design. However, a higher threshold voltage makes the gate voltage higher when reading data, which will cause a stronger electric field in the ferroelectric layer and interfere with the polarization state of the ferroelectric layer; that is, the corresponding storage unit will be weakly programmed when reading data. Therefore, the use of a higher threshold voltage cannot effectively improve the reliability of the memory. Summary of the invention

[0006] In view of the above problems, the purpose of the present invention is to provide a ferroelectric non-volatile memory and a preparation method to solve the problems of limited storage density, low reliability and high power consumption existing in existing FeFET memory devices.

[0007] The ferroelectric non-volatile memory provided by the present invention comprises a substrate, a source side control gate, a storage gate and a drain side control gate which are sequentially arranged above the substrate; wherein a source electrode and a drain electrode are arranged on the substrate, and a substrate region located between the source electrode and the drain electrode forms a channel for isolating the source electrode and the drain electrode; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used for applying a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the source side control gate and the drain side control gate are used for controlling the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source electrode, the source side control gate, the drain side control gate and the drain electrode.

[0008] In addition, an optional technical solution is that the substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

[0009] In addition, an optional technical solution is that the channel includes a channel under the source side control gate, a channel under the storage gate and a channel under the drain side control gate; the material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, and indium tin oxide; and the channel is formed on the substrate in a manner including: shallow trench isolation or field oxide isolation.

[0010] In addition, an optional technical solution is that the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, and BLT, and is composed of a single layer of any one of the above materials or a multilayer of a combination of multiple materials, and the formation method of the ferroelectric layer on the substrate includes: atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition, and plasma chemical deposition.

[0011] In addition, an optional technical solution is that a buffer medium is provided on the upper and lower surfaces of the ferroelectric layer respectively; the buffer medium includes at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

[0012] In addition, an optional technical solution is that the material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, metal silicide; and insulating media are provided between the storage gate and the source side control gate and between the storage gate and the drain side control gate.

[0013] In addition, an optional technical solution is that, when implementing data writing, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage cell to be written, and the voltages of the drain side control gate and the source side control gate are both 0V; except for the WL voltage of the selected storage cell being 0V, the remaining WLs are applied with a voltage greater than the drain control gate threshold voltage; the channel of the selected storage cell is turned off, the polarization state of the ferroelectric layer changes, and after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage cell is written with "1".

[0014] In addition, an optional technical solution is that when erasing data, the voltage of the drain side control gate and the source side control gate is set to 0V, and a negative voltage with an amplitude greater than the polarization reversal threshold is applied to the storage gate of the storage cell to be erased; the potential of the upper surface of the ferroelectric layer is a negative voltage, and the lower surface voltage is the substrate voltage of 0V. After the voltage is removed, the ferroelectric layer retains the residual polarization in the upward direction, and the storage cell is erased to "0".

[0015] In addition, an optional technical solution is that when realizing data reading, a voltage greater than the threshold voltage is applied to the drain side control gate and the source side control gate, and a read voltage is applied to the storage gate, and the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off and "0" is read.

[0016] On the other hand, the present invention provides a method for preparing a ferroelectric non-volatile memory, comprising: forming a gate dielectric and a buffer dielectric under a ferroelectric layer on a substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer dielectric, and patterning them by reactive ion etching or wet etching; depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; depositing a control gate material on the insulating layer, and patterning it by dry etching or reactive ion etching until the substrate is exposed to form a source side control gate and a drain side control gate located on both sides of the storage gate; forming source and drain epitaxy on the substrate by light doping injection or oblique injection, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form sidewalls of the source side control gate and the drain side control gate; forming heavily doped source and drain regions on the substrate by ion implantation or diffusion.

[0017] By utilizing the above-mentioned ferroelectric non-volatile memory and preparation method, a source side control gate, a storage gate and a drain side control gate are set, and a ferroelectric layer is set under the storage gate. CG is used to realize cross selection during programming, which can improve storage density and eliminate write crosstalk. In addition, CG is used to cut off leakage current, which can reduce threshold voltage and operating voltage, increase data retention time of the memory, increase storage window and erase speed, reduce leakage current and power consumption, and improve the overall performance and reliability of the memory.

[0018] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0020] Figure 1 A schematic diagram of the structure of a ferroelectric nonvolatile memory according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a writing principle of a ferroelectric nonvolatile memory according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of crosstalk elimination of a ferroelectric nonvolatile memory according to an embodiment of the present invention;

[0023] Figure 4 The figure is a flow chart of a method for preparing a ferroelectric nonvolatile memory according to an embodiment of the present invention.

[0024] The reference numerals include: substrate 1 , drain 2 , source 3 , ferroelectric layer 4 , drain-side control gate 5 , storage gate 6 , source-side control gate 7 .

[0025] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0026] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0027] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0028] In order to solve the problems of limited storage density, low reliability and high power consumption in existing memory solutions, the present invention provides a ferroelectric non-volatile memory and a preparation method thereof, which has three gates: a source side control gate, a storage gate and a drain side control gate, and a ferroelectric layer is arranged under the storage gate. Cross-selection during programming is achieved by using CG, which can improve storage density and eliminate write crosstalk. In addition, leakage current is cut off by using CG, which can reduce threshold voltage and operating voltage, increase data retention time of the memory, increase storage window and erase speed, reduce leakage current and power consumption, and improve overall performance and reliability of the memory.

[0029] To describe the ferroelectric nonvolatile memory and the preparation method of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 1 FIG. 4 shows a schematic structure of a ferroelectric nonvolatile memory according to an embodiment of the present invention.

[0031] like Figure 1 As shown, the ferroelectric non-volatile memory of the embodiment of the present invention comprises a substrate 1, a source side control gate 7, a storage gate 6 and a drain side control gate 5 which are sequentially arranged above the substrate 1; wherein a source electrode 3 and a drain electrode 2 are arranged on the substrate 1, and a region of the substrate 1 between the source electrode 3 and the drain electrode 2 forms a channel for isolating the source electrode 3 and the drain electrode 2; a ferroelectric layer 4 is arranged between the channel and the storage gate 6, and the storage gate 6 is used to apply a voltage to the upper surface of the ferroelectric layer 4 to change the polarization state of the ferroelectric layer 4; the source side control gate 7 and the drain side control gate 5 are used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate 6, the source electrode 3, the source side control gate 7, the drain side control gate 5 and the drain electrode 2.

[0032] Specifically, the memory may include six terminals, namely, a substrate 1, a source side control gate 7 (CGS), a memory gate 6 (MG), a drain side control gate 5 (CGD), a source 3, and a drain 2. A ferroelectric layer 4 composed of materials having ferroelectric properties such as hafnium zirconium oxide and hafnium oxide is arranged under the memory gate 6. A buffer material such as silicon dioxide may be added between the ferroelectric layer 4 and the substrate 1 to form a buffer medium. Insulating media are respectively arranged between the memory gate 6 and the source side control gate 7 and between the memory gate 6 and the drain side control gate 5. The insulating medium may be formed of an insulating layer made of insulating materials such as silicon nitride.

[0033] During the use of the ferroelectric non-volatile memory, the drain side control gate 5 can be connected to the word line (WL), the drain 2 can be connected to the bit line (BL), the storage gate can be connected to the same voltage as the drain 2, the source 3 can be grounded through the common source line (Common SL), and the substrate 1 can be grounded, together forming a NOR type cross array structure, thereby realizing random access, random writing, and block erasing of data.

[0034] In a specific embodiment of the present invention, the substrate 1 is located at the bottom and has a first doping type; its upper part includes source and drain regions, and the source and drain regions are doped with a second doping type opposite to the doping type of the substrate 1; the region between the source 3 and the drain 2 forms a channel, and the channel includes a channel under the source side control gate 7, a channel under the storage gate 6, and a channel under the drain side control gate 5; the material of the substrate 1 includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide).

[0035] The substrate can be a silicon substrate, which is located at the bottom and has P-type doping; its upper part contains source and drain regions, and the source and drain regions have N+ doping; the region between the source and drain is a channel. The gate dielectric, control gate (including source side control gate 7 and drain side control gate 5, the same below), storage gate, ferroelectric layer, and various insulating layers are stacked on the substrate. Ion implantation is used to form a p-well with a high doping concentration in the substrate, and then shallow trench isolation (STI) and field oxide (field oxide) processes are used to isolate each storage unit.

[0036] Among them, the gate dielectric located between the lower surface of the control gate and the upper surface of the substrate 1, the two control gates (including the source side control gate 7 and the drain side control gate 5, the storage gate 6, the ferroelectric layer 4, and the insulating dielectrics are all stacked on the substrate 1. According to the corresponding relationship in the vertical direction, the channel can be divided into the lower channel of the source side control gate 7, the lower channel of the storage gate 6, and the lower channel of the drain side control gate 5. The available substrate 1 materials include elemental semiconductors, such as silicon and germanium; compound semiconductors, such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, and indium antimonide; oxide semiconductors, such as IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); alloy compound semiconductors; organic materials; flexible materials and combinations of the above materials. The material is doped with the substrate 1 by diffusion, ion implantation, etc., and is connected to the substrate 1 through shallow trench isolation (STI), field oxide (field The material is divided into various substrate 1 regions by isolation technologies such as oxide. In addition, high doping concentration regions can be further formed in the substrate 1 by diffusion or ion implantation to improve the performance of the memory, such as p-well (n-well) and EPM implantation.

[0037] In a specific embodiment of the present invention, the ferroelectric layer 4 is a thin layer made of a material having ferroelectric properties, which is located above the substrate 1 and covers the middle part of the channel. The lower surface of the ferroelectric layer 4 is connected to the substrate 1, and the upper surface is connected to the storage gate 6. A buffer medium or an insulating layer can be added between the lower surface of the ferroelectric layer 4 and the substrate 1, and between the upper surface and the storage gate 6 to improve the properties of the interface.

[0038] In addition, the material of the ferroelectric layer 4 has a residual polarization when there is no electric field, and its polarization state can be reversed. The material of the ferroelectric layer 4 can include metal oxides, such as hafnium oxide, doped hafnium oxide, zirconium oxide, hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAlO), hafnium lanthanum oxide; salts, such as lead titanate, PZT, SBT, BLT, etc. The method for forming the ferroelectric layer 4 on the substrate 1 includes one or more of atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD) and the like.

[0039] In addition, buffer media are provided on the upper and lower surfaces of the ferroelectric layer 4, respectively. The buffer media includes at least one layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO, and the buffer media forms a dielectric layer.

[0040] As an example, the ferroelectric layer is a thin layer made of hafnium zirconium oxide (HZO), which is located above the substrate and covers part of the middle area of ​​the channel. The lower surface of the ferroelectric layer is connected to the substrate, and the upper surface is connected to the storage gate; there is a thin layer of silicon dioxide between the lower surface of the ferroelectric layer and the substrate to improve the interface properties. In addition, the ferroelectric layer can be formed by atomic layer deposition (ALD).

[0041] In a specific embodiment of the present invention, the storage gate 6 is located directly above the ferroelectric layer 4, and its cross section is aligned with the ferroelectric layer 4. The left and right sides of the storage gate 6 and the ferroelectric layer 4 are respectively the source side control gate 7 and the drain side control gate 5, and the control gate and the storage gate 6 are isolated by insulating layers. The storage gate 6 is used as a gate electrode to apply a large voltage to the upper surface of the ferroelectric layer 4. Available materials for the storage gate 6 include semiconductors, such as doped polysilicon; metals, such as tantalum and neodymium; metal nitrides and oxides, such as titanium nitride, tungsten nitride, and tantalum nitride; metal silicides, etc.

[0042] In addition, the method for forming the storage gate 6 on the ferroelectric layer 4 includes low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD), etc. If a polysilicon gate is used, in-situ doping can be performed during deposition. After the ferroelectric layer 4 and the storage gate 6 are formed successively, the two can be patterned, and the patterning process includes wet etching (WE) after photolithography, reactive ion etching (RIE) after photolithography, etc. Further, the materials for the insulating layer that can be selected include one or more layers of insulating media such as silicon dioxide, silicon nitride, and common compounds and organic composite isolation materials. After the ferroelectric layer 4 and the storage gate 6 are formed, the insulating layer can be formed by etching for a short time after forming a thin layer of insulating medium by chemical deposition methods such as LPCVD and PECVD. The etching method can be dry etching, reactive ion etching (RIE), etc.

[0043] As a specific example, the storage gate uses an N+ polysilicon gate, which is located directly above the ferroelectric layer, and the cross section overlaps with the ferroelectric layer. The storage gate and the ferroelectric layer are on both sides of the control gate, and the two control gates are isolated by a silicon nitride insulating layer. In the preparation process, the polysilicon film is first deposited using low-pressure chemical vapor deposition (LPCVD) technology, and N+ in-situ doping (In-situ Doping) is performed during deposition. Subsequently, the storage gate pattern is defined on the photoresist by photolithography, and then reactive ion etching (RIE) is performed, and the photoresist is stopped and removed when the silicon dioxide is exposed. Thereafter, a thin layer of silicon nitride is deposited by LPCVD, and RIE is used to etch for a short time until the silicon dioxide is exposed to form an insulating layer. Sidewall isolation can be formed by the same method after the ferroelectric layer, storage gate, control gate, and insulating layer are all formed.

[0044] In a specific embodiment of the present invention, the source side control gate 7 and the drain side control gate 5 are located above the substrate 1 and the gate dielectric, covering the remaining area of ​​the channel edge, and controlling the opening and closing of the channel thereunder. In the embodiment shown in the accompanying drawings, the control gate covers the left and right sides of the channel, and is located on both sides of the storage gate 6 and the ferroelectric layer 4. The lower surface of the control gate and the upper surface of the substrate 1 are separated by a gate dielectric, and one side of the control gate is a sidewall spacer, and the other side is isolated from the storage gate 6 by an insulating layer. Among them, the gate dielectric materials that can be used include one or more layers of silicon dioxide; silicon nitride; high dielectric constant metal oxide materials, such as titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, etc.

[0045] In addition, the gate dielectric is formed before forming each gate, and the method includes deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD; if silicon dioxide is used as the gate dielectric, thermal oxidation can be used to form a gate dielectric with better quality. The available materials for the control gate are similar to those for the storage gate 6, including polysilicon, metal, metal oxide or nitride, etc. The process flow for forming the control gate includes deposition, planarization, and patterning. Deposition can use chemical vapor deposition such as LPCVD, PECVD, HDP-CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc., planarization can use techniques such as chemical mechanical polishing (CMP), and patterning can be completed by etching techniques such as reactive ion etching (RIE) after photolithography masking.

[0046] Furthermore, the control gate can be formed after the storage gate 6 is formed and before the sidewall isolation is formed. The sidewall isolation can be formed by the same method after the ferroelectric layer 4, the storage gate 6, the control gate and the insulating layer are all formed; the available materials include one or more layers of insulating media such as silicon dioxide, silicon nitride, and common compounds and organic composite isolation materials, and the specific reference can be made to the insulating materials in the above content.

[0047] As a specific example, the source side control gate and the drain side control gate are also N+ polysilicon gates, located above the substrate and the gate dielectric, and cover the remaining areas on both sides of the channel respectively. There is a thin layer of silicon dioxide between the lower surface of the two control gates and the upper surface of the substrate. The source side control gate is close to the source side and the drain side control gate is close to the drain side for sidewall isolation, and the other side has a silicon nitride insulating layer to isolate it from the storage gate. In the preparation process, a thin layer of silicon dioxide is first formed by thermal oxidation, and then a polysilicon film is deposited by LPCVD, and in-situ doping is performed during the process. Thereafter, the chemical mechanical polishing (CMP) technology is used for flattening, and the control gate pattern is defined by photolithography. After photolithography, RIE is used for etching until the silicon substrate is exposed, and the photoresist is removed to form two control gates. The two control gates can be formed after the storage gate is formed and before the sidewall isolation is formed. The materials and formation methods of the sidewall isolation and the inter-gate insulating layer have been described.

[0048] In a specific embodiment of the present invention, the source region and the drain region are located on both sides of the channel of the substrate 1, with a high doping concentration and a doping type opposite to that of the channel. Doping processes such as diffusion and ion implantation can be used to form them. The source and drain regions can be doped before or after the gate stack and the sidewall are formed. If doped after formation, self-aligned ion implantation can be used. Furthermore, short-time diffusion, low-concentration ion implantation or oblique ion implantation can be performed after the gate stack is formed and before the sidewall is formed to form source and drain epitaxy to reduce the short channel effect.

[0049] Specifically, the source and drain regions are located in the substrate, on both sides of the channel, with N+ doping. After the gate stack is formed, low-concentration ion implantation and oblique ion implantation (Halo Implant) are first performed to form source and drain epitaxy. After the sidewall isolation is formed, self-aligned ion implantation is used to form source and drain doping.

[0050] When using the ferroelectric non-volatile memory of the embodiment of the present invention to write data, a positive voltage greater than the polarization reversal threshold can be applied to the storage gate and drain of the storage cell to be written, and the voltages of the drain side control gate and the source side control gate are both 0V; except for the WL voltage of the selected storage cell being 0V, the remaining WLs are applied with a voltage greater than the drain control gate threshold voltage; the channel of the selected storage cell is turned off, the polarization state of the ferroelectric layer changes, and after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage cell is written with "1".

[0051] Specifically, Figure 2 As shown, the writing principle of the ferroelectric non-volatile memory according to the embodiment of the present invention is that at this time, a positive voltage greater than the polarization reversal threshold is applied to the MG and the drain (BL) of the storage cell to be written, and the CGD (WL) voltage and the CGS voltage are both 0V. Except for the WL voltage of the selected storage cell being 0V, the other WLs need to be applied with a voltage greater than the CGD threshold voltage, such as a logic high level. At this time, the channel of the selected storage cell is turned off, the voltage on the lower surface of the ferroelectric layer is close to the substrate voltage of 0V, and the voltage on the upper surface is the larger positive voltage applied by MG, so that there is an electric field with a downward direction and a large intensity in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the cell is written with "1".

[0052] also, Figure 3 The crosstalk elimination principle of the ferroelectric nonvolatile memory according to the embodiment of the present invention is shown.

[0053] like Figure 3As shown, when the remaining memory cells that share BL with the programmed memory cell are half-selected, a positive voltage greater than the polarization reversal threshold is applied to the MG and the drain, the CGS voltage is 0, and the CGD voltage is greater than its threshold voltage. At this time, the inversion layer under MG is connected to the drain through the inversion layer under CGD, but the turned-off CGS channel isolates it from the source, and the channel surface potential under MG is close to the drain voltage. The voltage on the upper surface of the ferroelectric layer is the MG positive voltage, and the voltage on the lower surface is the drain positive voltage; since the voltage applied to MG and the drain is the same during use, the electric field inside the ferroelectric layer is very weak. The large positive voltage applied by MG and the drain falls on the reverse biased PN junction between the drain, the inversion layer and the substrate, and the ferroelectric layer is shielded by the inversion layer below it, and the polarization state does not change. Therefore, the memory cell half-selected by BL is not affected. For the remaining memory cells, the CGS, MG, drain, and source voltages are all 0V. Therefore, regardless of whether a positive voltage is applied to CGD, the upper and lower surface voltages of the ferroelectric layer are both 0V, the polarization state does not change, and the memory cell is not affected, thereby eliminating the crosstalk of the memory.

[0054] When erasing data using the ferroelectric nonvolatile memory of the embodiment of the present invention, the voltage of the drain side control gate and the source side control gate is set to 0V, and a negative voltage with an amplitude greater than the polarization reversal threshold is applied to the storage gate of the storage unit to be erased; at this time, the potential of the upper surface of the ferroelectric layer is a negative voltage, and the voltage of the lower surface is the substrate voltage 0V, which is subjected to a strong electric field in the upward direction; after the voltage is removed, the ferroelectric layer will retain the residual polarization in the upward direction, and the storage unit is erased to "0". Since erasure is only controlled by the MG voltage, the voltage on the entire BL is erased, thereby achieving a block-by-block erasure effect.

[0055] When using the ferroelectric non-volatile memory of the embodiment of the present invention to read data, a voltage greater than the threshold voltage is applied to the drain side control gate and the source side control gate, and a read voltage is applied to the storage gate, and the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; since the channel under CGS and CGD is turned on, whether the source to drain is turned on is determined by the channel under the ferroelectric layer, if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off and "0" is read.

[0056] Corresponding to the above ferroelectric non-volatile memory, the present invention also provides a method for preparing a ferroelectric non-volatile memory, specifically Figure 4 The flowchart of the method for preparing a ferroelectric nonvolatile memory according to an embodiment of the present invention is shown.

[0057] like Figure 4 As shown, the method for preparing the ferroelectric non-volatile memory of the embodiment of the present invention comprises:

[0058] S100: forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition;

[0059] Before step A100, a doped substrate may be first formed, and each memory cell may be formed by shallow trench isolation or field oxidation segmentation to form a memory array; then, a gate dielectric of two control gates and a buffer layer under the ferroelectric layer may be formed by thermal oxidation or chemical vapor deposition.

[0060] S200: forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer medium, and patterning them by reactive ion etching or wet etching;

[0061] S300: depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer;

[0062] S400: depositing a control gate material on the insulating layer, and patterning the material until the substrate is exposed by dry etching or reactive ion etching to form a source side control gate and a drain side control gate located on both sides of the storage gate;

[0063] S500: forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing a sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form sidewalls of a source side control gate and a drain side control gate;

[0064] S600: forming heavily doped source and drain regions on the substrate by ion implantation or diffusion.

[0065] As a specific example, the method for preparing the ferroelectric non-volatile memory according to the embodiment of the present invention may include:

[0066] 1) Forming substrate doping by diffusion, ion implantation, etc., and dividing the material into storage unit substrates by isolation technologies such as shallow trench isolation (STI) and field oxide;

[0067] 2) Forming a control gate dielectric and a buffer layer under the ferroelectric layer by using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD;

[0068] 3) Depositing ferroelectric layer materials using techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), and plasma induced chemical deposition (PECVD);

[0069] 4) Depositing storage gate materials using low pressure chemical vapor deposition (LPCVD), plasma assisted chemical deposition (PECVD) and other technologies;

[0070] 5) Using photolithography to define the memory gate and ferroelectric layer patterns on the photoresist, using wet etching (WE), reactive ion etching (RIE) and other etching techniques for patterning, and then removing the photoresist;

[0071] 6) Depositing insulating layer materials by chemical deposition methods such as LPCVD and PECVD, followed by short-term etching using dry etching, reactive ion etching (RIE) and other techniques until the gate dielectric deposited in step 2 is exposed, forming an insulating layer between the two control gates and the storage gate;

[0072] 7) Depositing control gate materials using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and other technologies such as LPCVD, PECVD, HDP-CVD, etc.;

[0073] 8) Planarization using techniques such as chemical mechanical polishing (CMP);

[0074] 9) Using photolithography to define a control gate pattern on the photoresist, using etching techniques such as reactive ion etching (RIE) to pattern, and then removing the photoresist to form a source side control gate and a drain side control gate;

[0075] 10) Depositing sidewall isolation materials using CVD, ALD or other techniques, and then etching using dry etching, RIE or other techniques until the substrate described in step 1 is exposed to form sidewall isolation;

[0076] 11) Heavy doping is performed using diffusion, ion implantation or other doping processes, with the doping type being opposite to the substrate doping type described in step 1, to form source and drain regions.

[0077] Furthermore, a high doping concentration region may be formed in the substrate by diffusion or ion implantation to improve device performance, such as p-well (n-well) and EPM implantation.

[0078] It should be noted that the embodiment of the method for preparing the ferroelectric non-volatile memory may refer to the description in the embodiment of the ferroelectric non-volatile memory, and will not be described in detail here.

[0079] According to the scheme of the ferroelectric non-volatile memory and the preparation method of the present invention described above, CG can be used to implement cross-selection during programming, the storage density is improved compared with FeFETs with additional transistors or transmission gates, the write crosstalk is eliminated compared with FeFETs without additional transistors, the reliability is enhanced, and the leakage current is cut off by CG, so that a lower threshold voltage and read voltage can be used, and the impact of the read operation on the data is reduced, so that the reliability is enhanced and the power consumption is reduced.

[0080] As described above, the ferroelectric non-volatile memory and the preparation method according to the present invention are described by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various improvements can be made to the ferroelectric non-volatile memory and the preparation method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A non-volatile memory, characterized in that: It includes a substrate, a source side control gate, a storage gate and a drain side control gate which are sequentially arranged above the substrate; wherein, A source electrode and a drain electrode are arranged on the substrate, and a substrate region between the source electrode and the drain electrode forms a channel for isolating the source electrode and the drain electrode; A ferroelectric layer is provided between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; The source side control gate and the drain side control gate are used to control the channel to be turned on or off; Data writing, reading and erasing are achieved by controlling the voltages of the storage gate, the source, the source-side control gate, the drain-side control gate and the drain; During the data writing process, the voltage applied to the leakage control gate is used to control the channel surface potential under the storage gate.

2. The nonvolatile memory according to claim 1, wherein: The substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

3. The nonvolatile memory according to claim 1, wherein: The channel includes a channel under the source side control gate, a channel under the storage gate, and a channel under the drain side control gate; The material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); The channel is formed on the substrate in a manner including shallow trench isolation or field oxide isolation.

4. The nonvolatile memory according to claim 1, wherein: The materials of the ferroelectric layer include hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, and BLT, and are composed of a single layer of any one of the above materials or a multilayer combination of multiple materials. The ferroelectric layer is formed on the substrate by atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition, and plasma chemical deposition.

5. The nonvolatile memory according to claim 1 or 4, characterized in that: Buffer media are respectively arranged on the upper and lower surfaces of the ferroelectric layer; The buffer medium includes at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

6. The nonvolatile memory according to claim 1, wherein: The material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, and metal silicide; An insulating medium is provided between the storage gate and the source-side control gate, and between the storage gate and the drain-side control gate.

7. The nonvolatile memory according to claim 1, wherein: When writing data, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage unit to be written, and the voltages of the drain side control gate and the source side control gate are both 0V; Except for the word line voltage of the selected memory cell being 0V, the remaining word lines are applied with a voltage greater than the threshold voltage of the leakage control gate; The channel of the selected memory cell is turned off, the polarization state of the ferroelectric layer changes, and after the voltage is removed, the ferroelectric layer has a residual polarization in a downward direction, and "1" is written into the memory cell.

8. The nonvolatile memory according to claim 1, wherein: When erasing data, the voltages of the drain-side control gate and the source-side control gate are set to 0V, and a negative voltage having an amplitude greater than a polarization reversal threshold is applied to the storage gate of the storage cell to be erased; The potential of the upper surface of the ferroelectric layer is the negative voltage, and the voltage of the lower surface is the substrate voltage 0V. After the voltage is removed, the ferroelectric layer retains the residual polarization in the upward direction, and the storage unit is erased to "0".

9. The nonvolatile memory according to claim 1, wherein: When data is read, a voltage greater than a threshold voltage is applied to the drain side control gate and the source side control gate, and a read voltage is applied to the storage gate, wherein the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; If the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read out; otherwise, the channel is turned off, and "0" is read out.

10. A method for preparing a non-volatile memory, characterized in that: For forming the non-volatile memory according to any one of claims 1 to 9, the method comprising: Forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer medium, and patterning them by reactive ion etching or wet etching; Depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; Depositing a control gate material on the insulating layer, and patterning the material until the substrate is exposed by dry etching or reactive ion etching to form a source-side control gate and a drain-side control gate located on both sides of the storage gate; Forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form sidewalls of the source side control gate and the drain side control gate; Heavily doped source and drain regions are formed on the substrate by ion implantation or diffusion.

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