Quantum circuit processing method, device and electronic equipment

Abstract

The present disclosure provides a quantum circuit processing method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: obtain a first directed acyclic graph of a first quantum circuit, and obtain a search level of the first directed acyclic graph; select a target output node from the output node list of the first directed acyclic graph to obtain a first list, and the number of target output nodes in the first list matches the search level; based on the first directed acyclic graph, the first list and the input node list of the first directed acyclic graph, determine a first set including target feasible solutions; determine the target directed edges that can be added in the second directed acyclic graph in turn, and obtain a fourth list; based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit, perform equivalent compilation on the first quantum circuit to obtain a second instruction list for the second quantum circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit processing method, device and electronic device. Background Art

[0002] Quantum computing uses the unique operating rules of the quantum world to provide a new and very promising way of information processing. In many specific problems, quantum algorithms can bring advantages over classical algorithms. For example, using Shor's algorithm, large integers can be efficiently decomposed, and using Grover's algorithm, data searches can be performed faster. With the development of quantum theory, new quantum algorithms are constantly being proposed. How to efficiently simulate these algorithms or run them on real quantum hardware has always been an important issue.

[0003] At present, the classical simulation or real machine operation of quantum algorithms is mainly limited by the number of quantum bits. In classical simulation, the length of the column vector describing the quantum state grows exponentially with the number of corresponding bits (for example, the length of the column vector of an n-bit quantum state is 2 n ), it is difficult for classical computers to simulate large-scale quantum algorithms. Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support the simulation of algorithms with dozens of quantum bits at most. Summary of the invention

[0004] The present disclosure provides a quantum circuit processing method, device and electronic device.

[0005] According to a first aspect of the present disclosure, a quantum circuit processing method is provided, comprising:

[0006] Obtaining a first directed acyclic graph of a first quantum circuit, and obtaining a search level of the first directed acyclic graph;

[0007] Selecting a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level;

[0008] Determining, based on the first directed acyclic graph, the first list, and the input node list of the first directed acyclic graph, a first set including target feasible solutions, the target feasible solutions indicating input nodes to which each target output node can be connected;

[0009] For each target feasible solution, determine in turn the target directed edges that can be added to the second directed acyclic graph to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes the output nodes in the output node list other than the first list, and the third list includes the input nodes in the input node list other than the input nodes indicated by the target feasible solution;

[0010] Based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and directed edges indicating target feasible solutions corresponding to the fourth list, and the third directed acyclic graph is obtained by adding directed edges in the target list to the first directed acyclic graph.

[0011] According to a second aspect of the present disclosure, there is provided a quantum circuit processing device, comprising:

[0012] An acquisition module, used to acquire a first directed acyclic graph of a first quantum circuit, and acquire a search level of the first directed acyclic graph;

[0013] A selection module, configured to select a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level;

[0014] A first determining module, configured to determine a first set including target feasible solutions based on the first directed acyclic graph, the first list, and the input node list of the first directed acyclic graph, wherein the target feasible solution indicates input nodes to which each target output node can be connected;

[0015] A second determination module is used to determine, for each target feasible solution, target directed edges that can be added to the second directed acyclic graph in turn to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes other output nodes in the output node list except the first list, and the third list includes other input nodes in the input node list except the input nodes indicated by the target feasible solution;

[0016] an equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on a third directed acyclic graph, a target list and a first instruction list of the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and directed edges indicating target feasible solutions corresponding to the fourth list, and the third directed acyclic graph is obtained by adding directed edges in the target list to the first directed acyclic graph.

[0017] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0018] at least one processor; and

[0019] a memory communicatively connected to at least one processor; wherein,

[0020] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0021] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0022] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0023] The technology disclosed in the present invention solves the problem that classical simulation and real machine operation of quantum circuits in related technologies are relatively difficult, making it possible to perform classical simulation and real machine operation on quantum circuits with large-scale quantum bits, and to balance the compilation effect and operation complexity of quantum circuit processing, thereby reducing the number of quantum bits required for the compiled dynamic quantum circuit and improving flexibility.

[0024] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0026] Figure 1 is a flowchart of a quantum circuit processing method according to the first embodiment of the present disclosure;

[0027] Figure 2This is a schematic diagram of the structure of an example static quantum circuit;

[0028] Figure 3 is a schematic diagram of the structure of a static quantum circuit of another example;

[0029] Figure 4 yes Figure 3 The schematic diagram of the structure of converting the static quantum circuit shown into a dynamic quantum circuit;

[0030] Figure 5(a) is Figure 3 A schematic diagram of the structure of the directed acyclic graph corresponding to the static quantum circuit shown;

[0031] FIG5( b ) is a schematic diagram of the structure of the directed acyclic graph after adding directed edges;

[0032] Figure 6 is a schematic diagram of the structure of a static quantum circuit of another example;

[0033] Figure 7 yes Figure 6 A schematic diagram of the structure of a directed acyclic graph of the circuit shown;

[0034] Figure 8(a) is Figure 6 Schematic diagram of the candidate edge matrix of the static quantum circuit shown;

[0035] FIG8( b ) is one of the updating process diagrams of the candidate edge matrix;

[0036] FIG8( c ) is the second diagram of the updating process of the candidate edge matrix;

[0037] Fig. 9 is an updated schematic diagram of the directed acyclic graph after adding candidate directed edges;

[0038] Fig.10 It is a schematic diagram comparing the compilation effects of different schemes on the maximum cut QAOA circuit;

[0039] Fig.11 This is one of the schematic diagrams comparing the compilability factors of random quantum circuits using different schemes;

[0040] Fig.12 This is the second diagram comparing the compilability factors of random quantum circuits using different schemes;

[0041] Fig.13 is a schematic structural diagram of a quantum circuit processing device according to a second embodiment of the present disclosure;

[0042] Fig.14 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0044] First embodiment

[0045] like Figure 1 As shown, the present disclosure provides a quantum circuit processing method, comprising the following steps:

[0046] Step S101: obtaining a first directed acyclic graph of a first quantum circuit, and obtaining a search level of the first directed acyclic graph.

[0047] In this embodiment, the quantum circuit processing method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology, which can be widely used in classical simulation and real machine operation scenarios of quantum circuits. The quantum circuit processing method of the disclosed embodiment can be executed by the quantum circuit processing device of the disclosed embodiment. The quantum circuit processing device of the disclosed embodiment can be configured in any electronic device to execute the quantum circuit processing method of the disclosed embodiment.

[0048] Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support algorithms that simulate dozens of qubits at most. For example, a laptop can simulate about 20-30 qubits, and a large supercomputer and cluster can simulate up to 30-40 qubits. In real machine operation, the scalability problem of current quantum chips has not yet been solved, resulting in a very limited number of qubits that a quantum computer can provide. Therefore, quantum circuit optimization is a fundamental issue in the field of quantum computing.

[0049] Quantum circuit optimization is a process that uses certain technical means to simplify a given quantum circuit to reduce the requirements for classical simulation and real-machine operation, thereby accelerating the research of quantum algorithms and the implementation of quantum computing in practical scenarios.

[0050] The quantum circuit processing of this embodiment can be a quantum circuit optimization process, and its purpose is to optimize and compile the quantum circuit so that the compiled quantum circuit can greatly simplify the original quantum circuit in terms of the number of quantum bits. On the one hand, it can further improve the scale of classical simulation of quantum algorithms and enhance the verification ability of classical computers on quantum algorithms. On the other hand, it can also reduce the bit number requirements of quantum algorithms on real machines, making up for the shortcomings of the current quantum chip scalability problem.

[0051] More specifically, the purpose of this embodiment is to compile a given quantum circuit into a dynamic quantum circuit to reduce the number of quantum bits in the quantum circuit and lower the requirements for its classical simulation and real machine operation.

[0052] Among them, dynamic quantum circuits are able to integrate classical communication and computing into quantum circuits by introducing intermediate circuit measurements of quantum bits and the ability to reset quantum bits to their ground state during calculations. This feature will greatly increase the diversity of circuits running on quantum hardware and is also crucial for the development of error-corrected and fault-tolerant quantum computing. Therefore, dynamic quantum circuits are expected to become an important part of many quantum applications in the future. In a mathematical sense and without experimental constraints, static and dynamic quantum circuits have the same computing power, that is, any problem that can be expressed by a dynamic quantum circuit can also be expressed as a static problem, so dynamic quantum circuits provide the possibility of a trade-off between circuit depth and width.

[0053] The quantum circuit model is introduced in detail below.

[0054] The quantum circuit model is a commonly used quantum computing model. The evolution of the quantum state is completed by performing quantum gate operations on the initial quantum state, and the calculation results are extracted through quantum measurements. The quantum circuit diagram represents the entire process of quantum circuit model calculation.

[0055] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit. Figure 2 As shown, a quantum bit system can be represented by a horizontal line, and the quantum bits are numbered from top to bottom, where the quantum bit numbers often start from zero.

[0056] The direction of time evolution in the quantum circuit diagram is from left to right. The leftmost end is the initial quantum state, where each quantum bit is usually initialized to the zero state, and then different quantum gate operations are applied to the initial state in sequence to complete the evolution of the quantum state. At the same time, quantum measurements can be performed on certain quantum bits to obtain measurement results.

[0057] If a quantum circuit does not have any quantum measurement or quantum state preparation operations in the middle of the circuit, then such a circuit is called a static quantum circuit. An example of a static quantum circuit diagram is as follows: Figure 2 shown.

[0058] The operations in a quantum circuit diagram are usually represented by an ordered list of instructions in the order in which they are used. Each element in the list represents an instruction operation. Specifically,

[0059] Each quantum state preparation (or initialization) operation is represented by a four-element instruction [Reset, qubit, None, None]. For example, [Reset, 2, None, None] means initializing qubit 2 to the zero state.

[0060] Each single-qubit gate (such as H, X, Y, Z, S, T, Rx, Ry, Rz, etc.) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is the quantum bit acted on by the quantum gate, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [Rx, 2, π, None] means to apply an Rx rotation gate to the quantum bit on qubit 2, with a rotation angle of π.

[0061] Each two-qubit gate (such as a controlled NOT gate, CNOT gate, SWAP gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the two-qubit gate acts on. For a controlled quantum gate, qubit is a list of control bits and controlled bits, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [SWAP, [1, 2], None, None] means to act on SWAP gates between qubits 1 and 2; and [CNOT, [1, 3], None, None] means to act on qubits 1 and 3, where 1 is the control bit and 3 is the controlled bit.

[0062] Each multi-qubit gate (such as CCX gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the multi-qubit gate acts on, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [CCX, [0, 1, 2], None, None] means to act on the CCX gate between qubits 1, 2, and 3, where 1 and 2 are control bits and 3 is a controlled bit.

[0063] A measurement in a computational basis is represented by a four-element instruction [Measure, qubit, None, None]. For example, [Measure, 2, None, None] represents a computational basis measurement on qubit 2.

[0064] In some application scenarios, it is allowed to measure some quantum bits in the middle of a quantum circuit, and reset these quantum bits to zero state after the measurement results are obtained, so that they can be used for subsequent calculations. A quantum circuit that includes intermediate measurements and reset operations is called a dynamic quantum circuit. Figure 3 The static quantum circuit shown is transformed into a dynamic quantum circuit. Figure 4 As shown, it can be seen that the dynamic circuit reduces the number of quantum bits by one, but the operating effects of the two quantum circuits are equivalent.

[0065] Figure 3 The instruction list of the static quantum circuit shown is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0066] Figure 4 The circuit instruction list of the dynamic quantum circuit obtained after the equivalent compilation shown is: dynamic_circuit = [[Reset,0,None,None],[Reset,1,None,None],[H,0,None,None],[H,1,None,None],[CNOT,[0,1],None,None],[Measure,0,None,None],[Reset,0,None,None],[H,0,None,None],[CNOT,[1,0],None,None],[Measure,0,None,None],[Measure,1,None,None]].

[0067] In this embodiment, a given static quantum circuit is compiled into an equivalent dynamic quantum circuit, so that the number of quantum bits required for the compiled quantum circuit is less than the number of quantum bits of the original quantum circuit. The compilation problem of the static quantum circuit can be transformed into an equivalent graph optimization problem. To ensure the equivalence of the quantum circuits before and after compilation, it is necessary to ensure that the order of the operation instructions with execution restrictions in the original static quantum circuit is not changed during compilation.

[0068] In the implementation process, the execution order of quantum circuit operation instructions can be represented by a directed acyclic graph. Each operation instruction in the quantum circuit corresponds to a node in the graph, and the execution order of the quantum circuit operation instructions can be represented by a directed acyclic graph. i Point to v j The directed edge of v i The corresponding operation instruction must be in v j The corresponding operation instruction is executed before execution.

[0069] For example, Figure 3 The directed acyclic graph corresponding to the static quantum circuit in is shown in Figure 5(a). Figure 3 The same as the operation instruction number in Figure 5(a). Figure 4 The dynamic quantum circuit is to Figure 3 The initialization operation on the quantum bit corresponding to quantum bit 2 (numbered 2) is postponed until the measurement operation on the quantum bit corresponding to quantum bit 0 (numbered 8), which is equivalent to adding a directed edge from node 8 to node 2 to the graph in the corresponding graph representation. As shown in Figure 5(b), the directed acyclic graph after adding the directed edge corresponds to the compiled dynamic quantum circuit.

[0070] The purpose of this embodiment is to transform the compilation problem of the static quantum circuit into an equivalent graph optimization problem, and to compile the static quantum circuit into an equivalent dynamic quantum circuit by searching for directed edges from the output node to the input node in the directed acyclic graph of the static quantum circuit. The more directed edges from the connected output node to the input node, the better the effect of the equivalent compilation, that is, the fewer quantum bits of the obtained dynamic quantum circuit.

[0071] In step S101, the first quantum circuit is a static quantum circuit, and the first directed acyclic graph can be determined based on the first instruction list of the first quantum circuit. The first directed acyclic graph includes nodes corresponding to instructions in the first instruction list and directed edges between the nodes, the directed edges between the nodes are used to characterize the timing relationship between different instructions in the first instruction list, and the paths formed by the directed edges between the nodes do not include directed loops.

[0072] In an optional implementation, the first instruction list can be traversed in the order of instruction arrangement from left to right, and the instruction sublist in the first instruction list that is sorted before the currently traversed instruction and the first quantum bit acted on by the currently traversed instruction are obtained; the instruction sublist is traversed in the order of instruction arrangement from right to left, and the first target instruction whose acted quantum bit intersects with the first quantum bit is obtained; the identifier of the first target instruction is used as the source node and the identifier of the currently traversed instruction is used as the target node to construct a directed edge; when the traversal of the first instruction list is completed, a first directed acyclic graph is obtained based on the constructed directed edges.

[0073] Optionally, the step S101 specifically includes:

[0074] Traversing the first instruction list according to the arrangement order of the operation instructions;

[0075] Take the currently traversed operation instruction as a node, and if the sixth list is not an empty list, add the node corresponding to the operation instruction at the end of the sixth list to the directed edge corresponding to the node of the currently traversed operation instruction; the sixth list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

[0076] The currently traversed operation instruction is added to the end of the sixth list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0077] The specific process is as follows:

[0078] Input: static quantum circuit instruction list Static_Circuit, width n;

[0079] Output: the first directed acyclic graph Digraph, the input node list Inputs and the output node list Outputs.

[0080] Step 1: Initialize an empty directed acyclic graph Digraph;

[0081] Step 2: Initialize a list Causal_Lists of length n, where each element is an empty list;

[0082] Step 3: Initialize two lists Inputs and Outputs of length n, where each element is initialized to None;

[0083] Step 4: Loop through Static_Circuit, assuming that the element currently being traversed is Instruction and its number index is Index:

[0084] Step 4.1: Add Index as a node to the directed acyclic graph Digraph;

[0085] Step 4.2: If Instruction is a qubit reset operation, obtain the qubit it acts on, and modify the value of the qubit indexed in the Inputs list to Index;

[0086] Step 4.3: If Instruction is a quantum bit measurement operation, obtain the quantum bit qubit it acts on, and modify the value of the Outputs list indexed as qubit to Index;

[0087] Step 4.4: Get the qubit value in the Instruction instruction and loop it. Let the looped element be q. Find the last element of the list Causal_Lists[q] (i.e., the sixth list) and record it as PreInstruction. If PreInstruction is not an empty element, add a directed edge from PreInstruction to Instruction to the directed acyclic graph Digraph. Add Index to the end of the list Causal_Lists[q].

[0088] Step 5: Return Digraph, Inputs and Outputs as output.

[0089] In this way, by creating a list corresponding to each quantum bit to store its corresponding operation instructions in order, it is very convenient to find the previous operation instructions associated with each operation instruction and construct directed edges, so that the first directed acyclic graph can be constructed very quickly and at high speed.

[0090] The search level is used to indicate the number of target output nodes for searching for feasible solutions using brute force search, where a feasible solution refers to a connection method of directed edges from output nodes to input nodes in a directed acyclic graph with constraints added. Constraints include:

[0091] 1) In order to make the entire graph still conform to the timing relationship of the circuit instructions, it is necessary to ensure that the entire graph is still acyclic after adding more directed edges. It should be noted that the direction of the directed edges in the graph represents the timing relationship of the instructions, and the ring structure will destroy this relationship. That is, after adding directed edges, there should still be no ring structure path in the graph (called a directed loop);

[0092] 2) Each output node can only be connected to one input node at most, indicating that after the output node is measured, the input node it points to continues to perform operations on the qubit;

[0093] 3) Different output nodes cannot be connected to the same input node.

[0094] The brute force search method refers to enumerating all feasible solutions of the directed edges from the output node to the input node in the directed acyclic graph by enumeration. The search level can be expressed by an integer or a percentage, which is not specifically limited here.

[0095] The search level may be preset, input by a user, or determined based on relevant information such as the number of quantum bits in the first quantum circuit, and is not specifically limited here.

[0096] Step S102: Select a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level.

[0097] The target output node can be selected arbitrarily from the output node list, or the target output node can be selected from the output node list by using the connectivity from the output node to the input node in the first directed acyclic graph. For example, the output node with the best or worst connectivity can be selected from the output node list as the target output node. The connectivity of the output node can be determined by the number of input nodes connected to it. The more the number of connectable input nodes is, the better the connectivity of the output node is, and the fewer the number of connectable input nodes is, the worse the connectivity of the output node is.

[0098] The number of target output nodes in the first list matches the search level, for example, the number of target output nodes is equal to the search level, or when the search level is expressed as a percentage, the number of target output nodes is obtained by multiplying the search level by the number of output nodes.

[0099] Step S103: Based on the first directed acyclic graph, the first list and the input node list of the first directed acyclic graph, determine a first set including target feasible solutions, wherein the target feasible solutions indicate input nodes to which each target output node can be connected.

[0100] Based on the first directed acyclic graph, the first list and the input node list, a brute force search method can be used to enumerate all target feasible solutions of input nodes to which each target output node in the first directed acyclic graph can be connected, so as to obtain a first set.

[0101] Step S104: For each target feasible solution, determine in turn the target directed edges that can be added to the second directed acyclic graph to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes other output nodes in the output node list except the first list, and the third list includes other input nodes in the input node list except the input nodes indicated by the target feasible solution.

[0102] For each target feasible solution, the directed edge indicated by the target feasible solution is added to the first directed acyclic graph to obtain a second directed acyclic graph. At the same time, the target output node in the output node list is removed to obtain a second list, and the output nodes connected to the target feasible solution indication in the input node list are removed to obtain a third list.

[0103] Afterwards, based on the second directed acyclic graph, the second list and the third list, a heuristic method is adopted to determine the target directed edges from the output node in the second list to the input node in the third list in sequence according to preset rules, and add them to the second directed acyclic graph in sequence until there are no directed edges from the output node to the input node in the second directed acyclic graph to be added, thereby obtaining a new directed acyclic graph.

[0104] Among them, the preset rule can be: give priority to selecting the output node with the least number of connectable input nodes in the second list, and the target directed edge is the directed edge between the selected output node and an input node in the third list. The preset rule can also be: score the candidate directed edges of the second directed acyclic graph, and select the candidate directed edge with the largest score value. The preset rule can also be other rules, which are not specifically limited here.

[0105] Accordingly, for each target feasible solution, a fourth table can be determined.

[0106] Step S105: Based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and a directed edge indicating a target feasible solution corresponding to the fourth list, and the third directed acyclic graph is obtained by adding the directed edges in the target list to the first directed acyclic graph.

[0107] The fourth list determined for the target feasible solution can be merged with the directed edges indicated by the target feasible solution to obtain a fifth list. Accordingly, the target list is the list with the largest length among the fifth lists, which corresponds to the list with the largest number of directed edges that can be added to the first directed acyclic graph determined by using brute force search and heuristic methods.

[0108] After adding the directed edge from the output node to the input node in the target list in the first directed acyclic graph to obtain the third directed acyclic graph, the timing relationship between the nodes can be determined based on the third directed acyclic graph, and the first instruction list can be reordered based on the timing relationship. After that, the relationship between the input node and the output node in the target list can be used to equivalently compile the instructions that act on other quantum bits (i.e., the quantum bits acted on by the instructions corresponding to the input nodes that are directionally connected to the output nodes) after the measurement instruction into instructions that act on the quantum bits acted on by the measurement instruction. In this way, the equivalent compilation of the first quantum circuit can be achieved, and a second instruction list for a second quantum circuit equivalent to the first quantum circuit can be obtained, and the quantum bits required in the second quantum circuit are fewer than the quantum bits required in the first quantum circuit.

[0109] In this embodiment, a brute force search is applied to a subset of the specified output nodes based on the search hierarchy, that is, all possible connection methods of the output nodes in the subset are exhaustively enumerated, and for each possible connection method, the edges that can be added to the remaining output nodes are obtained by a heuristic method. After that, the connection method with the largest number of directed edges that can be added to the directed acyclic graph among all compilation schemes is selected for connection, and the equivalent compilation of the static quantum circuit is performed based on the updated directed acyclic graph. The search hierarchy depicts the hierarchical changes between the brute force search method and the heuristic method, and provides an opportunity to balance the equivalent compilation effect and the compilation time, which can improve the effect of the equivalent compilation of the quantum circuit, reduce the number of quantum bits required for the compiled dynamic quantum circuit, and improve scalability. Users can balance the equivalent compilation effect and the compilation time, which improves flexibility.

[0110] Optionally, the step S105 specifically includes:

[0111] Based on the third directed acyclic graph, reorder the instructions in the first instruction list to obtain a third instruction list;

[0112] Based on the target list, instructions in the third instruction list are equivalently compiled to obtain the second instruction list.

[0113] In order to further compile the third directed acyclic graph into an instruction list of a dynamic quantum circuit, a feasible execution order of the dynamic quantum circuit instructions can be obtained by topologically sorting the third directed acyclic graph. That is, the topological sorting corresponding to the third directed acyclic graph is obtained, and based on the topological sorting, the instructions in the first instruction list are reordered to obtain the third instruction list.

[0114] The topological sorting of a directed acyclic graph refers to a linear arrangement of the nodes in the graph, so that for all directed edges (u, v) in the graph, node u appears before node v. The directed acyclic graph contains the order of execution of circuit operation instructions, so the topologically sorted list corresponds to a feasible instruction execution order list, which can be traversed and the quantum bits corresponding to the operation instructions can be updated according to the added directed edges, so as to obtain the instruction list of the compiled dynamic quantum circuit.

[0115] The process of equivalently compiling the first quantum circuit based on the third directed acyclic graph to obtain the dynamic quantum circuit, i.e., the second quantum circuit, is as follows:

[0116] Input: the instruction list Static_Circuit of the first quantum circuit, the directed acyclic graph Digraph after adding directed edges, i.e. the third directed acyclic graph, and the target list Added_Edges;

[0117] Output: The instruction list of the dynamic quantum circuit Dynamic_Circuit.

[0118] Step 1: Initialize two empty lists Topological_order and Dynamic_Circuit;

[0119] Step 2: Topologically sort the Digraph and store the results in the Topological_order list;

[0120] Step 3: Loop through the Topological_order list and set the currently traversed element as Vertex;

[0121] Step 3.1: Add the element indexed as Vertex in the Static_Circuit list to the end of the Dynamic_Circuit list (i.e., reorder to obtain the third instruction list);

[0122] Step 4: Loop through the Added_Edges list and set the currently looped element to Edge;

[0123] Step 4.1: Record the two nodes of Edge as Tail and Head respectively;

[0124] Step 4.2: Record the qubits acted upon by the instructions indexed as Head and Tail in the Static_Circuit list as q i and q j ;

[0125] Step 4.3: Loop through the Dynamic_Circuit list, set the currently traversed element to be Instruction; loop through the list of qubits that Instruction acts on, set the currently traversed element to be q; if q = q i , then update q to q j ;

[0126] Step 5: Return the Dynamic_Circuit list as output.

[0127] In this way, the third directed acyclic graph can be effectively utilized to easily implement equivalent compilation of the first quantum circuit.

[0128] Optionally, the step S101 specifically includes:

[0129] Based on the target information, determining the search level;

[0130] The target information includes at least one of the following:

[0131] The number of qubits of the first quantum circuit, the search level is inversely proportional to the number of qubits of the first quantum circuit;

[0132] the number of qubits of the second quantum circuit, the search level being inversely proportional to the number of qubits of the second quantum circuit;

[0133] The preset compile time of the first quantum circuit, and the search level is proportional to the preset compile time.

[0134] Since the compilation complexity grows exponentially with the search level, a larger search level can be used for quantum circuits with fewer qubits (such as dozens of qubits); a smaller search level can be used for quantum circuits with more qubits (such as hundreds of qubits). The larger the search level, the better the compilation effect (that is, the fewer qubits are required for the compiled dynamic quantum circuit). Therefore, if the required dynamic quantum circuit has fewer qubits, a larger search level can be used.

[0135] In addition, according to actual needs, the search level can be gradually increased from 1 until the required compilation effect is achieved (that is, the number of quantum bits of the compiled dynamic quantum circuit reaches a corresponding number) or the upper limit of the preset compilation time that can be tolerated is reached.

[0136] In the case where the target information includes multiple items, the search levels determined by each item may be weighted and summed, or the smallest search level may be selected as the final search level.

[0137] In this way, the search level can be automatically determined based on the target information, achieving a trade-off between the equivalent compilation effect and compilation time of the quantum circuit.

[0138] Optionally, the method further includes:

[0139] Determining a compilability factor based on the number of qubits of the first quantum circuit and the number of qubits of the second quantum circuit, the compilability factor indicating a compilability degree of the first quantum circuit;

[0140] Based on the compilability factor, the search level is adjusted.

[0141] In an optional implementation, the specific definition of the compilability factor is as shown in the following formula (1).

[0142]

[0143] Among them, n is the width of the input static quantum circuit, that is, the first quantum circuit, and n' is the width of the output dynamic quantum circuit, that is, the second quantum circuit. It can be seen that the higher the compilability factor b value, the better the circuit compilation effect, that is, the higher the compilation degree of the first quantum circuit, and the lower the compilability factor b value, the worse the circuit compilation effect, that is, the lower the compilation degree of the first quantum circuit.

[0144] When the compilability factor indicates that the compilability of the first quantum circuit is low, such as when the compilability factor is lower than a preset threshold, the search level can be increased, and the first quantum circuit can be re-compiled equivalently to improve the compilability of the first quantum circuit. In this way, while ensuring the compiling time, the compiling effect of the first quantum circuit can be improved, that is, the number of quantum bits required for the compiled dynamic quantum circuit can be reduced.

[0145] Optionally, the number of input nodes that the target output node can connect to is less than or equal to the number of input nodes that other output nodes in the output node list can connect to.

[0146] The target output node can be selected from the output node list by utilizing the connectivity from the output node to the input node in the first directed acyclic graph. Specifically, the target output node can be selected from the output node list based on the connectivity information of the first directed acyclic graph. The connectivity information can be represented by a candidate edge matrix.

[0147] Due to the restrictions of directed acyclic graph conditions, not all edges pointing from output nodes to input nodes can be added to the graph. In fact, after obtaining the graph representation of the static quantum circuit, all edges that will not directly introduce a ring structure (hereinafter referred to as candidate directed edges) can be obtained through the graph search algorithm. If there is no path between the input node with index i and the output node with index j in the directed acyclic graph of the static quantum circuit (that is, the input node i cannot reach the output node j; otherwise, it is called reachable), then connecting the output node with index j and the input node with index i will not directly introduce a ring in the graph, so such an edge is a candidate directed edge. Assuming that a static quantum circuit contains n input nodes and m output nodes, all candidate directed edges can be saved by an m×n matrix, which is called a candidate edge matrix. Among them, the jth row corresponds to the output node with index j, and the ith column corresponds to the input node with index i, and the matrix element (j,i) = 1 indicates that the edge between the output node with index j and the input node with index i is a candidate directed edge; otherwise, the matrix element is 0. Among them, the matrix index can start from 0.

[0148] The candidate edge matrix can be obtained based on the depth-first algorithm, and the process is as follows:

[0149] Input: directed acyclic graph Digraph, input node list Inputs, output node list Outputs;

[0150] Output: candidate edge matrix C.

[0151] Step 1: Get the length of the input and output node lists, denoted as n and m respectively;

[0152] Step 2: Initialize an m×n matrix C of all zeros;

[0153] Step 3: Loop through the input node list Inputs, and set the element currently being looped to be Input, and its index to be i;

[0154] Step 3.1: Loop through the output node list Outputs, set the element currently being looped to Output, and its index is j; search the Digraph using a depth-first algorithm or other algorithm to see if there is a path from Input to Output; if the path does not exist, set the matrix element (j,i) of the matrix C to 1; if the path exists, do not perform any operation and continue looping the next element;

[0155] Step 4: Return the candidate edge matrix C as output.

[0156] When the candidate edge matrix C is obtained, the sum of each row of the candidate edge matrix C can be calculated, and the output nodes corresponding to the first L smallest non-zero elements in each row sum are used as target output nodes. Accordingly, the number of input nodes that can be connected to the target output node is less than or equal to the number of input nodes that can be connected to other output nodes in the output node list. Wherein, L is the search level.

[0157] In this way, the selection of the target output node can be achieved and the compilation time of the quantum circuit can be reduced.

[0158] Optionally, the step S103 specifically includes:

[0159] For each target output node in the first list, obtaining a second set corresponding to the target output node, the second set including input nodes to which the target output node in the input node list can be connected;

[0160] A Cartesian product is performed on the second sets corresponding to the target output nodes to obtain a first set including target feasible solutions, wherein identifiers for indicating input nodes in the target feasible solutions cannot be repeated.

[0161] In this way, all possible connection modes for the target output node in the first list can be realized by brute force search. In addition, brute force search can be performed on the connection mode of the output node, and brute force search can also be performed on the input node.

[0162] Optionally, the step of sequentially determining target directed edges that can be added to the second directed acyclic graph to obtain a fourth list includes:

[0163] Determine target directed edges from the candidate directed edges of the second directed acyclic graph in sequence, and add the target directed edges in sequence, until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining the fourth list;

[0164] Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the second directed acyclic graph, and the score value is used to represent the maximum value of the number of directed edges that can be connected from the output node to the input node in the fourth directed acyclic graph, and the fourth directed acyclic graph is obtained after adding the candidate directed edges to the second directed acyclic graph.

[0165] A heuristic method may be used to sequentially determine the target directed edge from the candidate directed edges of the second directed acyclic graph. In the heuristic method, a maximum candidate edge greedy strategy may be used to determine the target directed edge.

[0166] The greedy strategy is to select the local optimal solution according to some predefined scoring criteria at each step, so as to obtain the global optimal solution. When this strategy is applied to quantum circuit equivalent compilation, it is hoped that after adding a candidate directed edge, the number of subsequent candidate directed edges available for selection will be as large as possible. Therefore, the number of subsequent candidate directed edges can be used as the scoring criterion for each step.

[0167] In a round of determining the target directed edge, a zero matrix with the same size as the candidate edge matrix is ​​initialized, called the scoring matrix, which is used to store the scores of all candidate directed edges in this round. By looping through all candidate directed edges in this round, for a candidate directed edge that is traversed, it is temporarily added to the graph, and then the candidate edge matrix needs to be updated.

[0168] Let the matrix element corresponding to the candidate edge currently traversed be (u, v), and let the set of all input nodes that can reach the output node u before adding the candidate directed edge be R u , and the set of all output nodes reachable by input node v is T v , then after adding the candidate directed edge (u,v), R u Any input node in can reach T v Therefore, all edges (t,r) are no longer candidate directed edges, where t∈T v , r∈R u , the corresponding matrix element needs to be updated to 0. At the same time, since an input / output node can add at most one edge, all matrix elements in the uth row and vth column of the candidate edge matrix need to be updated to 0. Then the number of matrix elements 1 in the updated candidate edge matrix is ​​calculated and stored as the score of the candidate directed edge in the matrix element corresponding to the candidate directed edge in the scoring matrix. After all candidate directed edges in a certain round are scored, the matrix element with the highest score in the scoring matrix is ​​selected. The corresponding candidate edge is the edge added to the graph in this round, the candidate edge matrix is ​​updated, and the next cycle continues.

[0169] Figure 6 is a schematic diagram of the structure of another example of a static quantum circuit. Figure 7 yes Figure 6 Schematic diagram of the structure of the directed acyclic graph of the circuit shown. Figure 7 In the above, the nodes corresponding to the intermediate operations of the quantum circuit are ignored, and only the input / output nodes are retained. The path from the input node through the intermediate nodes to the output node is simplified to a directed edge from the input node to the output node.

[0170] Its initial candidate edge matrix is ​​shown in Figure 8(a). Assume that its row and column indices are represented as {t0,…,t4} and {r0,…,r4} respectively. In this example, assume that the candidate directed edge currently traversed is (t3,r1) (the matrix element marked by box 801 in Figure 8(a)). Before adding this candidate directed edge, the set of all input nodes that can reach the output node t3 is R3 = {r0,r2,r3,r4}, and the set of all output nodes that can be reached by the input node r1 is T1 = {t1}. Therefore, after adding the candidate directed edge (t3,r1), the edges corresponding to T1×R3 = {(t1,r0), (t1,r2), (t1,r3), (t1,r4)} will no longer be candidate directed edges.

[0171] like Fig. 9 As shown in FIG8(b), for the convenience of display, the candidate edges of other output nodes are ignored in the figure. The edge marked by the dotted line 901 is the candidate directed edge (t3, r1) currently traversed, and the edge marked by the solid line 902 is the part of the candidate directed edge that should be deleted from the candidate edge matrix after adding the candidate directed edge (t3, r1). The corresponding matrix element should be updated to 0, as shown in FIG8(b) (the matrix element marked by the box 802 in FIG8(b)).

[0172] At the same time, all matrix elements in the 3rd row and 1st column of the candidate edge matrix should also be updated to 0, as shown in FIG8(c) (the matrix elements marked by box 803 in FIG8(c)). The updated candidate edge matrix is ​​shown in FIG8(c).

[0173] The specific process of sequentially determining the target directed edges that can be added to the second directed acyclic graph in a heuristic manner is as follows:

[0174] Input: the directed acyclic graph Digraph (i.e., the second directed acyclic graph) corresponding to the static quantum circuit, the input node list Inputs (i.e., the third list) and the output node list Outputs (i.e., the second list) of the directed acyclic graph Digraph, and the candidate edge matrix C;

[0175] Output: Modified_Digraph, the directed acyclic graph after the directed edges are added, and Added_Edges (the fourth list), the list of all candidate directed edges added to the directed acyclic graph.

[0176] Step 1: Get the length of the input and output node lists, denoted as n and m respectively;

[0177] Step 2: Initialize an empty list Added_Edges;

[0178] Step 3: When the candidate edge matrix is ​​not a zero matrix, perform the following operations;

[0179] Step 3.1: Initialize an m×n zero matrix S;

[0180] Step 3.2: Traverse the non-zero matrix elements of matrix C, set the currently traversed matrix element to (i, j); initialize a matrix C i,j =C; the matrix C i,j The column indices of all 0 elements in the i-th row are recorded as a set R i ; The matrix C i,j The row indices of all 0 elements in the jth column are recorded as a set T j ; Calculate the set T j and R i The Cartesian product of is recorded as a Pairs list; traverse the Pairs list, and set the element currently traversed to (u, v); i,j Set the matrix elements (u,v) of i,j All matrix elements in row i and column j are set to 0; calculate the matrix C i,j The sum of all matrix elements is recorded as Score; the matrix element (i, j) of matrix S is set to Score+1;

[0181] Step 3.3: Get all matrix elements with the highest score in matrix S and record them as Max_Score;

[0182] Step 3.4: Randomly select a matrix element from Max_Score and record it as (t,r);

[0183] Step 3.5: Add the directed edge (Outputs[t], Inputs[r]) to Added_Edges;

[0184] Step 3.6: Update the matrix C to matrix C t,r ;

[0185] Step 4: Add all directed edges in Added_Edges to the Digraph;

[0186] Step 5: Return Modified_Digraph and Added_Edges as output.

[0187] In this way, the target directed edges are determined in sequence by a heuristic method and the maximum candidate edge greedy strategy, until there are no directed edges from the output node to the input node that can be added in the second directed acyclic graph. This improves the efficiency of the directed edge search while ensuring the superiority of the directed edge search.

[0188] Optionally, the connectivity information of the directed acyclic graph is represented by a matrix, and the connectivity information is used to characterize the connectivity of each output node to the input node in the directed acyclic graph. The scoring value of the candidate directed edge is based on the non-zero elements in the first matrix plus 1. The first matrix represents the connectivity information of the fourth directed acyclic graph.

[0189] The scoring rule is: the sum of the non-zero elements in the first matrix plus 1. Selecting the sum of the non-zero elements of the updated candidate edge matrix plus 1 as the score can leave more room for selection for subsequent operations. In the numerical experiment process, the compilation effect of the greedy strategy of this scoring rule is significantly improved compared with related technologies.

[0190] When scoring a candidate directed edge, the actual score is the sum of the non-zero elements in the first matrix plus 1. The reason is that when the non-zero elements and sum(C i,j )=0, it is necessary to distinguish the candidate directed edge (whose score is 1) from the non-candidate directed edge (whose score is 0) in the scoring matrix.

[0191] Optionally, determining a target directed edge from candidate directed edges of the second directed acyclic graph includes:

[0192] When there are at least two candidate directed edges with the largest scores among the candidate directed edges of the second directed acyclic graph, a target directed edge is randomly selected from the candidate directed edges with the largest scores.

[0193] When there are multiple candidate directed edges in a certain cycle that meet the highest score at the same time, a certain degree of randomness can be introduced in the selection process. That is, when there are multiple candidate directed edges that meet the conditions, one can be randomly selected as the target directed edge to be added in this round. At the same time, in order to reduce the uncertainty caused by randomness, the input static quantum circuit can be compiled multiple times, and the one with the best compilation effect can be selected as the output result.

[0194] Compared with selecting the target directed edge to be added in this round according to deterministic rules (such as fixedly selecting the candidate directed edge with the smallest sum of row index and column index among all candidate directed edges that meet the conditions as the target directed edge to be added), since any rearrangement of the quantum bit index in the input quantum circuit will cause the row and column indices of the candidate edge in the matrix to change, randomly selecting candidate directed edges can avoid the limitation of relying on the arrangement of quantum bits, further improving the flexibility of quantum circuit processing.

[0195] In one example, the specific process of performing quantum circuit equivalent compilation based on the search level is as follows:

[0196] Input: directed acyclic graph Digraph corresponding to the static quantum circuit, input node list Inputs, output node list Outputs, candidate edge matrix C and search level L;

[0197] Output: Modified_Digraph, the directed acyclic graph after the directed edges are added, and Added_Edges, a list of all candidate directed edges added to the directed acyclic graph.

[0198] Step 1: Initialize five empty lists Max_Edges, Candidate_Num, Idx_Outputs, Idx_Inputs and Search_Space;

[0199] Step 2: Calculate the sum of each row of the candidate edge matrix C and record the result in Candidate_Num;

[0200] Step 3: Record the indexes of the first L smallest non-zero elements in Candidate_Num in Idx_Outputs (i.e., the first list);

[0201] Step 4: Loop through Idx_Outputs and set the currently traversed element as Index;

[0202] Step 4.1: Record the column indices of all non-zero elements in the Indexth row of matrix C as set R (i.e., the second set);

[0203] Step 4.2: Add an element None to R and add R to the end of the Idx_Inputs list;

[0204] Step 5: Record the Cartesian product of all sets in the Idx_Inputs list in Search_Space;

[0205] Step 6: Delete all duplicate elements (except None) in Search_Space;

[0206] Step 7: Loop through Search_Space (i.e., the first set including the target feasible solution), assuming that the element currently traversed is Solution (i.e., the target feasible solution);

[0207] Step 7.1: Initialize an empty list Added_Edges;

[0208] Step 7.2: Initialize two lists Inputs_Copy (i.e. the third list) and Outputs_Copy (i.e. the second list) as Inputs and Outputs;

[0209] Step 7.3: Loop from i=0 to L-1; if Solution[i] is not None, add the directed edge (Outputs[Idx_Outputs[i]], Inputs[Solution[i]]) to Added_Edges; set Outputs_Copy[Idx_Outputs[i]] and Inputs_Copy[Solution[i]] to None respectively;

[0210] Step 7.4: The graph after Added_Edges is added to the Digraph is recorded as Modified_Digraph (i.e., the second directed acyclic graph);

[0211] Step 7.5: If Modified_Digraph is an acyclic graph; take Modified_Digraph, Inputs_Copy and Outputs_Copy as input, and use a heuristic method to obtain the directed edge list Edges (i.e., the fourth list) that can continue to be added; add the Edges list to the end of Added_Edges; if the length of the Added_Edges list is greater than the Max_Edges list, update the Max_Edges list to the Added_Edges list;

[0212] Step 8: Add all directed edges in Max_Edges (i.e., the target list) to Digraph, and record the updated graph as Max_Digraph (i.e., the third directed acyclic graph);

[0213] Step 9: Return Max_Digraph and Max_Edges as output.

[0214] Afterwards, based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0215] Considering that the search space is the Cartesian product of the connectable input node sets of all target output nodes in the first list, L target output nodes with the least connectable input nodes are obtained, thereby greatly narrowing the search space.

[0216] For each target output node in the first list, a None element is added to its connectable input node set, indicating that the target output node is not connected to any input node.

[0217] In order to demonstrate the advantages of the equivalent compilation effect of this embodiment over related technologies, the equivalent compilation effects of different schemes on quantum circuits are compared through some numerical experiments of circuit compilation.

[0218] The quantum circuit compilation scheme of this embodiment can be compared with the compilation effects of the maximum cut QAOA circuit on the randomly generated 3-regular graph by the related technology 1 and the related technology 2. For each initial circuit width, 20 different 3-regular graphs and their corresponding maximum cut QAOA circuits can be randomly generated and compiled using different schemes.

[0219] Fig.10 Each data point in is the average value of the widths of 20 random circuits after compilation. It can be seen that the compilation effect of the technical solution of this embodiment (represented by curve 1001) is improved compared with the compilation effects of related technology 1 and related technology 2 (represented by curve 1002 and curve 1003 respectively), that is, the number of bits of the compiled quantum circuit is reduced compared with the related technology.

[0220] Considering that the maximum cut QAOA circuits are highly structured, in order to demonstrate the compilation effect on more general circuits, the compilation effects of different schemes on random quantum circuits can be compared. In this section, the ratio of the number of two-qubit gates m and the number of qubits n in the circuit is fixed to {1, 1.5, 2, 2.5}, an input quantum circuit width is randomly selected from 10 to 70, and the quantum circuit is constructed by randomly generating two-qubit gates, and then compiled using different schemes. For each ratio of two-qubit gates to qubits, 200 different circuit instances were tested. The compilability factor (an evaluation index of the circuit compilation effect) can be used to represent the circuit compilation effect of a certain scheme. Among them, the compilability factor can be defined using the above formula (1).

[0221] Fig.11 and Fig.12 The comparison of the compilability factors of random quantum circuits by different schemes is shown. Fig.11 and Fig.12 The horizontal axis is the compilability factor of the random quantum circuit obtained by using the related technology 1 and the related technology 2, and the vertical axis is the compilability factor of the random quantum circuit obtained by using the technical solution of this embodiment.

[0222] Fig.11 and Fig.12The black auxiliary line in represents y=x. Obviously, for most random quantum circuits, the data points fall above the auxiliary line. It can be seen that the compilation effect of the technical solution of this embodiment on random circuits is better than that of related technologies 1 and 2. In particular, as shown by data point 1101, for the case where m / n is small, the random quantum circuit itself can be compiled to a greater extent, and the number of quantum bits can be reduced more. The technical solution of this embodiment has a better compilation effect on it.

[0223] Second embodiment

[0224] like Fig.13 As shown, the present disclosure provides a quantum circuit processing device 1300, comprising:

[0225] An acquisition module 1301 is used to acquire a first directed acyclic graph of a first quantum circuit and acquire a search level of the first directed acyclic graph;

[0226] A selection module 1302 is used to select a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level;

[0227] A first determining module 1303 is used to determine a first set including target feasible solutions based on the first directed acyclic graph, the first list and the input node list of the first directed acyclic graph, wherein the target feasible solution indicates input nodes to which each target output node can be connected;

[0228] The second determination module 1304 is used to determine, for each target feasible solution, target directed edges that can be added to the second directed acyclic graph in turn to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes other output nodes in the output node list except the first list, and the third list includes other input nodes in the input node list except the input nodes indicated by the target feasible solution;

[0229] An equivalent compilation module 1305 is used to perform equivalent compilation on the first quantum circuit based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and a directed edge indicating a target feasible solution corresponding to the fourth list, and the third directed acyclic graph is obtained by adding the directed edges in the target list to the first directed acyclic graph.

[0230] Optionally, the acquisition module 1301 is specifically used to:

[0231] Based on the target information, determining the search level;

[0232] The target information includes at least one of the following:

[0233] The number of qubits of the first quantum circuit, the search level is inversely proportional to the number of qubits of the first quantum circuit;

[0234] the number of qubits of the second quantum circuit, the search level being inversely proportional to the number of qubits of the second quantum circuit;

[0235] The preset compile time of the first quantum circuit, and the search level is proportional to the preset compile time.

[0236] Optionally, the device further comprises:

[0237] A third determination module, configured to determine a compilability factor based on the number of quantum bits of the first quantum circuit and the number of quantum bits of the second quantum circuit, wherein the compilability factor indicates a compilability degree of the first quantum circuit;

[0238] An adjustment module is used to adjust the search level based on the compilability factor.

[0239] Optionally, the number of input nodes that the target output node can connect to is less than or equal to the number of input nodes that other output nodes in the output node list can connect to.

[0240] Optionally, the acquisition module 1301 is specifically used to:

[0241] Traversing the first instruction list according to the arrangement order of the operation instructions;

[0242] Take the currently traversed operation instruction as a node, and if the sixth list is not an empty list, add the node corresponding to the operation instruction at the end of the sixth list to the directed edge corresponding to the node of the currently traversed operation instruction; the sixth list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

[0243] The currently traversed operation instruction is added to the end of the sixth list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0244] Optionally, the first determining module 1303 is specifically configured to:

[0245] For each target output node in the first list, obtaining a second set corresponding to the target output node, the second set including input nodes to which the target output node in the input node list can be connected;

[0246] A Cartesian product is performed on the second sets corresponding to the target output nodes to obtain a first set including target feasible solutions, wherein identifiers for indicating input nodes in the target feasible solutions cannot be repeated.

[0247] Optionally, the second determining module 1304 is specifically configured to:

[0248] Determine target directed edges from the candidate directed edges of the second directed acyclic graph in sequence, and add the target directed edges in sequence, until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining the fourth list;

[0249] Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the second directed acyclic graph, and the score value is used to represent the maximum value of the number of directed edges that can be connected from the output node to the input node in the fourth directed acyclic graph, and the fourth directed acyclic graph is obtained after adding the candidate directed edges to the second directed acyclic graph.

[0250] Optionally, the connectivity information of the directed acyclic graph is represented by a matrix, and the connectivity information is used to characterize the connectivity of each output node to the input node in the directed acyclic graph. The scoring value of the candidate directed edge is based on the non-zero elements in the first matrix plus 1. The first matrix represents the connectivity information of the fourth directed acyclic graph.

[0251] Optionally, the second determining module 1304 is further configured to:

[0252] When there are at least two candidate directed edges with the largest scores among the candidate directed edges of the second directed acyclic graph, a target directed edge is randomly selected from the candidate directed edges with the largest scores.

[0253] The quantum circuit processing device 1300 provided in the present disclosure can implement each process implemented in the quantum circuit processing method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0254] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0255] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0256] Fig.14 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0257] like Fig.14 As shown, the device 1400 includes a computing unit 1401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1402 or a computer program loaded from a storage unit 1408 into a random access memory (RAM) 1403. In the RAM 1403, various programs and data required for the operation of the device 1400 can also be stored. The computing unit 1401, the ROM 1402, and the RAM 1403 are connected to each other via a bus 1404. An input / output (I / O) interface 1405 is also connected to the bus 1404.

[0258] A number of components in the device 1400 are connected to the I / O interface 1405, including: an input unit 1406, such as a keyboard, a mouse, etc.; an output unit 1407, such as various types of displays, speakers, etc.; a storage unit 1408, such as a disk, an optical disk, etc.; and a communication unit 1409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1409 allows the device 1400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0259] The computing unit 1401 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1401 performs the various methods and processes described above, such as the quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1408. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1400 via the ROM 1402 and / or the communication unit 1409. When the computer program is loaded into the RAM 1403 and executed by the computing unit 1401, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1401 may be configured to execute the quantum circuit processing method in any other appropriate manner (for example, by means of firmware).

[0260] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0261] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0262] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0263] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0264] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0265] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0266] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0267] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising: Obtaining a first directed acyclic graph of a first quantum circuit, and obtaining a search level of the first directed acyclic graph; Selecting a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level; Determining, based on the first directed acyclic graph, the first list, and the input node list of the first directed acyclic graph, a first set including target feasible solutions, the target feasible solutions indicating input nodes to which each target output node can be connected; For each target feasible solution, determine in turn the target directed edges that can be added to the second directed acyclic graph to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes the output nodes in the output node list except the first list, the third list includes the input nodes in the input node list except the input nodes indicated by the target feasible solution, and the fourth list includes the target directed edges; Based on the third directed acyclic graph, the target list and the first instruction list of the first quantum circuit, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and directed edges indicating target feasible solutions corresponding to the fourth list, the third directed acyclic graph is obtained by adding directed edges in the target list to the first directed acyclic graph, and the first instruction list includes operation instructions of the first quantum circuit.

2. The method according to claim 1, wherein: The obtaining of the search level of the first directed acyclic graph includes: Based on the target information, determining the search level; The target information includes at least one of the following: The number of qubits of the first quantum circuit, the search level is inversely proportional to the number of qubits of the first quantum circuit; the number of qubits of the second quantum circuit, the search level being inversely proportional to the number of qubits of the second quantum circuit; The preset compile time of the first quantum circuit, and the search level is proportional to the preset compile time.

3. The method according to claim 1, further comprising: Determining a compilability factor based on the number of qubits of the first quantum circuit and the number of qubits of the second quantum circuit, the compilability factor indicating a compilability degree of the first quantum circuit; Based on the compilability factor, the search level is adjusted.

4. The method according to claim 1, wherein: The number of input nodes that the target output node can connect to is less than or equal to the number of input nodes that other output nodes in the output node list can connect to.

5. The method according to claim 1, wherein: The step of obtaining a first directed acyclic graph of a first quantum circuit comprises: Traversing the first instruction list according to the arrangement order of the operation instructions; Take the currently traversed operation instruction as a node, and if the sixth list is not an empty list, add the node corresponding to the operation instruction at the end of the sixth list to the directed edge corresponding to the node of the currently traversed operation instruction; the sixth list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instruction is added to the end of the sixth list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

6. The method according to claim 1, wherein: The determining, based on the first directed acyclic graph, the first list, and the input node list of the first directed acyclic graph, a first set including target feasible solutions comprises: For each target output node in the first list, obtaining a second set corresponding to the target output node, the second set including input nodes to which the target output node in the input node list can be connected; A Cartesian product is performed on the second sets corresponding to the target output nodes to obtain a first set including target feasible solutions, wherein identifiers for indicating input nodes in the target feasible solutions cannot be repeated.

7. The method according to claim 1, wherein: The step of sequentially determining target directed edges that can be added to the second directed acyclic graph to obtain a fourth list includes: Determine target directed edges from the candidate directed edges of the second directed acyclic graph in sequence, and add the target directed edges in sequence, until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining the fourth list; Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the second directed acyclic graph, and the score value is used to represent the maximum value of the number of directed edges that can be connected from the output node to the input node in the fourth directed acyclic graph, and the fourth directed acyclic graph is obtained after adding the candidate directed edges to the second directed acyclic graph.

8. The method according to claim 7, wherein: The connectivity information of the directed acyclic graph is represented by a matrix, and the connectivity information is used to characterize the connectivity of each output node to the input node in the directed acyclic graph. The scoring value of the candidate directed edge is obtained based on the non-zero elements in the first matrix plus 1. The first matrix represents the connectivity information of the fourth directed acyclic graph.

9. The method according to claim 7, wherein: Determining a target directed edge from the candidate directed edges of the second directed acyclic graph includes: When there are at least two candidate directed edges with the largest scores among the candidate directed edges of the second directed acyclic graph, a target directed edge is randomly selected from the candidate directed edges with the largest scores.

10. A quantum circuit processing device, comprising: An acquisition module, used to acquire a first directed acyclic graph of a first quantum circuit, and acquire a search level of the first directed acyclic graph; A selection module, configured to select a target output node from the output node list of the first directed acyclic graph to obtain a first list, wherein the number of target output nodes in the first list matches the search level; A first determining module, configured to determine a first set including target feasible solutions based on the first directed acyclic graph, the first list, and the input node list of the first directed acyclic graph, wherein the target feasible solution indicates input nodes to which each target output node can be connected; A second determination module is used to determine, for each target feasible solution, target directed edges that can be added to the second directed acyclic graph in turn to obtain a fourth list; the target directed edges are directed edges from the output nodes in the second list to the input nodes in the third list, the second directed acyclic graph is obtained by adding the directed edges indicated by the target feasible solution to the first directed acyclic graph, the second list includes other output nodes in the output node list except the first list, the third list includes other input nodes in the input node list except the input nodes indicated by the target feasible solution, and the fourth list includes the target directed edges; an equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on a third directed acyclic graph, a target list, and a first instruction list of the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the target list is a list with the largest length among the fifth lists, the fifth list includes a fourth list and directed edges indicating target feasible solutions corresponding to the fourth list, the third directed acyclic graph is obtained by adding directed edges in the target list to the first directed acyclic graph, and the first instruction list includes operation instructions of the first quantum circuit.

11. The device according to claim 10, wherein: The acquisition module is specifically used for: Based on the target information, determining the search level; The target information includes at least one of the following: The number of qubits of the first quantum circuit, the search level is inversely proportional to the number of qubits of the first quantum circuit; the number of qubits of the second quantum circuit, the search level being inversely proportional to the number of qubits of the second quantum circuit; The preset compile time of the first quantum circuit, and the search level is proportional to the preset compile time.

12. The apparatus according to claim 10, further comprising: A third determination module is used to determine a compilability factor based on the number of quantum bits of the first quantum circuit and the number of quantum bits of the second quantum circuit, wherein the compilability factor indicates a compilability degree of the first quantum circuit; An adjustment module is used to adjust the search level based on the compilability factor.

13. The device according to claim 10, wherein: The number of input nodes that the target output node can connect to is less than or equal to the number of input nodes that other output nodes in the output node list can connect to.

14. The device according to claim 10, wherein: The acquisition module is specifically used for: Traversing the first instruction list according to the arrangement order of the operation instructions; Take the currently traversed operation instruction as a node, and if the sixth list is not an empty list, add the node corresponding to the operation instruction at the end of the sixth list to the directed edge corresponding to the node of the currently traversed operation instruction; the sixth list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instruction is added to the end of the sixth list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

15. The device according to claim 10, wherein: The first determining module is specifically configured to: For each target output node in the first list, obtaining a second set corresponding to the target output node, the second set including input nodes to which the target output node in the input node list can be connected; A Cartesian product is performed on the second sets corresponding to the target output nodes to obtain a first set including target feasible solutions, wherein identifiers for indicating input nodes in the target feasible solutions cannot be repeated.

16. The device according to claim 10, wherein: The second determining module is specifically used to: Determine target directed edges from the candidate directed edges of the second directed acyclic graph in sequence, and add the target directed edges in sequence, until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining the fourth list; Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the second directed acyclic graph, and the score value is used to represent the maximum value of the number of directed edges that can be connected from the output node to the input node in the fourth directed acyclic graph, and the fourth directed acyclic graph is obtained after adding the candidate directed edges to the second directed acyclic graph.

17. The device according to claim 16, wherein: The connectivity information of the directed acyclic graph is represented by a matrix, and the connectivity information is used to characterize the connectivity of each output node to the input node in the directed acyclic graph. The scoring value of the candidate directed edge is obtained based on the non-zero elements in the first matrix plus 1. The first matrix represents the connectivity information of the fourth directed acyclic graph.

18. The device according to claim 16, wherein: The second determining module is further used for: When there are at least two candidate directed edges with the largest scores among the candidate directed edges of the second directed acyclic graph, a target directed edge is randomly selected from the candidate directed edges with the largest scores.

19. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

20. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

21. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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