A PCIe device link training test method, device, equipment and medium

Abstract

The present invention discloses a test method, device, equipment and medium for link training of PCIe devices. The method comprises: obtaining a configuration file, wherein the configuration file comprises a test time, a type of device to be tested and the number of devices to be tested, and the test device comprises a PCIe device; obtaining the address of the device to be tested according to the number of devices to be tested and the type of device to be tested, and obtaining the slot of the device to be tested according to the address of the device to be tested; modifying the power supply state of the slot of the device to be tested to cyclically perform link training of the PCIe device, and generating a test report according to the link information of the PCIe device. The embodiment of the present invention can realize the automated test of link training of PCIe devices, saving the manpower and material resources required for testing; at the same time, it can control the training of a single / multiple PCIe devices at the same time, saving the test cost, and improving the test efficiency and accuracy. Furthermore, the technical solution of the present invention can automatically generate a test report at the end of the training, so that the staff can understand the test process conveniently.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a test method, device, equipment and medium for PCIe device link training. Background Art

[0002] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging and service quality and other functions. With the rapid development of PCIe technology applications, various specifications of PCIe terminal devices have emerged, which makes the stability requirements of PCIe links higher and higher. Since the server needs to provide high-speed CPU computing power, long-term reliable operation, strong I / O external data throughput and better scalability, it is necessary to conduct necessary tests on the link stability of PCIe devices with OCP 3.0 (Open Compute Project) protocol connected to the server.

[0003] The link stability test of PCIe devices can generally be performed in two ways. The first is the violent hot-plug method, which is: the staff directly hot-plugs the PCIe device on the server, that is, unplugs the device from the server, and then plugs the device into the original position, and powers on or off the device during continuous plugging and unplugging, thereby completing the PCIe link training process; the second method is to power off and on the server where the PCIe device is located, thereby completing the PCIe link training process. At the same time, after the training process is completed, the training process is manually recorded and summarized.

[0004] Both of these testing methods require manual power-on and power-off operations on the device or server, which consumes a lot of time and is not conducive to improving efficiency. At the same time, due to the uncertainty of manual operation, these two testing methods will have large testing errors, resulting in low accuracy of the final test results. Furthermore, manually recording the training process will also consume a lot of manpower and material resources. Summary of the invention

[0005] The present invention provides a test method, device, equipment and medium for link training of PCIe devices, which can automatically test the link training of one or more OCP3.0 PCIe devices, thereby improving the test speed and accuracy. At the same time, the method can automatically generate a test report according to the training process of the PCIe device, thereby saving manpower and material resources.

[0006] In a first aspect, an embodiment of the present invention provides a method for testing link training of a PCIe device, comprising:

[0007] Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, wherein the device to be tested includes a PCIe device;

[0008] Obtain the address of the device to be tested according to the number and type of the device to be tested, and obtain the slot of the device to be tested according to the address of the device to be tested;

[0009] The power supply status of the slot of the device to be tested is modified to cyclically execute the link training of the PCIe device, and a test report is generated according to the link information of the PCIe device.

[0010] Optionally, acquiring the address of the device to be tested according to the number of devices to be tested and the type of devices to be tested includes:

[0011] Start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested;

[0012] The thread performs PCIe device addressing according to the type of the device to be tested to obtain the address of the device to be tested.

[0013] Through the above solution, multiple threads can be started simultaneously to perform PCIe device addressing in parallel, and the address of the device to be tested can be obtained, thereby improving the addressing efficiency.

[0014] Optionally, before obtaining the slot of the device to be tested according to the address of the device to be tested, the method further includes:

[0015] Acquire the initial link information of the PCIe device according to the address of the device to be tested;

[0016] Comparing the initial link information with the system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test criteria according to the comparison result;

[0017] If yes, the power supply state of the slot of the device to be tested is modified to cyclically execute the PCIe device link training step.

[0018] Through the above scheme, when the initial link information meets the system performance evaluation test standard, the PCIe device link training test is performed to avoid the waste of computing resources caused by the link training test in the case of link errors.

[0019] Optionally, the modifying the power supply state of the slot of the device to be tested to cyclically perform PCIe device link training includes:

[0020] By rewriting the power state of the slot of the device to be tested, the link of the PCIe device is cyclically executed to power off and then power on;

[0021] Each time the link of the PCIe device is powered off and on, a PCIe device link training is performed through the link training state machine.

[0022] Through the above scheme, the link of the PCIe device is cycled to be powered off and then powered on to trigger link training, thereby automatically triggering the link training of the PCIe device, and providing a convenient and efficient way to trigger the link training of the PCIe device.

[0023] Optionally, generating a test report according to link information of a PCIe device includes:

[0024] When the test time is met, the power supply status of the slot of the device to be tested is stopped from being modified, and a test report is generated according to the link information corresponding to each PCIe device link training.

[0025] Through the above solution, the link training test is stopped by stopping the modification of the power supply state of the slot of the device to be tested, so as to achieve convenient and efficient termination of the link training of the PCIe device.

[0026] Optionally, generating a test report according to link information of a PCIe device includes:

[0027] When the link of the PCIe device is powered off, if link information of the PCIe device is obtained, determining that the test fails;

[0028] Determine whether to end the test based on the current number of test failures;

[0029] If yes, a test report is generated according to the link information corresponding to each PCIe device link training.

[0030] Through the above solution, the link training test is stopped according to the number of test failures, so as to achieve convenient and efficient termination of the link training of the PCIe device.

[0031] Optionally, generating a test report according to link information corresponding to each PCIe device link training includes:

[0032] For each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, determining that the link training result is a training failure;

[0033] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information does not meet the system performance evaluation test standard, determining that the link training result is a training failure;

[0034] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information meets the system performance evaluation test standard, then the link training result is determined to be training success;

[0035] A test report is generated according to the link training result.

[0036] Through the above solution, it is possible to automatically generate a test report based on the link training results of each link training, thereby improving the efficiency and accuracy of test report generation.

[0037] In a second aspect, an embodiment of the present invention provides a test device for PCIe device link training, comprising:

[0038] A configuration file acquisition module, used to acquire a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the test device to be tested includes a PCIe device;

[0039] A device address acquisition module, which acquires the address of the device to be tested according to the number of devices to be tested and the type of the devices to be tested, and acquires the slot of the device to be tested according to the address of the device to be tested;

[0040] The device link training module is used to modify the power supply state of the slot of the device to be tested to cyclically perform PCIe device link training and generate a test report according to the link information of the PCIe device.

[0041] Optionally, the device address acquisition module is specifically used for:

[0042] Start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested;

[0043] The thread performs PCIe device addressing according to the type of the device to be tested to obtain the address of the device to be tested.

[0044] Optionally, the device further includes a link information comparison module, configured to:

[0045] Before obtaining the slot of the device to be tested according to the address of the device to be tested, obtaining initial link information of the PCIe device according to the address of the device to be tested;

[0046] Comparing the initial link information with the system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test criteria according to the comparison result;

[0047] If yes, the power supply state of the slot of the device to be tested is modified to cyclically execute the PCIe device link training step.

[0048] Optionally, the device link training module is specifically used to:

[0049] By rewriting the power state of the slot of the device to be tested, the link of the PCIe device is cyclically executed to power off and then power on;

[0050] Each time the link of the PCIe device is powered off and on, a PCIe device link training is performed through the link training state machine.

[0051] Optionally, the device link training module is specifically used to:

[0052] When the test time is met, the power supply status of the slot of the device to be tested is stopped from being modified, and a test report is generated according to the link information corresponding to each PCIe device link training.

[0053] Optionally, the device link training module is further specifically used for:

[0054] When the link of the PCIe device is powered off, if link information of the PCIe device is obtained, determining that the test fails;

[0055] Determine whether to end the test based on the current number of test failures;

[0056] If yes, a test report is generated according to the link information corresponding to each PCIe device link training.

[0057] Optionally, the device link training module is further specifically used for:

[0058] For each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, determining that the link training result is a training failure;

[0059] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information does not meet the system performance evaluation test standard, determining that the link training result is a training failure;

[0060] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information meets the system performance evaluation test standard, then the link training result is determined to be training success;

[0061] A test report is generated according to the link training result.

[0062] In a third aspect, an embodiment of the present invention provides an electronic device, including:

[0063] at least one processor; and

[0064] a memory communicatively connected to at least one processor; wherein,

[0065] The memory stores a computer program that can be executed by at least one processor, and the computer program is executed by at least one processor so that the at least one processor can execute any one of the PCIe device link training test methods in any embodiment of the present invention.

[0066] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, including:

[0067] The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement any one of the PCIe device link training test methods in the embodiments of the present invention when executed.

[0068] The embodiment of the present invention provides a test method, device, equipment and medium for PCIe device link training. By obtaining the configuration file of the device to be tested, the address and link information of the device to be tested are obtained, and the specific slot of the device to be tested on the mainboard is determined, and then the PCIe device training process is automatically tested. After the training is completed, a test report is automatically generated. This test method helps to improve the accuracy of PCIe device link training test and improve the efficiency of the test. Furthermore, after the training is completed, a test report is automatically generated, which reduces the consumption of manpower and material resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0070] Figure 1 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0071] Figure 2 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0072] Figure 3 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0073] Figure 4A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0074] Figure 5 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0075] Figure 6 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

[0076] Figure 7 A schematic diagram of the structure of a test device for PCIe device link training provided by an embodiment of the present invention;

[0077] Figure 8 A schematic diagram of the structure of an electronic device that can be used to implement an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0078] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0079] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0080] Figure 1The present invention provides a flowchart of a test method for link training of a PCIe device. The method of the present invention can be applied to realize the automated test of link training of PCIe devices, and help staff improve the accuracy and efficiency of the test of link training of PCIe devices. The method can be executed by a test device for link training of PCIe devices, which can be implemented in the form of hardware and / or software. The test device for link training of PCIe devices can be configured in various servers, communication and data transmission equipment, and the present embodiment does not limit this.

[0081] like Figure 1 As shown, the method includes:

[0082] Step 110: Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the devices to be tested include PCIe devices.

[0083] The configuration file is a necessary file required before the PCIe device is tested, which includes necessary information required for the test, such as the test time, the type of device to be tested, and the number of devices to be tested.

[0084] Specifically, the test time can be the total duration of a single / multiple tests, and multiple specific tests can be included within the test time; the type of device to be tested can be understood as a PCIe device that can be installed on the server through the server motherboard slot, which can be a network card device, or other input and output devices, etc.; the number of devices to be tested can be understood as the total number of devices participating in the test at the same time. If multiple types of devices to be tested are tested at the same time, the number of devices to be tested is the sum of the number of devices to be tested.

[0085] Optionally, a specific function may be called to allow multiple devices to be tested to be tested simultaneously without affecting each other.

[0086] Step 120: Obtain addresses of the devices to be tested according to the number of devices to be tested and the types of the devices to be tested, and obtain slots of the devices to be tested according to the addresses of the devices to be tested.

[0087] The device address to be tested can be understood as the unique characteristic information of each PCIe device to be tested, and the device address to be tested can be obtained through a hardware query instruction. The slot of the device to be tested is the specific position of the slot corresponding to the device to be tested on the server motherboard.

[0088] Specifically, the number of devices to be tested and the types of devices to be tested can be obtained through the configuration file, and then the corresponding device addresses to be tested can be obtained according to the device types of each device to be tested according to the protocol standard corresponding to the type, and the specific slots of the devices to be tested on the mainboard can be finally obtained by using the setting instructions based on the addresses of the devices to be tested. If it is determined that there are multiple devices to be tested according to the number of devices to be tested, the device addresses to be tested corresponding to each device to be tested are obtained in parallel by referencing a specific function, and then the operation of determining the slots of the devices to be tested according to the addresses of the devices to be tested is executed in parallel.

[0089] Step 130: modify the power supply status of the slot of the device to be tested to cyclically execute PCIe device link training, and generate a test report according to the link information of the PCIe device.

[0090] Among them, the power supply status can be understood as the power-on status of the slot of the device to be tested, such as power on or power off. Since the link training is automatically completed by the link training state machine, in the process of each link training execution, the functions such as bit locking, character locking, block locking, link width determination, channel position flipping, signal polarity flipping, link data rate and channel alignment are completed. The link information can characterize the relevant information of the PCIe device link, and the stability of the PCIe device link can be characterized by the link information. Furthermore, the training process and results of the PCIe device can be obtained by parsing the link information.

[0091] Optionally, PCIe device link training is a link training method that initializes the physical layer of the PCIe link, port configuration information, the sending and receiving modules, and the status of related links, and understands the topology of the other end of the link to achieve functions such as bit locking, character locking, block locking, determining link width, channel position flipping, signal polarity flipping, determining the link data rate and channel alignment, and ultimately allowing the devices at both ends of the PCIe link to communicate data. The test report is a report document generated at the end of the test, which records the process information of each training in each test.

[0092] In the embodiment of the present invention, the test may be terminated when the test time is reached, or the test may be terminated when the number of test failures meets the test termination condition, etc. The present invention does not specifically limit the test termination condition.

[0093] Specifically, by automatically modifying the power supply status of the slot of the device to be tested, the PCIe device link training can be cyclically executed through the link training state machine, and the training process and information of each training will be written into the test report. When the test time is over, the test report will be sent to the staff.

[0094] The technical solution of this embodiment, by obtaining the configuration file of the device to be tested, realizes the automated testing of a single device through the test tool, and can also realize the automated testing of multiple devices at the same time; and determines the link information through the address of the device to be tested and automatically loops the test, which helps to improve the test accuracy and test speed and save test time; finally, when the test is completed, a test report is generated, so that the staff can accurately obtain the details and test results of each test process, standardize the test process, and simplify the acquisition of the test process and results.

[0095] Figure 2 A flowchart of a test method for PCIe device link training provided in an embodiment of the present invention. Based on the above embodiments, this embodiment further defines a method for obtaining the address of the device to be tested and a specific method for obtaining the slot of the device to be tested, and can be combined with the above embodiments.

[0096] like Figure 2 As shown, including:

[0097] Step 210: Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the devices to be tested include PCIe devices.

[0098] Step 220: Start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested.

[0099] Among them, the thread is the smallest unit for calculation scheduling. It can be understood that when multiple devices are tested at the same time, different devices to be tested are tested through different threads. Therefore, it is necessary to allocate a separate thread to each device to execute the test so that the link training test can be performed without affecting each other.

[0100] Optionally, when different devices to be tested are inserted into the server mainboard, corresponding required threads are started according to the number of devices to be tested, and link training tests of various devices to be tested are performed in parallel through the threads to meet the test requirements.

[0101] Step 230: Perform PCIe device addressing according to the type of the device to be tested through the thread to obtain the address of the device to be tested.

[0102] It is understandable that different types of devices under test have different addressing methods due to their different protocol contents. Therefore, it is necessary to perform PCIe device addressing through threads according to the corresponding protocol according to the specific type of the device under test to obtain the address of the device under test.

[0103] Step 240: Obtain initial link information of the PCIe device according to the address of the device to be tested.

[0104] Specifically, after determining the address of the device to be tested and its corresponding protocol, the test tool will perform corresponding PCIe addressing according to the type of the device to be tested to obtain the PCIe address. Further, the obtained address characters can be processed using a specific instruction function to intercept key information in the address as the required link information. The initial link information is determined based on the intercepted link information and the PCIe device address.

[0105] Step 250 , compare the initial link information with the system performance evaluation test parameters, and determine whether the link information meets the system performance evaluation test standards based on the comparison result. If so, execute step 260 ; otherwise, execute step 270 .

[0106] The system performance evaluation test parameters are standard parameters for evaluating the performance of the server system. For example, the system performance evaluation test parameters include standard parameters corresponding to the PCIe link information.

[0107] Specifically, before the device to be tested is tested, the initial link information will be compared with the system performance evaluation test parameters. When the initial link information meets the system performance evaluation test parameters, it means that the initial link information meets the test requirements, and the device to be tested can be tested, otherwise it cannot be tested.

[0108] Step 260: modify the power supply status of the slot of the device to be tested to cyclically execute the PCIe device link training, and generate a test report according to the link information of the PCIe device.

[0109] The cyclic execution can be understood as repeatedly modifying the power supply status of the device to be tested, which may include cyclically powering off and then powering on the slot of the device to be tested. The link training state machine is triggered to automatically perform link training by powering on the endpoint of the slot of the device to be tested.

[0110] Specifically, when the link information meets the system performance evaluation test parameters, the link training state machine will cyclically change the power supply status of the slot of the device to be tested, thereby controlling the power supply status of the device to be tested, cyclically triggering the link training state machine to automatically perform link training, and obtain PCIe link information during each link training process.

[0111] Optionally, the training will end when the training reaches a preset test time.

[0112] Step 270, end.

[0113] The embodiment of the present invention obtains a configuration file, starts a corresponding number of threads according to the number of devices to be tested, allocates the threads to each device to be tested, and then performs PCIe device addressing according to the type of the device to be tested to obtain the address of the device to be tested. This addressing method helps to quickly and accurately determine the specific position of the device to be tested on the server motherboard, thereby improving the addressing efficiency; further, the link information of the PCIe device is obtained through the address of the device to be tested, and the initial link information is compared with the system performance evaluation test parameters. If the initial link information meets the system performance evaluation test parameters, multiple automated tests can be started, and the link training state machine will cyclically execute the PCIe device link training steps. This automated PCIe device link training test method helps to save manpower and material resources required for the test, improve the test accuracy, and improve the test efficiency. Finally, at the end of the test, a test report is automatically generated according to the link information of the PCIe device during each test. This automated generation method helps to standardize the test process and improve the efficiency of test personnel in obtaining test results.

[0114] Figure 3 A flowchart of a PCIe device link training test method provided by an embodiment of the present invention. Based on the above embodiments, this embodiment further defines a PCIe device link training method and can be combined with the above embodiments.

[0115] like Figure 3 As shown, the method includes:

[0116] Step 310: Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the devices to be tested include PCIe devices.

[0117] Step 320: Start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested.

[0118] Step 330: Perform PCIe device addressing according to the type of the device to be tested through the thread to obtain the address of the device to be tested.

[0119] Step 340: Obtain initial link information of the PCIe device according to the address of the device to be tested.

[0120] Before modifying the power supply status of the slot of the device to be tested, the setting information in the address of the device to be tested is obtained, and the obtained setting information and the address of the device to be tested are used as initial link information.

[0121] Step 350 , compare the initial link information with the system performance evaluation test parameters, and determine whether the link information meets the system performance evaluation test standards based on the comparison result. If so, execute step 360 , otherwise execute step 390 .

[0122] Step 360: Rewrite the power state of the slot of the device to be tested so that the link of the PCIe device executes the power-off and power-on steps in a cyclic manner.

[0123] Among them, each slot of the device to be tested has its own independent power state. The power state of each slot of the device to be tested can be powered on or off by rewriting operation, and then the link of the PCIe device can be cyclically powered off and then powered on by cyclic rewriting operation.

[0124] Step 370: Each time the link of the PCIe device is powered off and on, a link training of the PCIe device is performed through the link training state machine.

[0125] Exemplarily, each time the link of a PCIe device is powered off and on, the link training state machine will automatically execute the device link training steps to complete a PCIe device link training. Then, the link training state machine will repeatedly power off and on the PCIe device link to complete each PCIe device link training in a cycle, thereby realizing automated training.

[0126] Step 380: When the test time is met, stop modifying the power supply status of the slot of the device to be tested, and generate a test report according to the link information corresponding to each PCIe device link training.

[0127] Among them, meeting the test time can be understood as not exceeding the set test time within the prescribed test time range.

[0128] Specifically, when the test time is met, the power supply status of the slot of the device to be tested will be stopped from being modified, and during the stop time, a test report will be generated according to the link information corresponding to the PCIe device link training, and the test report will include all the details of this training.

[0129] Optionally, for each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, the link training result is determined to be a training failure; if the link information of the PCIe device is obtained when the link of the PCIe device is powered on and the link information does not meet the system performance evaluation test standard, the link training result is determined to be a training failure; if the link information of the PCIe device is obtained when the link of the PCIe device is powered on and the link information meets the system performance evaluation test standard, the link training result is determined to be a training success; and a test report is generated according to the link training result.

[0130] Exemplarily, when the test time is met, the test tool will generate a test report based on the link information corresponding to each PCIe device link training. After the test report is generated, the PCIe device will be automatically trained by changing the power supply status in an automated cycle, and a corresponding test report will be automatically generated for each training. After the test time is reached, all training will be terminated, and all training processes and result details within the test time will be organized into a test report and sent to the tester.

[0131] Step 390, end.

[0132] The embodiment of the present invention obtains a configuration file, obtains the address of the device to be tested according to the configuration file, and then obtains the slot of the device to be tested according to the address of the device to be tested. In this way, the specific location of the device to be tested on the server can be quickly determined; the power state of the slot of the device to be tested is rewritten by the link training state machine, the link of the PCIe device is controlled to cycle through the steps of powering off and then powering on, and the training steps are cycled through the device to be tested, thereby realizing a fast and efficient training process and saving manpower and material resources. Specifically, when the test time is met, the power supply state of the slot of the device to be tested is stopped from being modified, and a test report is automatically generated according to the link information corresponding to each PCIe device link training, which can improve the test efficiency, standardize the test work, and help testers reduce the reading burden.

[0133] Figure 4 A flowchart of a test method for link training of a PCIe device is provided in an embodiment of the present invention. Based on the above embodiments, this embodiment further defines a specific method for generating a test report according to the link information of the PCIe device, and can be combined with the above embodiments.

[0134] like Figure 4 As shown, including:

[0135] Step 410: Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the devices to be tested include PCIe devices.

[0136] Step 420: Obtain addresses of the devices to be tested according to the number of devices to be tested and the types of the devices to be tested, and obtain slots of the devices to be tested according to the addresses of the devices to be tested.

[0137] Step 430: rewrite the power state of the slot of the device to be tested so that the link of the PCIe device executes the steps of powering off and then powering on in a cyclic manner.

[0138] Step 440: Perform a PCIe device link training through a link training state machine each time the link of the PCIe device is powered off and powered on.

[0139] Step 450: When the link of the PCIe device is powered off, if the link information of the PCIe device is obtained, it is determined that the test has failed.

[0140] Specifically, when the link of the PCIe device is powered off, the PCIe device will be disconnected from the server. If the link information of the PCIe device is obtained, it proves that a link failure may occur, and it is determined that this test fails.

[0141] Step 460 , determine whether to end the test based on the current number of test failures, if so, execute step 470 , otherwise execute step 430 .

[0142] The number of test failures is the total number of test failures within the test time.

[0143] Specifically, whether to end the test can be determined by judging the preset test failure threshold. The test failure threshold can be understood as follows: if the number of test failures is greater than the test failure threshold within the predicted time, the test will be ended. That is, the test tool has a certain fault tolerance rate and will not directly end all tests due to the failure of a single test.

[0144] Step 470: Generate a test report based on the link information corresponding to each PCIe device link training.

[0145] Specifically, when the number of test failures exceeds the test failure threshold, the test will be terminated, and a test report will be generated based on the link information corresponding to each PCIe device link training and sent to the staff.

[0146] In an embodiment of the present invention, when the link of the PCIe device is powered off, if the link information of the PCIe device is obtained, it is determined that the test has failed, and the test will be terminated when the number of test failures is greater than the test failure threshold. This method of terminating the test is convenient for terminating the test in time when the test fails multiple times, thereby realizing convenient and efficient termination of the link training of the PCIe device.

[0147] Figure 5An embodiment of the present invention provides a flow chart of a test method for PCIe device link training. The method can be combined with the above embodiments and implemented as a separate technical solution.

[0148] like Figure 5 As shown, including:

[0149] Step 510: Install the required testing software and hardware on the server.

[0150] The hardware required for the test includes the required equipment to be tested, various hardware required to complete the test, etc. The equipment to be tested includes a PCIe device.

[0151] For example, before the tester conducts the PCIe device test, the test environment needs to be configured on the server and the necessary software applications, such as the corresponding Python version, need to be installed. At the same time, the OCP3.0-compliant PCIe device required for the test needs to be installed outside the server. By installing the necessary software inside the server and the necessary external hardware, the software and hardware requirements for the test have been met.

[0152] Step 520: Set specific parameters of the configuration file.

[0153] Optionally, due to the different number of devices to be tested, types of devices to be tested, and test time, it is necessary to determine specific parameters in the configuration file before testing.

[0154] Optionally, the test tool will provide a configuration file before the test. The tester needs to configure the test parameters in the configuration file. By setting the test parameters, specific information such as the test time, the type of device to be tested, and the number of devices to be tested will be determined.

[0155] Step 530: The server runs the link training state machine.

[0156] Optionally, the PCIe link training is in the physical layer of the PCIe link. By initializing the physical layer of the PCIe link, port configuration information, sending and receiving modules, and related link states, the devices at both ends of the PCIe link can finally communicate data. The entire process can be automatically completed by the test tool. Specifically, before the PCIe link can communicate normally, the PCIE device will be trained through the link training state machine to achieve functions such as bit locking, character locking, block locking, determining link width, channel position flipping, signal polarity flipping, determining link data rate, and channel alignment.

[0157] Step 540: After the test is completed, a test report is generated and sent to the staff.

[0158] The embodiment of the present invention can set the number and type of devices to be tested by installing the software and hardware required for the test and setting the configuration file parameters. By parsing the configuration file, the PCIe address of the device to be tested can be quickly determined. Then, the test tool is run, and the device to be tested can be subjected to automated test training through the test tool by cyclically powering on and off the device slot, thereby saving manpower and material resources required for the test and improving the test accuracy and efficiency. When the test time is reached, the test ends, and a test report is generated and sent to the staff, which helps the staff to quickly understand the test results, standardizes the test process, and saves the time of the tester in obtaining the test process.

[0159] Figure 6 A flowchart of a test method for PCIe device link training provided by an embodiment of the present invention, the method specifically defines a method based on the number of devices to be tested and a method for PCIe device link training, and can be combined with the above embodiments.

[0160] like Figure 6 As shown, including:

[0161] Step 601: Obtain a configuration file.

[0162] Optionally, the configuration file includes test time, type of device to be tested and number of devices to be tested, and the devices to be tested include PCIe devices.

[0163] Step 602 : Determine whether multiple devices to be tested are to be tested simultaneously according to the configuration file. If so, execute step 603 ; otherwise, execute step 604 .

[0164] If multiple devices to be tested are tested simultaneously, step 603 is executed to test the multiple devices to be tested simultaneously; otherwise, step 604 is executed to test a single device to be tested separately.

[0165] Step 603 , obtain the PCIe address of each device in the multiple devices to be tested, and execute step 605 .

[0166] Step 604 , obtain the PCIe address of a single device to be tested, and execute step 606 .

[0167] Specifically, the PCIe device address can be addressed through specific instructions in the test tool script. For example, the relevant information of the PCIe address can be obtained through the operation instruction lspci|grep-i xxx. Further, according to the PCIe address and lspci-s PCIe Addr-vvvvv|grep-i slot, the specific slot position of the PCIe device on the server can be obtained.

[0168] Step 605 , determining whether the initial link information of the multiple devices to be tested conforms to the system performance evaluation test parameters, if so, executing step 607 , otherwise, executing step 611 .

[0169] Step 606 , determine whether the link information of the single device to be tested meets the system performance evaluation test parameters, if so, execute step 607 , otherwise, execute step 611 .

[0170] Specifically, the initial link information is compared with the system performance evaluation test parameters. If the system performance evaluation test parameter conditions are met, it indicates that the initial link information meets the test requirements and can be tested.

[0171] Step 607: The test tool sets the power state of the slot of the device to be tested corresponding to the PCIe address of the device to be tested.

[0172] For example, the power status of the slot of the device to be tested can be checked through the corresponding command of the test tool, such as through the command cat / sys / bus / pci / slots / <The physical slot of xxxx Device> / power View the power status of the PCIe device slot.

[0173] Step 608: Perform PCIe device link training through the link training state machine.

[0174] Specifically, the power state of the corresponding slot of the device to be tested can be changed through the link training state machine. For example, the power-on state and power-off state of the slot can be corresponded to "1" and "0" respectively. When the power state of the slot is equal to "0", it indicates that it is in the power-off state. If the PCIe device link information can be obtained in the server operating system at this time, it indicates that the link may be faulty and the test fails. When the power state of the slot is equal to "1", it indicates that it is in the power-on state. If the PCIe device link information cannot be obtained in the server operating system at this time, it indicates that the link may be faulty and the training fails.

[0175] Step 609 , determine whether the test time has been exceeded, if so, execute step 610 , otherwise return to execute step 607 .

[0176] If the test time has not been exceeded, the process returns to step 607 , and the test tool sets the power state of the slot of the device to be tested corresponding to the PCIe address of the device to be tested; if the test time has been exceeded, the process executes step 610 .

[0177] Step 610: Generate a test report and send it to the staff.

[0178] When the training time exceeds the test time parameter set in the configuration file, it indicates that the test time has reached the preset upper limit. At this time, the test will be terminated, the power supply status of the slot of the device to be tested will stop being changed, and all test results will be integrated into a test report, which will be sent to the tester's email.

[0179] Step 611, end.

[0180] The embodiment of the present invention obtains a configuration file, obtains the number of devices to be tested according to the configuration file, and then obtains the device address through the addressing method, and finally obtains the slot of the device to be tested on the mainboard. In this way, the specific location of the device to be tested on the server can be quickly determined; at the same time, after obtaining the PCIe address of the device, it will be determined whether the link information of the multiple devices to be tested meets the system performance evaluation test parameters. If it meets the test parameters, the test tool will be started to start the test. Specifically, the test tool rewrites the power status of the slot of the device to be tested, controls the link of the PCIe device to cycle the power-off and then power-on steps, and cycles the training steps through the device to be tested, thereby realizing a fast and efficient automated training process and saving manpower and material resources. Among them, when the test time is met, the power supply status of the slot of the device to be tested is stopped from being modified, and a test report is automatically generated according to the link information corresponding to each PCIe device link training, which can standardize the test work and help testers reduce the reading burden.

[0181] Figure 7 A structural schematic diagram of a PCIe device link training test device provided in an embodiment of the present invention can be used to execute a PCIe device link training test method described in the above embodiments. The device specifically includes: a configuration file acquisition module 710, a device address acquisition module 720, and a device link training module 730.

[0182] The configuration file acquisition module 710 is used to: acquire a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the devices to be tested include PCIe devices.

[0183] Optionally, the file acquisition module 710 includes a reading and writing unit for setting parameters in a configuration file.

[0184] The device address acquisition module 720 is used to: acquire the address of the device to be tested according to the number of devices to be tested and the type of devices to be tested, and acquire the slot of the device to be tested according to the address of the device to be tested.

[0185] Optionally, the device address acquisition module 720 includes: a thread allocation unit and a PCIe device addressing unit.

[0186] The thread allocation unit is used to start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested.

[0187] The PCIe device addressing unit is used to: perform PCIe device addressing according to the type of the device to be tested through a thread to obtain the address of the device to be tested.

[0188] Furthermore, the device address acquisition module 720 may also include: a link information acquisition unit, a standard comparison unit, and a training execution unit.

[0189] The link information acquisition unit is used to acquire the initial link information of the PCIe device according to the address of the device to be tested.

[0190] The standard comparison unit is used to compare the initial link information with the system performance evaluation test parameters, and determine whether the link information meets the system performance evaluation test standards based on the comparison results.

[0191] The training execution unit is used for: if the comparison result determines that the link information meets the system performance evaluation test standard, then modifying the power supply state of the slot of the device to be tested to cyclically execute the PCIe device link training steps.

[0192] The device link training module 730 is used to modify the power supply status of the slot of the device to be tested to cyclically perform PCIe device link training, and generate a test report according to the link information of the PCIe device.

[0193] Optionally, the device link training module 730 includes: a cyclic training unit and a test report generating unit.

[0194] The cyclic training unit is used to modify the power supply status of the slot of the device to be tested to cyclically perform PCIe device link training.

[0195] The cyclic training unit may include: a power state control subunit and a training execution subunit.

[0196] The power state control subunit is used to rewrite the power state of the slot of the device to be tested so that the link of the PCIe device cyclically executes the steps of powering off and then powering on.

[0197] The training execution subunit is used to perform a PCIe device link training through a link training state machine each time the link of the PCIe device is powered off and powered on.

[0198] The test report generating unit is used to: when the test time is met, stop modifying the power supply state of the slot of the device to be tested, and generate a test report according to the link information corresponding to each PCIe device link training.

[0199] Optionally, the test report generating unit includes: a test failure determining subunit, a judging subunit, and a test failure test reporting subunit.

[0200] The test failure determination subunit is used to determine that the test has failed if link information of the PCIe device is obtained when the link of the PCIe device is powered off.

[0201] The judging subunit is used to judge whether to end the test according to the current number of test failures.

[0202] The test failure test report subunit is used to: if the current number of test failures is greater than a preset test failure threshold, generate a test report based on the link information corresponding to each PCIe device link training.

[0203] Furthermore, the test report generating unit also includes a training failure judging unit.

[0204] The training failure judgment unit is used to judge whether the training has failed and generate a corresponding test report.

[0205] For each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, it is determined that the link training result is a training failure;

[0206] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information does not meet the system performance evaluation test standard, the link training result is determined to be a training failure;

[0207] If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information meets the system performance evaluation test standard, the link training result is determined to be training success;

[0208] Generate a test report based on the link training results.

[0209] The device to be tested for PCIe device link training provided in the embodiment of the present invention can execute any one of the test methods for PCIe device link training in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0210] Figure 8A schematic diagram of an electronic device 800 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0211] like Figure 8 As shown, the electronic device 800 includes at least one processor 801, and a memory connected to the at least one processor 801, such as a read-only memory (ROM) 802, a random access memory (RAM) 803, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 801 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 802 or the computer program loaded from the storage unit 808 to the random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0212] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0213] The processor 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 801 executes the various methods and processes described above, such as a test method for PCIe device link training.

[0214] In some embodiments, a test method for PCIe device link training may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the processor 801, one or more steps of the test method for PCIe device link training described above may be performed. Alternatively, in other embodiments, the processor 801 may be configured to perform a test method for PCIe device link training in any other appropriate manner (e.g., by means of firmware).

[0215] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0216] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0217] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0218] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0219] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0220] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0221] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0222] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A test method for PCIe device link training, characterized in that: include: Obtain a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the device to be tested includes a PCIe device; Acquire the address of the device to be tested according to the number of devices to be tested and the type of the devices to be tested, and acquire the slot of the device to be tested according to the address of the device to be tested; By rewriting the power state of the slot of the device to be tested, the link of the PCIe device is cyclically executed to power off and then power on; Each time the link of the PCIe device is powered off and powered on, performing a PCIe device link training through a link training state machine; Generate a test report based on the link information of the PCIe device; The test report is generated based on the link information of the PCIe device, including: If the test time does not exceed the set test time within the specified test time range, stop modifying the power supply state of the slot of the device to be tested; For each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, determining that the link training result is a training failure; If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information does not meet the system performance evaluation test standard, determining that the link training result is a training failure; If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information meets the system performance evaluation test standard, then the link training result is determined to be training success; A test report is generated according to the link training result.

2. The method according to claim 1, characterized in that The step of obtaining the address of the device to be tested according to the number of devices to be tested and the type of devices to be tested includes: Start a corresponding number of threads according to the number of devices to be tested, and allocate the threads to each device to be tested; The thread performs PCIe device addressing according to the type of the device to be tested to obtain the address of the device to be tested.

3. The method according to claim 1, characterized in that: Before obtaining the slot of the device to be tested according to the address of the device to be tested, the method further includes: Acquire the initial link information of the PCIe device according to the address of the device to be tested; Comparing the initial link information with the system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test criteria according to the comparison result; If yes, the power supply state of the slot of the device to be tested is modified to cyclically execute the PCIe device link training step.

4. The method according to claim 1, characterized in that Generating a test report according to link information of a PCIe device includes: When the link of the PCIe device is powered off, if link information of the PCIe device is obtained, determining that the test fails; Determine whether to end the test based on the current number of test failures; If yes, a test report is generated according to the link information corresponding to each PCIe device link training.

5. A test device for PCIe device link training, characterized in that: include: A configuration file acquisition module, used to acquire a configuration file, wherein the configuration file includes a test time, a type of device to be tested, and a number of devices to be tested, and the test device to be tested includes a PCIe device; A device address acquisition module, which acquires the address of the device to be tested according to the number of devices to be tested and the type of the devices to be tested, and acquires the slot of the device to be tested according to the address of the device to be tested; A device link training module, used to rewrite the power state of the slot of the device to be tested so that the link of the PCIe device cyclically executes the steps of powering off and then powering on, and each time the link of the PCIe device is powered off and powered on, a PCIe device link training is performed once through a link training state machine, and a test report is generated according to the link information of the PCIe device; The test report is generated based on the link information of the PCIe device, including: If the test time does not exceed the set test time within the specified test time range, stop modifying the power supply state of the slot of the device to be tested; For each PCIe device link training, if the link information of the PCIe device is not obtained when the link of the PCIe device is powered on, determining that the link training result is a training failure; If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information does not meet the system performance evaluation test standard, determining that the link training result is a training failure; If, when the link of the PCIe device is powered on, the link information of the PCIe device is obtained and the link information meets the system performance evaluation test standard, then the link training result is determined to be training success; A test report is generated according to the link training result.

6. An electronic device, characterized in that: Electronic equipment includes: at least one processor; and a memory communicatively connected to at least one processor; wherein, The memory stores a computer program executable by at least one processor, and the computer program is executed by at least one processor so that the at least one processor can execute the test method for link training of a PCIe device according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test method for PCIe device link training described in any one of claims 1-4 when executed.

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