Wafer defect detection method, system, device and readable medium

Abstract

The present application provides a wafer defect detection method, system, device and medium. The method includes: when considering the defect radius, constructing an R-Tree to store the relationship between the current wafer layer and the previous wafer layer, traversing the current wafer layer, finding added defects and common defects; traversing the previous wafer layer, finding missing defects, and determining the defect type; when not considering the defect radius, constructing a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer, traversing the current wafer layer, finding added defects and common defects; traversing the previous wafer layer, finding missing defects, and determining the defect type. By establishing an effective mapping and matching between the KD-Tree and the R-Tree, the present application can achieve accurate and efficient Adder defect calculation, thereby improving the efficiency and reliability of defect analysis in the semiconductor manufacturing process.

Description

Technical Field

[0001] The present application relates to the technical field, and in particular to a wafer defect detection method, system, device and readable medium. Background Art

[0002] In the field of semiconductor manufacturing, defect analysis is a critical step in the process. The presence of defects may affect the performance and reliability of the device. Therefore, accurate detection and analysis of defects is crucial to improving yield and product quality. At present, the industry has proposed several methods for dealing with defect analysis, but these methods still have some challenges and limitations in practical applications:

[0003] Die-to-Die comparison is a common method that compares the defects of the front and back wafers at the die level. Although the principle of this method is simple, in practice, it is very challenging to achieve accurate matching due to various factors such as translation and rotation between wafers. These changes may cause false positives or negatives, which in turn affects the accuracy of defect analysis.

[0004] Machine learning methods. In recent years, with the development of artificial intelligence technology, machine learning has been widely used in many fields. In the field of semiconductor defect analysis, machine learning algorithms are also used to analyze and predict defects. The advantage of this method is that it can learn patterns and rules from a large amount of data, thereby improving the accuracy of defect detection. However, it also has its limitations, such as requiring a large amount of training data to train the model, which may increase the cost of computing and storage. In addition, the generalization ability of the model may also be limited, resulting in the inability to achieve ideal detection results on some new or unseen data. Summary of the invention

[0005] One object of the present application is to provide a wafer defect detection method, system, device and readable medium, at least to enable the method to accurately and efficiently detect and analyze defects without the technical problems of limitations in computing efficiency and accuracy.

[0006] To achieve the above-mentioned objectives, some embodiments of the present application provide a wafer defect detection method, which includes: when the defect radius is considered, constructing an R-Tree to store the relationship between the current wafer layer and the previous wafer layer, traversing the current wafer layer, and searching for added defects and common defects; traversing the previous wafer layer, searching for missing defects, and determining the defect type; when the defect radius is not considered, constructing a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer, traversing the current wafer layer, and searching for added defects and common defects; traversing the previous wafer layer, searching for missing defects, and determining the defect type.

[0007] Furthermore, the construction of the R-Tree to store the relationship between the current wafer layer and the previous wafer layer includes: initializing the R-Tree index, obtaining the wafer point information of the current wafer layer and the previous wafer layer, the wafer point information including the wafer point coordinates and the defect radius; traversing the wafer point information, defining a bounding box for each wafer point according to the wafer point coordinates and the defect radius, and inserting the bounding box and the point index into the R-Tree.

[0008] Furthermore, constructing the R-Tree to store the relationship between the current wafer layer and the previous wafer layer also includes: creating an index of the previous wafer layer and the current wafer layer according to the R-Tree to store the relationship between the previous wafer layer and the current wafer layer, and obtaining a wafer point index list.

[0009] Furthermore, the search for added defects and common defects includes: traversing each point in the current wafer layer, and searching for the index of the point in the previous wafer layer that intersects with it according to the wafer point coordinates and the defect radius; considering the defect radius, when the distance between the current wafer point and a point in the previous wafer layer is less than or equal to the tolerance difference, marking it as a common defect; otherwise, marking it as an added defect.

[0010] Furthermore, the method of searching for missing defects includes: traversing each point in the previous wafer layer, and searching for the index of the point in the current wafer layer that intersects with the point according to the wafer point coordinates and the defect radius; considering the defect radius, when the distance between a point in the previous wafer layer and any point in the current wafer layer is greater than the tolerance difference, marking it as a missing defect.

[0011] Furthermore, constructing a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer includes: obtaining wafer point information in each wafer layer, the wafer point information including wafer point coordinates; and constructing a KD-Tree index for the previous wafer layer and the current wafer layer according to the wafer point information.

[0012] Furthermore, the search for added defects and common defects includes: traversing each wafer point in the current wafer layer, querying all points in the previous wafer layer that are within the tolerance difference with the current wafer point; when there is a defective point within the tolerance difference, marking the current wafer point as a common defect; when there is no defective point within the tolerance difference, marking the current wafer point as an added defect; the search for missing defects includes: traversing each wafer point in the previous wafer layer, querying all points in the current wafer layer that are within the tolerance difference with the wafer point in the previous wafer layer; when there is no defective point within the tolerance difference, marking the wafer point as a missing defect.

[0013] Some embodiments of the present application also provide a wafer defect detection system, which includes: an R-Tree defect detection module, which is used to construct an R-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is considered, traverse the current wafer layer, find additional defects and common defects; traverse the previous wafer layer, find missing defects, and determine the defect type; a KD-Tree defect detection module, which is used to construct a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is not considered, traverse the current wafer layer, find additional defects and common defects; traverse the previous wafer layer, find missing defects, and determine the defect type.

[0014] Some embodiments of the present application also provide a wafer defect detection device, which includes: one or more processors; and a memory storing computer program instructions, and when the computer program instructions are executed, the processor executes the method as described above.

[0015] Some embodiments of the present application also provide a computer-readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the wafer defect detection method.

[0016] Compared with the prior art, in the solution provided in the embodiment of the present application, the wafer defect detection method provides a fast calculation method based on KD-Tree and R-Tree for Adder defect analysis of front and rear wafers. By combining these two spatial data structures, the present application can efficiently compare defects between wafers, regardless of whether there are slight geometric changes. By establishing an effective mapping and matching between KD-Tree and R-Tree, the present method can achieve accurate and efficient Adder defect calculation, thereby improving the efficiency and reliability of defect analysis in the semiconductor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a wafer defect detection method provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a wafer defect detection system provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of a wafer defect detection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] Explanation of key terms and technical abbreviations:

[0022] Layer: A layer of different materials, structures or patterns applied or formed when manufacturing semiconductor chips (tiny circuits on a wafer). Each layer represents a specific step in the manufacturing process, such as depositing materials, photolithography, etching, etc.

[0023] Adder defect: A defect that exists in the current layer but not in the previous layer. It "adds" a new defect when it did not exist before.

[0024] Missing defect: A defect that existed in the previous layer but was not detected in the current layer. The defect has "disappeared" compared to the previous layer.

[0025] Common defect: A defect that exists at the same location in two consecutive layers. This is a common defect that propagates from one layer to the next.

[0026] Wafer: Mainly used in semiconductor manufacturing and microelectronics engineering, a wafer is a thin round silicon wafer, which is the basic material for manufacturing semiconductor chips. It is usually made of high-purity single crystal silicon and processed through a series of processes such as cutting and polishing.

[0027] In view of the many challenges and limitations faced by the semiconductor manufacturing industry in defect detection, how to improve efficiency and reduce costs while ensuring accuracy has become an urgent problem to be solved in the industry. In response to the above technical problems, the present application embodiment provides a wafer defect detection method, such as Figure 1 As shown, the core of the embodiment of the present application is: when the defect radius is considered, an R-Tree is constructed to store the relationship between the current wafer layer and the previous wafer layer, the current wafer layer is traversed to find added defects and common defects; the previous wafer layer is traversed to find missing defects, and the defect type is determined; when the defect radius is not considered, a KD-Tree is constructed to store the relationship between the current wafer layer and the previous wafer layer, the current wafer layer is traversed to find added defects and common defects; the previous wafer layer is traversed to find missing defects, and the defect type is determined.

[0028] In the preliminary stage of wafer defect detection, the two spatial data structures KD-Tree and R-Tree are first organically integrated. This unique structural fusion strategy not only ensures a significant improvement in computational efficiency, but also cleverly solves the matching problem caused by slight geometric changes between wafers. By combining the characteristics of these two structures, efficient and accurate defect comparison between wafers can be achieved. In order to further improve the accuracy of defect detection, a robust mapping and matching mechanism between KD-Tree and R-Tree is established. Regardless of the geometric changes between wafers, such as slight translation and rotation, the present application can ensure the accurate calculation of Adder defects. In the actual detection process of wafer defects, processing speed is a key indicator for evaluating the pros and cons of a method. The present application gives full play to the advantages of KD-Tree and R-Tree in search and matching, thereby realizing the rapid calculation of Adder defects of front and rear wafers. In summary, the wafer defect detection method provided by the present application combines the advantages of KD-Tree and R-Tree, and successfully realizes efficient, accurate and robust defect analysis.

[0029] In some embodiments of the present application, constructing an R-Tree to store the relationship between the current wafer layer and the previous wafer layer includes: initializing the R-Tree index, obtaining the wafer point information of the current wafer layer and the previous wafer layer, the wafer point information including the wafer point coordinates and the defect radius; traversing the wafer point information, defining a bounding box for each wafer point according to the wafer point coordinates and the defect radius, and inserting the bounding box and the point index into the R-Tree.

[0030] First, initialize an empty R-Tree index structure, which can be achieved by calling index.Index(). This function comes from the R-Tree module and provides a structure for storing and querying spatial data. Next, it is necessary to obtain the wafer point information of the current wafer layer and the previous wafer layer. The information of each wafer point includes its coordinates (x and y) and the radius r of the defect. These data can be obtained in advance from the relevant data source and passed in as a list as the input parameter of the function. Subsequently, the information of these wafer points will be traversed, and for each wafer point, a rectangular bounding box will be defined according to its coordinates and defect radius. Specifically, the coordinates of the lower left corner of the bounding box are (xr, yr), and the coordinates of the upper right corner are (x+r, y+r), which ensures that the entire defect is covered by this bounding box. After defining the bounding box, insert it into the previously initialized R-Tree together with the index of the wafer point. In this way, each wafer point will be assigned a unique index and associated with its corresponding bounding box. After the above steps are repeated, each wafer point of the current wafer layer and the previous wafer layer will be stored in their respective R-Tree structures. Through the above method, not only can the information of wafer points be stored and queried efficiently, but also each defect can be correctly surrounded and recorded for subsequent defect analysis.

[0031] In some embodiments of the present application, constructing an R-Tree to store the relationship between the current wafer layer and the previous wafer layer also includes: creating an index of the previous wafer layer and the current wafer layer according to the R-Tree, which is used to store the relationship between the previous wafer layer and the current wafer layer, and obtain a wafer point index list.

[0032] On the premise that bounding boxes have been created for each wafer point in the current wafer layer and the previous wafer layer and stored in the R-Tree structure. By traversing each wafer point in the current wafer layer and querying the R-Tree of the previous wafer layer for matching or similar wafer points. In this way, a wafer point index list can be obtained, in which each element represents the relationship between a point in the current wafer layer and a point in the previous wafer layer. Find and store the relationship between the two wafer layers. For example, if the 5th point in the current wafer layer has a relationship with the 8th point in the previous wafer layer, there will be an entry in the wafer point index list to represent this relationship. In this way, an index can be created for each pair of related wafer points between the previous wafer layer and the current wafer layer. This not only helps to quickly find and analyze the relationship between the two layers, but also provides key information for subsequent defect analysis and matching. This index creation method ensures the efficiency and accuracy of the data structure, making the processing of large-scale data faster and more stable.

[0033] In some embodiments of the present application, the search for added defects and common defects includes: traversing each point in the current wafer layer, and searching for the index of the point in the previous wafer layer that intersects with it based on the wafer point coordinates and the defect radius; considering the defect radius, when the distance between the current wafer point and a point in the previous wafer layer is less than or equal to the tolerance difference, marking it as a common defect; otherwise, marking it as an added defect.

[0034] According to the list storing the relationship between the points of the current wafer layer and the previous wafer layer, each point in the current wafer layer is traversed and the coordinate and radius information of the point is extracted. In order to find the point of the previous wafer layer associated with the current point, the intersection method of R-Tree is used to find the index of the point of the previous wafer layer that intersects with the current point. A tolerance difference tolerance is added to broaden the search range. After that, the indexes of all points that intersect with the current point are traversed. If the distance to a certain intersection point (minus the radius of the two points) is less than or equal to the given tolerance difference, it is considered to be a common defect. Once an intersection point that meets this condition is found, the point is marked as a common defect. Otherwise, it is marked as an increase defect. Finally, the defect type found (increase or common) is added to the relationship list. If it is an increase defect, it is marked as 1; if it is a common defect, we mark it as 0. The defect comparison between the previous and next wafer layers is effectively realized, and the increase and common defects are found in an efficient and accurate manner. By using the R-Tree structure and the tolerance difference strategy, accuracy and calculation speed are ensured.

[0035] In some embodiments of the present application, the missing defect search includes: traversing each point in the previous wafer layer, and searching for the index of the point in the current wafer layer that intersects with it based on the wafer point coordinates and the defect radius; considering the defect radius, when the distance between a point in the previous wafer layer and any point in the current wafer layer is greater than the tolerance difference, marking it as a missing defect.

[0036] Create a list of point indexes for storing points identified as missing defects, traverse each point in the previous wafer layer, and extract the coordinate and radius information from it. Use the intersection method of R-Tree to find the points in the current wafer layer that intersect with this point. Add a tolerance value tolerance to make the search range slightly larger, so that those intersection points within the tolerance range can be captured more accurately. For each point of the current wafer layer that intersects with the point of the previous wafer layer, calculate the distance between the two points (minus the radius of the two points). If this distance is greater than the given tolerance difference, then it means that there is no point in the current wafer layer that matches the point of the previous wafer layer, so it is marked as a missing defect and its index is added to the missing defect index table. This method can effectively find the points in the previous wafer layer that do not match the current wafer layer, thereby determining which points are missing defects. The accuracy and efficiency of this method are ensured by using the R-Tree structure and the tolerance difference strategy.

[0037] In some embodiments of the present application, constructing a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer includes: obtaining wafer point information in each wafer layer, the wafer point information including wafer point coordinates; and constructing a KD-Tree index for the previous wafer layer and the current wafer layer according to the wafer point information.

[0038] The relationship between the previous wafer layer and the current wafer layer is stored through the KD-Tree data structure. KD-Tree is a partitioned binary tree, which is often used for points in high-dimensional space to quickly find the nearest neighbor points. In order to build a KD-Tree, you first need to extract the coordinate information of the points from each layer of the wafer. Only considering the coordinate information of the wafer points and ignoring its radius information, the coordinate information of the previous wafer layer and the current wafer layer is extracted and then stored in a new list. Next, use this coordinate information to build KD-Tree indexes for the previous wafer layer and the current wafer layer respectively, and then these indexes can be used to perform efficient nearest neighbor queries or other related operations.

[0039] In some embodiments of the present application, the search for added defects and common defects includes: traversing each wafer point in the current wafer layer, querying all points in the previous wafer layer that are within the tolerance difference with the current wafer point; when there is a defective point within the tolerance difference, marking the current wafer point as a common defect; when there is no defective point within the tolerance difference, marking the current wafer point as an added defect; the search for missing defects includes: traversing each wafer point in the previous wafer layer, querying all points in the current wafer layer that are within the tolerance difference with the wafer point in the previous wafer layer; when there is no defective point within the tolerance difference, marking the wafer point as a missing defect.

[0040] Traverse every wafer point in the current wafer layer, and query all points within the tolerance difference in the KD-Tree index of the previous wafer layer. If there is a point in the previous wafer layer within the tolerance difference, the current point is marked as a common defect; otherwise, it is marked as an added defect. Traverse every point in the previous wafer layer, and query all points within the tolerance difference in the KD-Tree index of the current wafer layer. If there is no point in the current wafer layer within the tolerance difference, the point is marked as a missing defect. Through the above steps, three different defect types can be effectively identified, and indexes or relationship lists can be established for each type. Using the KD-Tree data structure, fast queries can be performed in high-dimensional data, thereby improving the efficiency of the algorithm.

[0041] By using two data structures, KD-Tree and R-Tree, this application can perform wafer defect calculations in a shorter time. KD-Tree has a faster query speed when performing nearest neighbor search, while R-Tree is suitable for range query. The combination of the two significantly improves the calculation speed. Considering the radius information, wafer defects can be judged more accurately. By searching for intersection points in the adjacent area, Adder defects and Missing defects can be effectively distinguished to avoid misjudgment, thereby improving the accuracy of defect judgment. This application provides two calculation modes, which are respectively applicable to situations where radius information is considered and not considered. This allows the method to be effectively used in different practical application scenarios and has a wider applicability.

[0042] Figure 2 A wafer defect detection system is shown, which may include:

[0043] An R-Tree defect detection module, wherein the R-Tree defect detection module is used to construct an R-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is considered, traverse the current wafer layer, find added defects and common defects; traverse the previous wafer layer, find missing defects, and determine the defect type;

[0044] The KD-Tree defect detection module is used to construct a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is not considered, traverse the current wafer layer, find added defects and common defects; traverse the previous wafer layer, find missing defects, and determine the defect type.

[0045] It is not difficult to find that the embodiment of the present application is a system embodiment corresponding to the method embodiment. The implementation details of the embodiment of the present application have been explained in the method embodiment. To avoid repetition, they will not be repeated here.

[0046] In addition, the present application also provides a wafer defect detection device, the structure of which is as follows: Figure 3 As shown, the device includes a memory 90 for storing computer-readable instructions and a processor 100 for executing computer-readable instructions, wherein when the computer-readable instructions are executed by the processor, the processor is triggered to execute the wafer defect detection method.

[0047] The methods and / or embodiments in the embodiments of the present application may be implemented as computer software programs. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. When the computer program is executed by the processing unit, the above functions defined in the method of the present application are executed.

[0048] It should be noted that the computer-readable medium described in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device.

[0049] In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0050] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0051] The flow chart or block diagram in the accompanying drawings shows the possible architecture, function and operation of the equipment, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated system for hardware that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0052] As another aspect, the embodiments of the present application further provide a computer-readable medium, which may be included in the device described in the above embodiments; or may exist independently without being assembled into the device. The above computer-readable medium carries one or more computer-readable instructions, which may be executed by a processor to implement the steps of the methods and / or technical solutions of the above multiple embodiments of the present application.

[0053] In a typical configuration of the present application, the terminal and the equipment of the service network each include one or more processors (CPU), input / output interface, network interface and memory.

[0054] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0055] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0056] In addition, an embodiment of the present application further provides a computer program, which is stored in a computer device, so that the computer device executes the method for controlling code execution.

[0057] It should be noted that the present application can be implemented in software and / or a combination of software and hardware, for example, can be implemented using an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In certain embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0058] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic features of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present application is limited by the attached claims rather than the above description, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the device claim can also be implemented by one unit or device through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

Claims

1. A wafer defect detection method, characterized in that: The method comprises: When considering the defect radius, construct an R-Tree to store the relationship between the current wafer layer and the previous wafer layer, initialize the R-Tree index, obtain the wafer point information of the current wafer layer and the previous wafer layer, the wafer point information includes the wafer point coordinates and the defect radius; traverse the wafer point information, define a bounding box for each wafer point according to the wafer point coordinates and the defect radius, and insert the bounding box and the index of the wafer point into the R-Tree; traverse the current wafer layer, find added defects and common defects, mark the defect type, traverse the previous wafer layer, find missing defects, and determine the defect type; When the defect radius is not considered, a KD-Tree is constructed to store the relationship between the current wafer layer and the previous wafer layer, and the wafer point information in each wafer layer is obtained, wherein the wafer point information includes the wafer point coordinates; a KD-Tree index is constructed for the previous wafer layer and the current wafer layer according to the wafer point information; the current wafer layer is traversed to find added defects and common defects, and the defect type is marked; the previous wafer layer is traversed to find missing defects and determine the defect type.

2. The method according to claim 1, characterized in that: The constructing of the R-Tree to store the relationship between the current wafer layer and the previous wafer layer also includes: An index of a previous wafer layer and a current wafer layer is created according to the R-Tree to store the relationship between the previous wafer layer and the current wafer layer, and a wafer point index list is obtained.

3. The method according to claim 2, characterized in that: The search for additional defects and common defects includes: Traversing each point in the current wafer layer, and finding the index of the point in the previous wafer layer intersecting with it according to the wafer point coordinates and the defect radius; Considering the defect radius, when the distance between the current wafer point and a point on the previous wafer layer is less than or equal to the tolerance difference, it is marked as a common defect; otherwise, it is marked as an added defect.

4. The method according to claim 3, characterized in that: The method of finding missing defects includes: Traversing each point in the previous wafer layer, and finding the index of the point in the current wafer layer that intersects with it according to the wafer point coordinates and the defect radius; Considering the defect radius, when the distance between a point in the previous wafer layer and any point in the current wafer layer is greater than the tolerance difference, it is marked as lacking a defect.

5. The method according to claim 1, characterized in that: The search for additional defects and common defects includes: Traverse each wafer point in the current wafer layer and query all points in the previous wafer layer that are within the tolerance difference with the current wafer point; When there is a defect point within the tolerance difference, mark the current wafer point as a common defect; When there is no defect point within the tolerance difference, mark the current wafer point as an added defect; The method of finding missing defects includes: Traverse each wafer point in the previous wafer layer, and query all points in the current wafer layer that are within the tolerance difference with the wafer point in the previous wafer layer; When there is no defect point within the tolerance difference, the wafer point is marked as a missing defect.

6. A wafer defect detection system, characterized in that: The system comprises: An R-Tree defect detection module, wherein the R-Tree defect detection module is used to construct an R-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is considered, initialize the R-Tree index, obtain the wafer point information of the current wafer layer and the previous wafer layer, wherein the wafer point information includes wafer point coordinates and defect radius; traverse the wafer point information, define a bounding box for each wafer point according to the wafer point coordinates and defect radius, and insert the bounding box and the index of the wafer point into the R-Tree; traverse the current wafer layer, search for added defects and common defects, mark the defect type, traverse the previous wafer layer, search for missing defects, and determine the defect type; A KD-Tree defect detection module is used to construct a KD-Tree to store the relationship between the current wafer layer and the previous wafer layer when the defect radius is not considered, and obtain the wafer point information in each wafer layer, wherein the wafer point information includes the wafer point coordinates; construct a KD-Tree index for the previous wafer layer and the current wafer layer according to the wafer point information; traverse the current wafer layer, search for added defects and common defects, mark the defect type, traverse the previous wafer layer, search for missing defects, and determine the defect type.

7. A wafer defect detection device, characterized in that: The device comprises: one or more processors; and A memory storing computer program instructions, which, when executed, cause the processor to perform the method according to any one of claims 1 to 5.

8. A computer-readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method according to any one of claims 1 to 5.

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