Display panel and display device

Abstract

This invention provides a display panel and display device, relating to the field of display technology, for avoiding the need for drilling holes in the color resist while electrically connecting pixel electrodes and corresponding transistors. The display panel includes an array substrate, with a color resist, pixel electrodes, and a first transistor located on the same side of the substrate. The first transistor includes a first semiconductor layer. Along a direction perpendicular to the plane of the substrate, the color resist is located between the first semiconductor and the pixel electrode, and the first semiconductor layer and the pixel electrode are electrically connected via a first connection portion. The first connection portion includes a first sub-connection portion located within a first connection hole, wherein the orthographic projection of the first sub-connection portion onto the plane of the substrate and the orthographic projection of the color resist onto the plane of the substrate do not overlap. Along a direction parallel to the plane of the substrate, the first sub-connection portion and the color resist at least partially overlap; or, along a direction perpendicular to the plane of the substrate, the first semiconductor layer and the pixel electrode are located on the same side of the color resist.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. [Background Technology]

[0002] With the continuous development of display technology, thin film transistor liquid crystal displays (TFT-LCDs) have become dominant in the flat panel display field due to their advantages such as small size, low power consumption, and no radiation.

[0003] Thin-film transistor liquid crystal displays (TFT-LCDs) consist of electrically connected pixel electrodes and transistors. Currently, it is necessary to create vias in the color resist to electrically connect the pixel electrodes and transistors located on both sides of the color resist. The fabrication process of these vias is quite difficult and is not conducive to the small-size design of sub-pixels. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and a display device for electrically connecting pixel electrodes and corresponding transistors while avoiding drilling holes in the color resist.

[0005] On one hand, embodiments of the present invention provide a display panel including an array substrate, the array substrate including a substrate, the array substrate having a display area, the display area including a color resist, a pixel electrode and a first transistor located on the same side of the substrate;

[0006] The first transistor includes a first semiconductor layer; wherein,

[0007] Along a direction perpendicular to the plane of the substrate, the color resist is located between the first semiconductor and the pixel electrode, and the first semiconductor layer and the pixel electrode are electrically connected through a first connection portion; the first connection portion includes a first sub-connection portion located within a first connection hole, and the orthographic projection of the first sub-connection portion onto the plane of the substrate and the orthographic projection of the color resist onto the plane of the substrate do not overlap; along a direction parallel to the plane of the substrate, the first sub-connection portion and the color resist at least partially overlap;

[0008] or,

[0009] Along a direction perpendicular to the plane of the substrate, the first semiconductor layer and the pixel electrode are located on the same side of the color resist.

[0010] On the other hand, embodiments of the present invention provide a display device including the display panel described above.

[0011] The display panel and display device provided in this embodiment of the invention, by including a color resist in the array substrate, allow the color resist and the first transistor to be formed sequentially on the same side of the substrate during the fabrication of the display panel. That is, the color resist and the first transistor can be integrated in the array substrate. Compared with the method of forming the color resist and the first transistor on different substrates to form a color filter substrate including the color resist and a driving substrate including the first transistor, and then aligning and bonding the color filter substrate and the driving substrate to form the display panel, the setting method provided in this embodiment of the invention can improve the alignment accuracy, thereby reducing the possibility of defects such as light leakage caused by alignment deviation and improving the product yield.

[0012] Furthermore, the smaller the subpixel size, the higher the requirement for alignment accuracy. Therefore, by adopting the configuration method provided in the embodiments of the present invention, and by placing the color resist in the array substrate, the subpixel size can be designed to be smaller while ensuring the yield of the display panel. This is beneficial for increasing the number of subpixels per inch in the display panel and for achieving high-resolution display panels. For example, the display panel provided in the embodiments of the present invention can be used in virtual reality display products.

[0013] Furthermore, in the direction perpendicular to the plane of the substrate, embodiments of the present invention ensure that the orthographic projection of the first sub-connection portion onto the plane of the substrate and the orthographic projection of the color resist onto the plane of the substrate do not overlap; or, in the direction perpendicular to the plane of the substrate, the first semiconductor layer and the pixel electrode are located on the same side of the color resist. Both methods ensure electrical connection between the first semiconductor layer and the pixel electrode while avoiding the need for vias in the color resist to connect the pixel electrode and the first semiconductor layer. The greater the thickness of the color resist, the more difficult it is to create vias within it, and the larger the area of ​​the vias required. Therefore, the arrangement provided by the embodiments of the present invention can reduce the technological difficulty of electrically connecting the first semiconductor layer and the pixel electrode. Moreover, if vias are created in the color resist, due to technological limitations, the size of the vias cannot be designed too small, and correspondingly, the area of ​​the color resist cannot be designed too small, making it difficult to meet the requirements of high-resolution display panels. However, the arrangement provided by the embodiments of the present invention ensures electrical connection between the first semiconductor layer and the pixel electrode while also allowing the area of ​​the color resist to be set small enough to further adapt to the design requirements of high-resolution display panels. [Attached Image Description]

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 3 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 4 This is a top view schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention;

[0019] Figure 5 for Figure 4 A schematic diagram of a cross-section along BB';

[0020] Figure 6 for Figure 4 A schematic diagram of a cross section along CC';

[0021] Figure 7 for Figure 4 A top view of the second conductive layer in the process;

[0022] Figure 8 A top view schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0023] Figure 9 for Figure 8 A schematic diagram of a cross-section along DD';

[0024] Figure 10 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 11 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0026] Figure 12 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0027] Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0028] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should be understood that the terms first, second, and third used in the embodiments of the present invention are not used to describe a specific order, but only to distinguish similar objects.

[0033] This invention provides a display panel, such as... Figure 1 and Figure 2 As shown, Figure 1 and Figure 2 This is a cross-sectional schematic diagram of two display panels provided in embodiments of the present invention. The display panel includes an array substrate 1, which has a display area AA and a non-display area NA. Specifically, the array substrate 1 includes a substrate 10, which includes the display area AA and the non-display area NA, with the non-display area NA at least partially surrounding the display area AA. The display area AA includes a color resist 11, a pixel electrode 12, and a first transistor 13 located on the same side of the substrate 10. The first transistor 13 and the pixel electrode 12 are electrically connected. Specifically, as shown... Figure 1 As shown, the first transistor 13 includes a first gate 130 and a first semiconductor layer 133. The first semiconductor layer 133 includes a channel region 1330, a first doped region 1331, and a second doped region 1332, wherein the first doped region 1331 is electrically connected to the data line, and the second doped region 1332 is electrically connected to the pixel electrode 12. Figure 1 As shown, the orthographic projection of the first gate 130 onto the plane of the substrate 10 overlaps with the orthographic projection of the channel region 1330 onto the plane of the substrate 10.

[0034] In embodiments of the present invention, such as Figure 1 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, in this embodiment of the invention, the color resist 11 can be disposed between the first semiconductor layer 133 and the pixel electrode 12, and the first semiconductor layer 133 and the pixel electrode 12 can be electrically connected through the first connection portion 141. Figure 1As shown, the first connecting portion 141 includes a first sub-connecting portion 1411 located within the first connecting hole K1. The orthographic projection of the first sub-connecting portion 1411 onto the plane of the substrate 10 and the orthographic projection of the color resist 11 onto the plane of the substrate 10 do not overlap. In this embodiment of the invention, the first sub-connecting portion 1411 located within the first connecting hole K1 can be made of the same material as the pixel electrode 12 and formed in the same process. Furthermore, along a direction parallel to the plane of the substrate 10, the first sub-connecting portion 1411 and the color resist 11 at least partially overlap. Figure 1 The thickness of the first sub-connector 1411 is greater than the thickness of the color resist 11. Along a direction parallel to the plane where the substrate 10 is located, part of the first sub-connector 1411 overlaps with the color resist 11, while another part does not overlap with the color resist 11, as shown in the diagram.

[0035] Or, such as Figure 2 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, in this embodiment of the invention, the first semiconductor layer 133 and the pixel electrode 12 can be located on the same side of the color resist 11.

[0036] For example, the display panel can be a liquid crystal display panel. The display panel can be configured in conjunction with a backlight module (not shown), with the color resist 11 located on the light-emitting side of the backlight module. For example... Figure 1 and Figure 2 As shown, the display panel also includes a common electrode 51 and a liquid crystal layer 81, with the liquid crystal layer 81 located on the side of the pixel electrode 12 away from the substrate 10. When the display panel is displaying, the first transistor 13 is turned on under the control of the first gate 130. The pixel electrode 12 receives the data voltage provided by the data line through the first transistor 13, and the common electrode 51 receives the common voltage. Under the influence of the electric field between the pixel electrode 12 and the common electrode 51, the liquid crystal molecules in the liquid crystal layer 81 deflect at a specific angle to adjust the transmittance of the light emitted by the backlight module. Furthermore, the light emitted by the backlight module can be emitted in a specific color after passing through the color resist 11, causing the corresponding sub-pixels to light up in the desired color.

[0037] The display panel provided in this embodiment of the invention includes a color resist 11 on the array substrate 1. During the fabrication of the display panel, the color resist 11 and the first transistor 13 can be formed sequentially on the same side of the substrate 10. That is, the color resist 11 and the first transistor 13 can be integrated in the array substrate 1. Compared with the method of forming the color resist 11 and the first transistor 13 on different substrates to form a color filter substrate including the color resist 11 and a driving substrate including the first transistor 13, and then aligning and bonding the color filter substrate and the driving substrate to form the display panel, the setting method provided in this embodiment of the invention can improve the alignment accuracy, thereby reducing the possibility of defects such as light leakage caused by alignment deviation and improving the product yield.

[0038] Furthermore, the smaller the subpixel size, the higher the requirement for alignment accuracy. Therefore, by adopting the configuration method provided in this embodiment of the invention, and by placing the color resist 11 in the array substrate 1, the subpixel size can be designed to be smaller while ensuring the yield of the display panel. This is beneficial for increasing the number of subpixels per inch (PPI) in the display panel, and for achieving high-resolution display panels. For example, the display panel provided in this embodiment of the invention can be used in display products for virtual reality (VR).

[0039] In addition, such as Figure 1 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, the embodiment of the present invention ensures that the orthographic projection of the first sub-connection portion 1411 onto the plane where the substrate 10 is located and the orthographic projection of the color resist 11 onto the plane where the substrate 10 is located do not overlap; or, as... Figure 2 As shown, along a direction perpendicular to the plane of the substrate 10, the first semiconductor layer 133 and the pixel electrode 12 are located on the same side of the color resist 11. This ensures electrical connection between the first semiconductor layer 133 and the pixel electrode 12 while avoiding the need for vias in the color resist 11 to connect the pixel electrode 12 and the first semiconductor layer 133. The greater the thickness of the color resist 11, the more difficult it is to create vias within it, and the larger the area of ​​the vias required. Therefore, the arrangement provided in this embodiment of the invention reduces the technological difficulty of electrically connecting the first semiconductor layer 133 and the pixel electrode 12. Furthermore, if vias are created in the color resist 11, due to technological limitations, the size of the vias cannot be designed to be too small, and correspondingly, the area of ​​the color resist 11 cannot be designed to be too small, making it difficult to meet the requirements of high-resolution display panels. However, the arrangement provided in this embodiment of the invention ensures electrical connection between the first semiconductor layer 133 and the pixel electrode 12 while also allowing the area of ​​the color resist 11 to be set sufficiently small to further adapt to the design requirements of high-resolution display panels.

[0040] For example, such as Figure 1 and Figure 2 As shown, the array substrate 1 further includes a first conductive layer M1 and a second conductive layer M2. The first conductive layer M1 includes the first gate 130 of the first transistor 13 described above. The second conductive layer M2 includes the first electrode 131 of the first transistor 13 described above, and the first electrode 131 is electrically connected to the data line. The first electrode 131 includes a source or a drain. For example, the first transistor includes a P-type transistor or an N-type transistor.

[0041] Optionally, the first conductive layer M1 or the second conductive layer M2 may include a metal layer.

[0042] Figure 1 and Figure 2The illustration shows the first conductive layer M1 located on the side of the first semiconductor layer 133 away from the substrate 10, and the second conductive layer M2 located on the side of the first conductive layer M1 away from the first semiconductor layer 133. Optionally, such as... Figure 1 and Figure 2 As shown, the array substrate 1 further includes a first gate insulating layer 221 and a first interlayer dielectric layer 231. The first gate insulating layer 221 is located between the first semiconductor layer 133 and the first conductive layer M1, and the first interlayer dielectric layer 231 is located between the first conductive layer M1 and the second conductive layer M2.

[0043] For example, such as Figure 1 and Figure 2 As shown, the array substrate 1 further includes a first electrode insulating layer 31 and a second electrode insulating layer 32. The first electrode insulating layer 31 is located between the common electrode 51 and the pixel electrode 12, and the second electrode insulating layer 32 is located between the pixel electrode 12 and the second conductive layer M2.

[0044] Optional, such as Figure 1 As shown, in this embodiment of the invention, the color resist 11 can be disposed on the side of the second conductive layer M2 away from the first conductive layer M1. Optionally, as... Figure 1 As shown, the second electrode insulating layer 32 includes a first sub-electrode insulating layer 321 and a second sub-electrode insulating layer 322 stacked together. The first sub-electrode insulating layer 321 is located between the color resist 11 and the pixel electrode 12, and the second sub-electrode insulating layer 322 is located between the color resist 11 and the second conductive layer M2. Optionally, the first sub-electrode insulating layer 321 includes a planarization layer to improve the flatness of its surface, thereby improving the fabrication yield of the pixel electrode 12 located on the surface of the first sub-electrode insulating layer 321.

[0045] For example, in embodiments of the present invention, the first connection hole K1 can penetrate the entire insulating layer between the first semiconductor layer 133 and the pixel electrode 12, such as... Figure 1 As shown, the first connection hole K1 penetrates the first sub-electrode insulating layer 321, the second sub-electrode insulating layer 322, the first interlayer dielectric layer 231, and the first gate insulating layer 221.

[0046] Alternatively, in embodiments of the present invention, the depth of the first connection hole K1 can be set to be shallower, so that the first connection hole K1 only penetrates a portion of the insulating layer between the first semiconductor layer 133 and the pixel electrode 12. For example, as shown... Figure 3 As shown, Figure 3This is a cross-sectional schematic diagram of another display panel provided by an embodiment of the present invention. In this embodiment, the first connecting portion 141 can be configured to further include a first connecting electrode 1410 located between the pixel electrode 12 and the first semiconductor layer 133. The orthographic projection of the first connecting electrode 1410 onto the plane of the substrate 10 and the orthographic projection of the first semiconductor layer 133 onto the plane of the substrate 10 at least partially overlap, and the orthographic projection of the first connecting electrode 1410 onto the plane of the substrate 10 and the orthographic projection of the pixel electrode 12 onto the plane of the substrate 10 at least partially overlap. In this embodiment, the first connecting hole K1 can be configured to penetrate only the insulating layer located between the pixel electrode 12 and the first connecting electrode 1410, and the first sub-connecting portion 1411 located within the first connecting hole K1 electrically connects the first connecting electrode 1410 and the pixel electrode 12. Figure 3 As illustrated, the first connecting electrode 1410 is located between the first sub-electrode insulating layer 321 and the second sub-electrode insulating layer 322. The insulating layer between the pixel electrode 12 and the first connecting electrode 1410 includes the first sub-electrode insulating layer 321, and the first connecting hole K1 only penetrates the first sub-electrode insulating layer 321.

[0047] Optional, such as Figure 3 As shown, the first connecting portion 141 further includes a second sub-connecting portion 1412 located within the second connecting hole K2; along a direction h1 perpendicular to the plane of the substrate 10, the second connecting hole K2 is located between the first connecting electrode 1410 and the first semiconductor layer 133. The second sub-connecting portion 1412 electrically connects the first connecting electrode 1410 and the first semiconductor layer 133. In this embodiment of the invention, the second connecting hole K2 only penetrates the insulating layer between the first connecting electrode 1410 and the first semiconductor layer 133. Figure 3 As shown, the second connection hole K2 penetrates the second sub-electrode insulating layer 322, the first interlayer dielectric layer 231, and the first gate insulating layer 221.

[0048] In this embodiment of the invention, by having the first sub-connection portion 1411, the first connection electrode 1410, and the second sub-connection portion 1412 jointly connect the pixel electrode 12 and the first semiconductor layer 133, it is not necessary to set a via with a large depth between the first semiconductor layer 133 and the pixel electrode 12. This reduces the connection difficulty between the pixel electrode 12 and the first semiconductor layer 133. In addition, the area of ​​the first connection hole K1 can be reduced. In this way, while ensuring that the orthographic projection of the first connection hole K1 on the plane of the substrate 10 does not overlap with the color resist 11, the area of ​​the color resist 11 can be set as large as possible, which is beneficial to increasing the aperture ratio of the sub-pixel.

[0049] Optional, such as Figure 3As shown, the array substrate 1 further includes a third conductive layer M3. The third conductive layer M3 and the color resist 11 are both located between the second sub-electrode insulating layer 322 and the first sub-electrode insulating layer 321. The third conductive layer M3 includes the aforementioned first connection electrode 1410. Exemplarily, the third conductive layer M3 comprises metal.

[0050] For example, such as Figure 1 and Figure 3 As shown, the first sub-electrode insulating layer 321 includes a first sub-part 3211 and a second sub-part 3212 located in the display area AA. The orthographic projection of the first sub-part 3211 onto the plane of the substrate 10 overlaps with the orthographic projection of the color resist 11 onto the plane of the substrate 10. The orthographic projection of the second sub-part 3212 onto the plane of the substrate 10 does not overlap with the orthographic projection of the color resist 11 onto the plane of the substrate 10. Figure 3 As shown, the orthographic projection of the second sub-part 3212 onto the plane where the substrate 10 is located overlaps with the orthographic projection of the first connecting electrode 1410 onto the plane where the substrate 10 is located.

[0051] Optional, such as Figure 1 and Figure 3 As shown, in this embodiment of the invention, the first connecting hole K1 can pass through the second sub-part 3212 so that the orthographic projection of the first connecting hole K1 on the plane where the substrate 10 is located does not overlap with the orthographic projection of the color resist 11 on the plane where the substrate 10 is located.

[0052] It should be noted that, in this embodiment of the invention, the first buffer layer 211, the first gate insulating layer 221, the first interlayer dielectric layer 231, the second sub-electrode insulating layer 322, and the first sub-electrode insulating layer 321 may include one or more insulating layers. The materials of the different insulating layers may be the same or different. For example, when multiple insulating layers are included, some insulating layers may be silicon oxide, and other insulating layers may be silicon nitride. Figure 1 and Figure 3 The first gate insulating layer 221 includes a first sub-gate insulating layer 2211 and a second sub-gate insulating layer 2212, and the first interlayer dielectric layer 231 includes a first sub-sublayer dielectric layer 2311, a second sub-sublayer dielectric layer 2312 and a third sub-sublayer dielectric layer 2313 as an illustration. Figure 2 The first gate insulating layer 221, the first interlayer dielectric layer 231, and the second electrode insulating layer 32 are all single-layer structures, as illustrated.

[0053] For example, the array substrate 1 includes a plurality of color resists 11 with different colors, such as Figure 4 As shown, Figure 4This is a top view schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention. Multiple color resists 11 are arrayed in a first direction h21 and a second direction h22. The first direction h21 and the second direction h22 intersect; both are parallel to the plane containing the substrate 10. Figure 4 The color resist 11 is illustrated by including a first color color resist 111 and a second color color resist 112. For example, the first color includes any one of red, green, and blue, and the second color includes the other one of red, green, and blue besides the first color.

[0054] Combination Figure 4 and Figure 5 As shown, Figure 5 for Figure 4 A cross-sectional view along BB' shows that the array substrate 1 further includes a first light-blocking portion 41 located in the display area AA. In this embodiment, the first light-blocking portion 41 can be configured to include a first sub-light-blocking portion 411 extending along a first direction h21 and a second sub-light-blocking portion 412 extending along a second direction h22. At least a portion of the first sub-light-blocking portion 411 is located between two adjacent color resists 11 in the second direction h22; at least a portion of the second sub-light-blocking portion 412 is located between two adjacent color resists 11 in the first direction h21. The arrangement of the first sub-light-blocking portion 411 and the second sub-light-blocking portion 412 can block the opaque structure in the display area AA to avoid light leakage problems caused by electric field disturbances near the opaque structure. For example, the opaque structure includes a first transistor 13 and opaque wiring portions such as gate lines and data lines. On the other hand, the first sub-light-blocking portion 411 and the second sub-light-blocking portion 412 can also prevent color mixing between different sub-pixels, improve display contrast, and enhance display effects.

[0055] In this embodiment of the invention, by placing the first light-blocking part 41 in the array substrate 1, compared with placing the first light-blocking part 41 in the opposing substrate opposite to the array substrate 1, light leakage can be avoided while the width of the first light-blocking part 41 can be set as small as possible, which is beneficial to improving the aperture ratio of the sub-pixel. Correspondingly, the light transmittance of the display panel can also be improved.

[0056] Optionally, in embodiments of the present invention, at least one of the first sub-light-blocking portion 411 and the second sub-light-blocking portion 412 may be configured to include metal. Compared with resin materials, metal has better light-blocking performance. By configuring at least one of the first sub-light-blocking portion 411 and the second sub-light-blocking portion 412 to include metal, the present invention can reduce the thickness of the first sub-light-blocking portion 411 or the second sub-light-blocking portion 412 and reduce the width of the first sub-light-blocking portion 411 or the second sub-light-blocking portion 412 while ensuring the light-blocking performance of the first sub-light-blocking portion 411 and / or the second sub-light-blocking portion 412, thereby further improving the aperture ratio of the sub-pixel. For example, the metal may include a metal material with relatively low reflectivity to reduce visible reflection. Optionally, the metal may include at least one of molybdenum, chromium, aluminum, titanium, and copper, or at least one of the metal oxides and metal nitrides corresponding to molybdenum, chromium, aluminum, titanium, and copper.

[0057] Furthermore, in this embodiment of the invention, by using metal to fabricate the first light-blocking portion 41 and / or the second light-blocking portion 42, the thickness of the first light-blocking portion 41 and / or the second light-blocking portion 42 can be made as thin as possible while ensuring light-blocking performance. When the color resist 11 is located on the side of the first light-blocking portion 41 away from the substrate 10, and when the orthographic projection of the color resist 11 onto the plane of the substrate 10 at least partially overlaps with the orthographic projection of the first light-blocking portion 41 onto the plane of the substrate 10, as... Figure 6 As shown, Figure 6 for Figure 4 According to a cross-sectional schematic diagram along CC', the embodiment of the present invention can avoid forming an excessively large included angle β between the bottom surface S1 and the side surface S2 of the color resist 11, which can better form and cover the first sub-electrode insulating layer 321 formed after the color resist 11, thus improving the yield of the display panel.

[0058] Optionally, in embodiments of the present invention, a first film layer may be formed in the array substrate 1, and the first film layer may include a first portion and a second portion that are mutually insulated from each other. The first portion includes the aforementioned first sub-light-blocking portion 411, and the second portion includes the aforementioned first connecting electrode 1410. That is, the first sub-light-blocking portion 411 and the first connecting electrode 1410 may be co-formed in the first film layer. Co-formed means that they are made of the same material and formed in the same patterning process.

[0059] For example, the first film layer can be the metal film layer in the array substrate 1 that is closest to the color resist 11, so as to reduce the distance between the first sub-blocking part 411 and the color resist 11, and prevent the large-angle light emitted by one of the sub-pixels from passing through the area between the first sub-blocking part 411 and the color resist 11 to hit another sub-pixel, thereby avoiding color mixing between different sub-pixels. Figure 5The array substrate 1 includes a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3 as an example, wherein the first film layer includes the third conductive layer M3.

[0060] Optional, such as Figure 4 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, the embodiment of the present invention can make the first connecting electrode 1410 and the first sub-light blocking part 411 not overlap, so that when the two are disposed in the same layer on the first film layer, the first connecting electrode 1410 and the first sub-light blocking part 411 are insulated from each other.

[0061] Optional, such as Figure 4 As shown, in this embodiment of the invention, the first connecting electrode 1410 and the second sub-light blocking part 412 can overlap at least partially, so that when the first connecting electrode 1410 and the first sub-light blocking part 411 are disposed in the same layer on the first film layer, the first connecting electrode 1410 avoids occupying additional space in the opening area of ​​the sub-pixel for transmitting light, thus ensuring the aperture ratio of the sub-pixel.

[0062] For example, such as Figure 4 As shown, in this embodiment of the invention, the second sub-light-blocking part 412 can be electrically connected to the first transistor 13. Combined with... Figure 5 As shown, in this embodiment of the invention, the second sub-light-blocking portion 412 can be electrically connected to the first electrode 131 of the first transistor 13. The first electrode 131 includes a source or a drain. The first electrode 131 is electrically connected to the first doped region 1331 of the first semiconductor layer 133. When the display panel is displaying, the second sub-light-blocking portion 412 provides a data signal to the first transistor 13. This configuration is equivalent to multiplexing the data line into the second sub-light-blocking portion 412, which can further improve the aperture ratio of the sub-pixels and simplify the manufacturing process of the display panel.

[0063] Optional, such as Figure 5 As shown, in an embodiment of the invention, along a direction perpendicular to the plane of the substrate 10, the second sub-light-blocking portion 412 can be located between the first connecting electrode 1410 and the first semiconductor layer 133. (Combined) Figure 4 , Figure 5 and Figure 7 As shown, Figure 7 for Figure 4 A top view of the second conductive layer shows that the second sub-blocking portion 412 includes a first sub-hole K21. The orthographic projection of the first connecting electrode 1410 onto the plane of the substrate 10 at least partially overlaps with the first sub-hole K21. The first sub-hole K21 allows the first connecting electrode 1410 to be electrically connected to the first semiconductor layer 133 through a connecting portion located within the first sub-hole K21. Based on this arrangement, the electrical connection between the first connecting electrode 1410 and the first semiconductor layer 133 can be maintained without affecting the aperture ratio of the sub-pixel.

[0064] For example, such as Figure 4 and Figure 5 As shown, the array substrate 1 also includes a second sub-hole K22, and the first electrode 131 of the first transistor 13 is electrically connected to the first doped region 1331 of the first semiconductor layer 133 through a connection portion located within the second sub-hole K22. Figure 5 As shown, the second sub-hole K22 penetrates the first gate insulating layer 221 and the first interlayer dielectric layer 231.

[0065] Optionally, in addition to the first and second parts described above, embodiments of the present invention may also provide a third part in the first film layer. The third part is insulated from both the first and second parts, and includes the second sub-light-blocking portion 412 described above. (Combined with...) Figure 8 and Figure 9 As shown, Figure 8 This is a top view schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention. Figure 9 for Figure 8 A cross-sectional schematic diagram along DD' is shown, illustrating an array substrate 1 comprising a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3, with the first film layer including the third conductive layer M3. Based on this arrangement, the first sub-light-blocking portion 411, the second sub-light-blocking portion 412, and the first connecting electrode 1410 can be disposed in the same layer on the first film layer. This simplifies the manufacturing process of the display panel and reduces its thickness. Furthermore, it reduces the distance between the second sub-light-blocking portion 412 and the color resist 11, preventing color mixing between adjacent sub-pixels and ensuring display quality. Exemplarily, in embodiments of the present invention, both the first sub-light-blocking portion 411 and the second sub-light-blocking portion 412 can be in contact with the color resist 11.

[0066] For example, such as Figure 8 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, the embodiments of the present invention can ensure that the orthographic projection of the first connecting electrode 1410 on the plane where the substrate 10 is located does not overlap with the orthographic projection of the first sub-light blocking part 411 on the plane where the substrate 10 is located, and that the orthographic projection of the first connecting electrode 1410 on the plane where the substrate 10 is located does not overlap with the orthographic projection of the second sub-light blocking part 412 on the plane where the substrate 10 is located, so as to reduce the thickness of the display panel and simplify the manufacturing process of the display panel while ensuring that the first connecting electrode 1410 is mutually insulated from the first sub-light blocking part 411 and the second sub-light blocking part 412 respectively.

[0067] It should be noted that, Figure 4 and Figure 8 The shape of the orthographic projection of the pixel electrode 12 onto the plane of the substrate 10 shown is only an illustration. The shape of the orthographic projection of the pixel electrode 12 onto the plane of the substrate 10 can be adjusted according to different design requirements in the embodiments of the present invention.

[0068] See you again Figure 1 and Figure 3 As shown, the array substrate 1 also includes a non-display area NA, which includes a second light-blocking portion 42. When the display panel is displaying, the second light-blocking portion 42 can prevent light emitted by the backlight module from leaking out from the non-display area NA.

[0069] Optional, such as Figure 1 and Figure 3 As shown, in this embodiment of the invention, the second light-blocking portion 42 can be disposed between the second sub-electrode insulating layer 322 and the first sub-electrode insulating layer 321. Exemplarily, in this embodiment of the invention, the second light-blocking portion 42 can include a third sub-light-blocking portion 421, which includes a light-absorbing material; the light-absorbing material can prevent the third sub-light-blocking portion 421 from coupling with the conductive structure in the non-display area NA. Exemplarily, the light-absorbing material includes resin.

[0070] For example, such as Figure 1 and Figure 3 As shown, the array substrate 1 also includes a common connection line 52 located in the non-display area NA; the common electrode 51 and the common connection line 52 are electrically connected through a second connection portion 142. Exemplarily, the common connection line 52 receives a common voltage signal provided by a driver chip (not shown) and transmits it to the common electrode 51 through the second connection portion 142. Figure 1 and Figure 3 As shown, the second connection portion 142 includes a third sub-connection portion 1421 located within the third connection hole K3. The third connection hole K3 penetrates at least a portion of the film layer between the common electrode 51 and the common connection line 52. Along a direction parallel to the plane of the substrate 10, the third sub-connection portion 1421 at least partially overlaps with the third sub-light-blocking portion 421.

[0071] For example, such as Figure 1 and Figure 3 As shown, the orthographic projection of the third sub-connection portion 1421 onto the plane of the substrate 10 and the orthographic projection of the third sub-light blocking portion 421 onto the plane of the substrate 10 do not overlap. This arrangement avoids the need to provide the third connection hole K3 in the third sub-light blocking portion 421. While ensuring the smooth connection between the common electrode 51 and the common connection line 52 and reducing the fabrication difficulty of the third connection hole K3, the thickness of the third sub-light blocking portion 421 can be set to be larger to ensure the light absorption performance of the third sub-light blocking portion 421.

[0072] Continue to refer to Figure 1 and Figure 3As shown, the first sub-electrode insulating layer 321 further includes a third sub-part 3213 and a fourth sub-part 3214 located in the non-display area NA. The orthographic projection of the third sub-part 3213 onto the plane of the substrate 10 and the orthographic projection of the third sub-light-blocking part 421 onto the plane of the substrate 10 do not overlap, while the orthographic projection of the fourth sub-part 3214 onto the plane of the substrate 10 and the orthographic projection of the third sub-light-blocking part 421 onto the plane of the substrate 10 overlap. In this embodiment of the invention, the third connecting hole K3 can pass through the third sub-part 3213 to avoid the third connecting hole K3 passing through the third sub-light-blocking part 421, thus reducing the manufacturing difficulty of the third connecting hole K3.

[0073] For example, such as Figure 1 and Figure 3 As shown, in this embodiment of the invention, the common connection line 52 may include a first sub-common connection line 521 located in the first conductive layer M1 and a second sub-common connection line 522 located in the second conductive layer M2. The first sub-common connection line 521 and the second sub-common connection line 522 are electrically connected to reduce the resistance of the common connection line 52.

[0074] When setting the third connection hole K3, for example, in this embodiment of the invention, the third connection hole K3 can penetrate all the insulating layers between the common electrode 51 and the common connection line 52. Figure 1 The diagram illustrates a common electrode 51 and a common connection line 52, which include a first electrode insulating layer 31, a first sub-electrode insulating layer 321, and a second sub-electrode insulating layer 322, with a third connection hole K3 penetrating through the first electrode insulating layer 31, the first sub-electrode insulating layer 321, and the second sub-electrode insulating layer 322.

[0075] Or, such as Figure 3 As shown, in this embodiment of the invention, the depth of the third connecting hole K3 can be set to be relatively shallow, and a second connecting electrode 1420 is provided between the third connecting hole K3 and the common connecting line 52. The third connecting hole K3 penetrates the first electrode insulating layer 31 and the first sub-electrode insulating layer 321, as shown... Figure 3 As shown, the second connecting electrode 1420 is electrically connected to the common connecting line 52 and the third sub-connecting part 1421. Based on this arrangement, the depth of the third connecting hole K3 can be reduced, thereby reducing the difficulty of fabricating the third connecting hole K3.

[0076] For example, in addition to the first and second parts described above, embodiments of the present invention may also provide a fourth part in the first film layer, the fourth part including the second connecting electrode 1420, that is, as shown below. Figure 3 As shown, in this embodiment of the invention, the second connecting electrode 1420 and the first connecting electrode 1410 can be disposed in the same layer on the first film layer to simplify the manufacturing process of the display panel. Figure 3 The first film layer includes a third conductive layer M3 as an example.

[0077] Optional, such as Figure 3 As shown, the second light-blocking part 42 also includes a fourth sub-light-blocking part 422, which includes the aforementioned second connecting electrode 1420. This configuration effectively reuses the second connecting electrode 1420 as the fourth sub-light-blocking part 422. While reducing the manufacturing difficulty of the third connecting hole K3 by avoiding the third sub-light-blocking part 421, it also prevents light leakage from the display panel at locations where the third sub-light-blocking part 421 is not located.

[0078] For example, such as Figure 3 As shown, the orthographic projection of the second connecting electrode 1420 onto the plane of the substrate 10 at least partially overlaps with the orthographic projection of the third sub-light blocking part 421 onto the plane of the substrate 10, so as to avoid forming a gap between the two and thus avoid light leakage at the gap.

[0079] Optional, such as Figure 2 As shown, along the direction h1 perpendicular to the plane where the substrate 10 is located, in this embodiment of the invention, the first semiconductor layer 133 and the pixel electrode 12 can be located on the same side of the color resist 11. Figure 2 The illustration shows the first semiconductor layer 133 and the pixel electrode 12 both located on the side of the color resist 11 away from the substrate 10. In this embodiment of the invention, the first semiconductor layer 133 and the pixel electrode 12 can be electrically connected through a third connection portion 143 located within a fourth connection hole K4; the fourth connection hole K4 is located on the side of the color resist 11 closer to the pixel electrode 12. Furthermore, in a direction parallel to the substrate 10, the fourth connection hole K4 and the color resist 11 do not overlap. Based on this arrangement, when the third connection portion 143 is provided within the fourth connection hole K4 to electrically connect the first semiconductor layer 133 and the pixel electrode 12, the fourth connection hole K4 can be prevented from passing through the color resist 11, thus reducing the fabrication difficulty of the fourth connection hole K4.

[0080] Optional, such as Figure 2 As shown, the fourth connection hole K4 penetrates the first gate insulating layer 221, the first interlayer dielectric layer 231, and the second electrode insulating layer 32. Figure 1 and Figure 3 The difference is that, in Figure 2 In the first gate insulating layer 221, the first interlayer dielectric layer 231, and the second electrode insulating layer 32 are located on the same side of the color resist 11.

[0081] For example, in embodiments of the present invention, the first semiconductor layer 133 may comprise a metal oxide. Based on this configuration, not only can the carrier mobility in the first semiconductor layer 133 be improved, but also, when displaying a panel according to… Figure 2When designing the film layer architecture shown, the light transmittance of the first semiconductor layer 133 can be increased, thereby reducing the visibility of the first semiconductor layer 133 and improving the display effect. Optionally, the first semiconductor layer 133 includes indium gallium zinc oxide (IGZO).

[0082] Optional, such as Figure 10 As shown, Figure 10 This is a cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention. Along the direction h1 perpendicular to the plane where the substrate 10 is located, the first semiconductor layer 133 and the pixel electrode 12 are located on the same side of the color resist 11. In this embodiment of the present invention, there is no insulating layer between the first semiconductor layer 133 and the pixel electrode 12, allowing the first semiconductor layer 133 and the pixel electrode 12 to be electrically connected by contact. With this configuration, there is no need to prepare a hole for electrically connecting the pixel electrode 12 and the first semiconductor layer 133, which can simplify the manufacturing process of the display panel.

[0083] For example, such as Figure 10 As shown, in this embodiment of the invention, the pixel electrode 12 can be located on the side of the first semiconductor layer 133 closest to the substrate 10. That is, the first transistor 13 forms a bottom-gate bottom-contact structure, where bottom contact means that the surface of the first semiconductor layer 133 closest to the substrate 10 is in contact with the pixel electrode 12 and the first electrode 131, respectively. Based on this structure, when the display panel is displaying, charge carriers can be directly injected into the channel region 1330 of the first transistor 13 from the edge of the pixel electrode 12 or the first electrode 131, which is beneficial to improving the carrier injection efficiency. Of course, in this embodiment of the invention, both the first electrode 131 and the pixel electrode 12 can be located on the side of the first semiconductor layer 133 away from the substrate 10, so that both the first electrode 131 and the pixel electrode 12 are in contact with the surface of the first semiconductor layer 133 away from the substrate 10, that is, the first transistor 13 forms a bottom-gate top-contact structure.

[0084] Optional, such as Figure 10 As shown, the first gate insulating layer 221 is located between the first conductive layer M1 and the first semiconductor layer 133. The first electrode 131 of the first transistor 13 and the pixel electrode 12 are both located between the first gate insulating layer 221 and the first semiconductor layer 133. The first doped region 1331 of the first semiconductor layer 133 is located on the side of the first electrode 131 away from the substrate 10, and the first doped region 1331 is electrically connected to the first electrode 131. The second doped region 1332 of the first semiconductor layer 133 is located on the side of the pixel electrode 12 away from the substrate 10, and the second doped region 1332 is electrically connected to the pixel electrode 12. For example, as... Figure 10 As shown, the array substrate 1 also includes an electrode insulating layer 30 located between the common electrode 51 and the pixel electrode 12.

[0085] For example, in embodiments of the present invention, the pixel electrode 12 and the first electrode 131 of the first transistor 13 can be fabricated using the same material in the same patterning process. For instance, both the pixel electrode 12 and the first electrode 131 can be made of transparent metal oxide to avoid affecting the normal light emission of the sub-pixel. Alternatively, in embodiments of the present invention, the pixel electrode 12 and the first electrode 131 of the first transistor 13 can be fabricated using different materials in different patterning processes. For instance, in embodiments of the present invention, the pixel electrode 12 can be made of transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the first electrode 131 can be made of metal.

[0086] For example, in an embodiment of the present invention, the non-display area NA includes a gate driving circuit, which includes cascaded shift register units; the shift register units are electrically connected to the gate line. Figure 1 , Figure 2 , Figure 3 and Figure 10 As shown, the shift register unit includes a second transistor 14. The second transistor 14 includes a second gate 140, a first electrode 141, a second electrode 142, and a second semiconductor layer 143. One of the first electrode 141 and the second electrode 142 is the source, and the other is the drain.

[0087] In one implementation, such as Figure 1 and Figure 3 As shown, embodiments of the present invention can make the first semiconductor layer 133 and the second semiconductor layer 143 use the same material and be formed in the same patterning process, and make the first gate 130 and the second gate 140 use the same material and be formed in the same patterning process. Optionally, the materials of the first semiconductor layer 133 and the second semiconductor layer 143 include low-temperature polycrystalline silicon or metal oxide.

[0088] Alternatively, embodiments of the present invention may also allow at least a portion of the structure in the first transistor 13 and the second transistor 14 to be disposed in different layers. For example... Figure 2 and Figure 10As shown, in this embodiment of the invention, the first transistor 13 and the second transistor 14 can be located on opposite sides of the color resist 11. Along direction h1 perpendicular to the plane of the substrate 10, in this embodiment of the invention, the first semiconductor layer 133 and the second semiconductor layer 143 can be located on opposite sides of the color resist 11, and the first gate 130 and the second gate 140 can be located on opposite sides of the color resist 11. Optionally, the materials of the first semiconductor layer 133 and the second semiconductor layer 143 can be the same or different; the materials of the first gate 130 and the second gate 140 can be the same or different. Using this arrangement, the first transistor 13 and the second transistor 14 can be independently configured. During the fabrication of the display panel, the characteristics of the first transistor 13 and the second transistor 14 can be adjusted according to different requirements, which is beneficial to improving the process flexibility of both.

[0089] Optional, such as Figure 2 and Figure 10 As shown, the array substrate 1 further includes a fourth conductive layer M4 and a fifth conductive layer M5. The fourth conductive layer M4 includes the second gate 140 of the second transistor 14, and the fifth conductive layer M5 includes the first electrode 141 and the second electrode 142 of the second transistor 14. For example, as... Figure 2 and Figure 10 As shown, both the fourth conductive layer M4 and the fifth conductive layer M5 are located on the side of the color resist 11 closest to the substrate 10. Optionally, the fourth conductive layer M4 and the fifth conductive layer M5 may comprise metal.

[0090] For example, such as Figure 2 and Figure 10 As shown, the array substrate 1 further includes a second gate insulating layer 222 and a second interlayer dielectric layer 232. The second gate insulating layer 222 is located between the second semiconductor layer 143 and the fourth conductive layer M4, and the second interlayer dielectric layer 232 is located between the fifth conductive layer M5 and the fourth conductive layer M4. Figure 2 and Figure 10 The second interlayer dielectric layer 232 includes a fourth sub-interlayer dielectric layer 2321 and a fifth sub-interlayer dielectric layer 2322 stacked together as an example.

[0091] Or, such as Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 The following is a cross-sectional schematic diagram of two other display panels provided in the embodiments of the present invention. In the embodiments of the present invention, the first transistor 13 and the second transistor 14 are both located on the side of the color resist 11 close to the substrate 10, the first semiconductor layer 133 and the second semiconductor layer 143 are disposed in different layers, and the first gate 130 and the second gate 140 are disposed in different layers.

[0092] and Figure 2 and Figure 10The difference is that, in Figure 11 and Figure 12 In addition to the first electrode 131 of the first transistor 13, the second conductive layer M2 also includes the first electrode 141 and the second electrode 142 of the second transistor 14.

[0093] like Figure 11 and Figure 12 As shown, the array substrate 1 further includes a fourth conductive layer M4, which includes the second gate 140 of the second transistor 14. Along the direction away from the substrate 10, the second semiconductor layer 143, the fourth conductive layer M4, the first semiconductor layer 133, the first conductive layer M1, and the second conductive layer M2 are sequentially stacked.

[0094] For example, such as Figure 2 , Figure 10 and Figure 11 As shown, the display area AA further includes a first insulating layer 61, a third light-blocking portion 43 located in the display area AA, and a fourth light-blocking portion 44 located in the non-display area NA. The first insulating layer 61 includes a first opening 610, and at least a portion of the color resist 11 is located within the first opening 610. The third light-blocking portion 43 and the fourth light-blocking portion 44 are located on the side of the first insulating layer 61 away from the substrate 10. In the fabrication of having such... Figure 2 , Figure 10 and Figure 11 In the display panel with the structure shown, optionally, in this embodiment of the invention, a first insulating layer 61 can be formed first, followed by the formation of the first opening 610 in the first insulating layer 61, and then a color resist 11 can be formed within the first opening 610. Subsequently, a third light-blocking portion 43 and a fourth light-blocking portion 44 can be formed on the side of the color resist 11 away from the substrate 10. Exemplarily, the third light-blocking portion 43 and the fourth light-blocking portion 44 can be made of the same material and formed in the same patterning process. Based on this arrangement, the first opening 610 can be used as a accommodating space for the color resist 11, which helps to improve the accuracy of the position of the color resist 11.

[0095] like Figure 2 , Figure 9 and Figure 10 As shown, the array substrate 1 further includes a second insulating layer 62, which is located on the side of the third light-blocking portion 43 and the fourth light-blocking portion 44 away from the substrate 10, and covers the third light-blocking portion 43 and the fourth light-blocking portion 44. Exemplarily, both the first insulating layer 61 and the second insulating layer 62 comprise a transparent organic material. Optionally, both the first insulating layer 61 and the second insulating layer 62 include a planarization layer. By configuring the second insulating layer 62 to include a planarization layer, the flatness of the surface of the second insulating layer 62 can be improved in this embodiment of the invention. Figure 2As shown, in this embodiment of the invention, the first semiconductor layer 133 can be disposed on the side of the second insulating layer 62 away from the substrate 10, thereby ensuring the yield of the fabricated first semiconductor layer 133. Alternatively, as... Figure 10 As shown, in this embodiment of the invention, the first gate 130 can be disposed on the side of the second insulating layer 62 away from the substrate 10, thereby ensuring the yield of the fabricated first gate 130 and the gate line disposed on the same layer as the first gate 130. Alternatively, as... Figure 11 As shown, in this embodiment of the invention, the pixel electrode 12 can be disposed on the side of the second insulating layer 62 away from the substrate 10, thereby ensuring the yield of the pixel electrode 12.

[0096] Moreover, while ensuring the flatness of the surface of the second insulating layer 62, the joint arrangement of the first insulating layer 61 and the second insulating layer 62 can avoid the need for a single-layer planarization layer with a large thickness, which is beneficial to improving the preparation yield of the first insulating layer 61 and the second insulating layer 62.

[0097] Furthermore, by placing the third light-blocking part 43 and the fourth light-blocking part 44 between the first insulating layer 61 and the second insulating layer 62, the embodiment of the present invention can avoid light leakage while also preventing the arrangement of the third light-blocking part 43 and the fourth light-blocking part 44 from affecting the flatness of the corresponding positions.

[0098] Optionally, embodiments of the present invention may also make the third light-blocking portion 43 and / or the fourth light-blocking portion 44 metal. Compared with resin materials, metal has better light-blocking performance. By making at least one of the third light-blocking portion 43 and / or the fourth light-blocking portion 44 include metal, embodiments of the present invention can reduce the thickness and width of the third light-blocking portion 43 and / or the fourth light-blocking portion 44 while ensuring the light-blocking performance of the third light-blocking portion 43 and / or the fourth light-blocking portion 44. Exemplarily, the metal includes a metal material with relatively low reflectivity to reduce visible reflection. Optionally, the metal includes at least one of molybdenum, chromium, aluminum, titanium, and copper, or at least one of the metal oxides and metal nitrides corresponding to molybdenum, chromium, aluminum, titanium, and copper.

[0099] For example, such as Figure 2 and Figure 10 As shown, in this embodiment of the invention, the orthographic projection of the channel region 1330 of the first semiconductor layer 133 onto the plane of the substrate 10 overlaps with the orthographic projection of the third light-blocking portion 43 onto the plane of the substrate. Based on this arrangement, the third light-blocking portion 43 can block the light emitted from the backlight module from illuminating the channel region 1330, thus ensuring the accurate activation of the first transistor 13.

[0100] For example, in embodiments of the present invention, the fourth light-blocking portion 44 may include metal and be grounded. For example, as... Figure 2 , Figure 10 and Figure 11 As shown, the array substrate 1 includes a ground portion 9, and the fourth light-blocking portion 44 is electrically connected to the ground portion 9. In this embodiment of the invention, by grounding the fourth light-blocking portion 44, the thickness of the fourth light-blocking portion 44 can be reduced, thereby weakening the coupling interference between the fourth light-blocking portion 44 and other conductive structures located in the non-display area NA.

[0101] Optional, such as Figure 2 , Figure 10 and Figure 11 As shown, in this embodiment of the invention, a second opening 440 located in the non-display area NA can also be provided in the fourth light-blocking part 44. The second opening 440 can reduce the overlap area between the fourth light-blocking part 44 and other conductive structures located in the non-display area NA, thereby reducing the coupling interference between the fourth light-blocking part 44 and other conductive structures located in the non-display area NA.

[0102] For example, such as Figure 2 , Figure 10 and Figure 11 As shown, the non-display area NA also includes a fifth light-blocking portion 45, which at least partially overlaps with the second opening 440 along a direction perpendicular to the plane of the substrate 10. The provision of the fifth light-blocking portion 45 can prevent light leakage from the non-display area NA at the second opening 440.

[0103] Optionally, in embodiments of the present invention, the fifth light-blocking portion 45 may be disposed on the side of the second opening 440 near the substrate 10. For example, as Figure 2 and Figure 10 As shown, the fifth light-blocking portion 45 can be disposed on the fifth conductive layer M5. Alternatively, as... Figure 11 As shown, the fifth light-blocking part 45 can be disposed on the second conductive layer M2.

[0104] Alternatively, in this embodiment of the invention, the fifth light-blocking part 45 may be disposed on the side of the second opening 440 away from the substrate 10.

[0105] For example, such as Figure 2 , Figure 10 and Figure 11As shown, the non-display area NA includes a peripheral circuit area NA1 and a common trace area NA2; the peripheral circuit area NA1 includes the aforementioned shift register unit, which includes the second transistor 14. The common trace area NA2 includes the aforementioned common connection line 52. In this embodiment of the invention, the aforementioned second opening 440 can be located in the common trace area NA2. Compared with the peripheral circuit area NA1, the common trace area NA2 has relatively fewer conductive structures. By placing the second opening 440 in the common trace area NA2, this embodiment of the invention reduces the coupling interference between the fourth light-blocking part 44 and other conductive structures, and makes it easier to place a fifth light-blocking part 45 in the common trace area NA2 that does not interfere with the existing conductive structures.

[0106] For example, such as Figure 2 and Figure 10 As shown, in this embodiment of the invention, the common connection line 52 can be located in the second conductive layer M2, and the fifth light-blocking part 45 can be located in the fifth conductive layer M5. It can also be located in the first conductive layer M1 or the fifth conductive layer M5.

[0107] Or, such as Figure 11 As shown, in this embodiment of the invention, the common connection line 52 can be located in the fourth conductive layer M4, and the fifth light-blocking part 45 can be located in the second conductive layer M2.

[0108] Optional, such as Figure 11 As shown, in this embodiment of the invention, the fifth light-blocking part 45 can be located between the common electrode 51 and the common connection line 52, and the fifth light-blocking part 45 can be electrically connected to the common electrode 51 and the common connection line 52. This arrangement allows the fifth light-blocking part 45 to not only block light emission and prevent light leakage in the non-display area (NA), but also to electrically connect the common electrode 51 and the common connection line 52. This eliminates the need for separate components to prevent light leakage in the non-display area (NA) and to electrically connect the common electrode 51 and the common connection line 52, simplifying the structure and manufacturing process of the display panel.

[0109] For example, such as Figure 11 and Figure 12 As shown, in this embodiment of the invention, the color resist 11 can be located between the pixel electrode 12 and the first semiconductor layer 133, and the pixel electrode 12 and the first semiconductor layer 133 can be electrically connected through the fifth connection portion 15. At least a portion of the fifth connection portion 15 is located within the fifth connection hole K5, and the fifth connection hole K5 penetrates the color resist 11.

[0110] For example, such as Figure 12As shown, the array substrate 1 further includes a sixth light-blocking portion 46 and a seventh light-blocking portion 47. The sixth light-blocking portion 46 is located in the display area AA and includes a third opening 460, within which at least a portion of the color resist 11 is located. The seventh light-blocking portion 47 is located in the non-display area NA. Exemplarily, the sixth light-blocking portion 46 and the seventh light-blocking portion 47 include light-absorbing materials; optionally, the light-absorbing material includes a light-shielding resin.

[0111] In this embodiment of the invention, the sixth light-blocking portion 46 and the seventh light-blocking portion 47 can be reused as a planarization layer. Optionally, the planarization layer can be... Figure 2 , Figure 10 and Figure 11 The first insulating layer 61 is located in the display panel. This arrangement simplifies the film structure within the display panel, reduces the thickness of the display panel, and simplifies the manufacturing process of the display panel.

[0112] Optionally, the sixth light-blocking part 46 and the seventh light-blocking part 47 can be made of the same material and formed in the same patterning process.

[0113] For example, such as Figure 1 , Figure 2 , Figure 3 , Figure 10 , Figure 11 and Figure 12 As shown, the display panel also includes a cover plate 6, a frame adhesive 7, and a support portion 8. When assembling the array substrate 1 and the cover plate 6, based on the method provided in this embodiment of the invention, the cover plate 6 and the color resist 11 are set separately, thus reducing the alignment accuracy requirements of the array substrate 1 and the cover plate 6.

[0114] Optional, such as Figure 1 , Figure 2 , Figure 3 and Figure 10 As shown, the support portion 8 is located between the cover plate 6 and the array substrate 1; the orthographic projection of the support portion 8 onto the plane of the substrate 10 at least partially overlaps with the orthographic projection of the first transistor 13 onto the plane of the substrate 10. After the array substrate 1 and the cover plate 6 are assembled, the support portion 8 is used to maintain the cell thickness between the array substrate 1 and the cover plate 6. By setting the orthographic projection of the support portion 8 onto the plane of the substrate 10 and the orthographic projection of the first transistor 13 onto the plane of the substrate 10 to at least partially overlap, this embodiment of the invention can prevent the support portion 8 from affecting the deflection of the liquid crystal in the sub-pixel aperture area, thus ensuring the display effect of the display panel.

[0115] For example, pixel electrode 12 and common electrode 51 include transparent conductive oxide, which includes ITO or IZO.

[0116] It should be noted that, Figure 1 , Figure 2 , Figure 3 , Figure 8 , Figure 9 and Figure 10 The pixel electrode 12 shown is located on the side of the common electrode 51 closer to the substrate 10, which is merely an illustration. This embodiment of the invention does not limit the relative position and shape of the pixel electrode 12 and the common electrode 51. For example, this embodiment of the invention can design the pixel electrode 12 and the common electrode 51 into architectures corresponding to different display modes according to different needs. Exemplary display modes include any one of the following: Advanced Super Dimension Switch (ADS) mode, High Advanced Super Dimension Switch (HADS) display mode, Twisted Nematic (TN) display mode, In Plane Switching (IPS), and Fringe Field Switching (FFS) display mode.

[0117] Optional, such as Figure 1 , Figure 3 , Figure 5 , Figure 9 , Figure 11 and Figure 12 As shown, the array substrate 1 also includes a first protective layer LS1. The orthographic projection of the first protective layer LS1 onto the plane of the substrate 10 overlaps with the orthographic projection of the channel region 1330 of the first semiconductor layer 133 onto the plane of the substrate 10. The first protective layer LS1 is located on the side of the first semiconductor layer 133 closer to the substrate 10. The first protective layer LS1 can absorb or reflect light from the back side of the display panel that is incident on the first semiconductor layer 133, so as to prevent light from the back side from illuminating the channel region 1330 of the first semiconductor layer 133, thus ensuring the accurate turning on or off of the first transistor 13.

[0118] For example, such as Figure 11 and Figure 12 As shown, in this embodiment of the invention, the first light-shielding layer LS1 and the second gate 140 can be disposed in the same layer on the fourth conductive layer M4.

[0119] Optional, such as Figure 1 , Figure 2 , Figure 3 , Figure 10 , Figure 11 and Figure 12As shown, the array substrate 1 also includes a second protective layer LS2. The orthographic projection of the second protective layer LS2 onto the plane of the substrate 10 overlaps with the orthographic projection of the channel region of the second semiconductor layer 143 onto the plane of the substrate 10. The second protective layer LS2 is located on the side of the second semiconductor layer 143 closest to the substrate 10. The second protective layer LS2 can absorb or reflect light from the back side of the display panel that is incident on the second semiconductor layer 143, thereby preventing light from the back side from illuminating the channel region of the second semiconductor layer 143 and ensuring the accurate turn-on of the second transistor 14.

[0120] Optional, such as Figure 1 and Figure 3 As shown, in this embodiment of the invention, the first protective layer LS1 and the second protective layer LS2 can be disposed in the same layer.

[0121] This invention also provides a display device, such as... Figure 13 As shown, Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 13 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, The array substrate includes a substrate and has a display area, the display area including a color resist, a pixel electrode and a first transistor located on the same side of the substrate; The first transistor includes a first semiconductor layer; wherein, Along a direction perpendicular to the plane of the substrate, the color resist is located between the first semiconductor and the pixel electrode, and the first semiconductor layer and the pixel electrode are electrically connected through a first connection portion; the first connection portion includes a first sub-connection portion located within a first connection hole, and the orthographic projection of the first sub-connection portion onto the plane of the substrate and the orthographic projection of the color resist onto the plane of the substrate do not overlap; along a direction parallel to the plane of the substrate, the first sub-connection portion and the color resist at least partially overlap; The first connecting portion further includes a first connecting electrode; The array substrate also includes a first light-blocking portion located in the display area. The first light-blocking portion includes a first sub-light-blocking portion extending along a first direction, the first sub-light-blocking portion being located between two adjacent color filters in a second direction; the first direction and the second direction intersect; along a direction perpendicular to the plane of the substrate, the first connecting electrode does not overlap with the first sub-light-blocking portion. The array substrate includes a first film layer, which includes a first part and a second part that are mutually insulated from each other. The first part includes a first sub-light blocking part, and the second part includes the first connecting electrode. The first light-blocking portion further includes a second sub-light-blocking portion extending along the second direction; the second sub-light-blocking portion is located between two adjacent color filters in the first direction; Along a direction perpendicular to the plane of the substrate, the first connecting electrode and the second sub-light blocking part at least partially overlap.

2. The display panel according to claim 1, characterized in that, The first connection portion further includes a second sub-connection portion located within the second connection hole; along a direction perpendicular to the plane of the substrate, the first connection electrode is located between the first connection hole and the second connection hole, the first sub-connection portion is electrically connected to the first connection electrode and the pixel electrode; the second sub-connection portion is electrically connected to the first connection electrode and the first semiconductor layer.

3. The display panel according to claim 1, characterized in that, The second sub-light-blocking section is electrically connected to the source or drain of the first transistor, and the second sub-light-blocking section is used to provide data signals to the first transistor.

4. The display panel according to claim 1, characterized in that, The second sub-light-blocking portion is located between the first connecting electrode and the first semiconductor layer; The second sub-blocking portion includes a first sub-hole, and the orthographic projection of the first connecting electrode onto the plane of the substrate at least partially overlaps with the first sub-hole.

5. The display panel according to claim 1, characterized in that, The array substrate further includes a non-display area, which includes a second light-blocking portion; the second light-blocking portion includes a third sub-light-blocking portion, which includes a light-absorbing material. The array substrate further includes a common electrode and a common connection line located in the non-display area; the common electrode and the common connection line are electrically connected through a second connection portion; The second connection portion includes a third sub-connection portion located within the third connection hole. The orthographic projection of the third sub-connection portion onto the plane of the substrate and the orthographic projection of the third sub-light blocking portion onto the plane of the substrate do not overlap. Along a direction parallel to the plane of the substrate, the third sub-connection portion and the third sub-light blocking portion at least partially overlap.

6. The display panel according to claim 5, characterized in that, The second connection portion further includes a second connection electrode that electrically connects the common connection line and the third sub-connection portion, the second connection electrode being located between the third connection hole and the common connection line.

7. The display panel according to claim 6, characterized in that, The second connecting electrode is in the same layer as the first connecting electrode.

8. The display panel according to claim 6, characterized in that, The second light-blocking part further includes a fourth sub-light-blocking part, which includes the second connecting electrode.

9. The display panel according to claim 1, characterized in that, The display area further includes a sixth light-blocking portion, at least a portion of which is located between two adjacent color resists; The array substrate also includes a non-display area, which includes a seventh light-blocking portion; The sixth and seventh light-blocking portions include light-absorbing materials, and the sixth and seventh light-blocking portions reuse the planarization layer in the array substrate; The sixth light-blocking section includes a third opening, and at least a portion of the color resist is located within the third opening.

10. The display panel according to claim 1, characterized in that, The first semiconductor layer comprises a metal oxide.

11. The display panel according to claim 1, characterized in that, It also includes a liquid crystal layer located on the side of the pixel electrode away from the substrate.

12. The display panel according to claim 1, characterized in that, The display area also includes a cover plate and a support portion, wherein the support portion is located between the cover plate and the array substrate; The orthographic projection of the support portion onto the plane of the substrate at least partially overlaps with the orthographic projection of the first transistor onto the plane of the substrate.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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