Parallel fault simulation method, system and medium for heterogeneous computing

Abstract

The present invention discloses a parallel fault simulation method, system and medium for heterogeneous computing, the method includes obtaining device parameters of multiple heterogeneous fault processors and a first fault set and a test vector set of a digital circuit; determining the fault simulation mode of each fault processor; assigning a corresponding fault group to each fault processor, and performing fault simulation on the corresponding circuit netlist through different fault processors according to the fault simulation mode and the fault group under the current test vector group, and updating the first fault set and the second fault set; returning to the step of assigning the fault group when the first fault set is not empty, otherwise updating the test vector set and the first fault set; terminating the simulation when the second fault set is empty, otherwise returning to the step of obtaining the current test vector set; terminating the simulation when the test vector set is empty. The present invention realizes parallel fault simulation of heterogeneous architecture, overcomes the problems of data competition and storage capacity constraints during fault simulation, and improves the resource utilization rate and fault simulation performance of the processor.

Description

Technical Field

[0001] The present invention relates to the field of digital circuit technology, and in particular to a parallel fault simulation method, system and medium for heterogeneous computing. Background Art

[0002] Fault simulation is an important part of the test pattern generation system (ATPG) and chip reliability analysis, and is a fundamental and critical issue in the field of chip testing. Most of the existing parallel fault simulation technologies are based on the homogeneous parallel computing of many-core processors. The most representative one is the data parallel fault simulation solution based on many-core processors proposed by Siemens and others. It improves the performance of fault simulation by improving the performance of single-threaded simulation of single faults and using many-core processors to implement multi-threaded fault simulation.

[0003] Although the performance of fault simulation through single thread in homogeneous parallel computing is constantly improving, the memory required for fault simulation usually increases linearly with the number of threads, and the scale of digital circuits is constantly expanding, which makes it difficult for the memory available in the processor to meet the memory requirements of fault simulation, and frequent memory space exchange will greatly inhibit the performance of fault simulation. If we only focus on improving the performance of single thread in homogeneous parallel computing, it will be difficult to improve the performance of multi-thread synchronously.

[0004] Compared with parallel computing that relies solely on multi-core processors, heterogeneous computing can obtain high-performance computing power from different types of chips more economically and efficiently. If the memory of heterogeneous devices can be reasonably allocated, the memory requirements of fault simulation can be met to a certain extent, and its application potential is huge. Other commonly used computing devices include general-purpose graphics processing units (GPGPUs). Their advantage is that the number of computing cores is much larger than that of multi-core processors, but their disadvantages are that the single-core performance is relatively weak and the memory is relatively limited. More than a decade ago, general-purpose graphics processors were proposed for fault simulation, but their memory is small, and it is necessary to explore suitable memory sharing fault simulation methods to give full play to their advantages. The current related parallel fault simulation technologies have the following defects:

[0005] On the one hand, existing mature parallel fault simulation technologies are all implemented based on homogeneous parallel computing of multi-core processors. However, homogeneous parallel computing cannot effectively utilize other types of processors, which wastes the high-performance computing power of other types of processors. The efficiency of fault simulation needs to be improved.

[0006] On the other hand, other types of processors such as general-purpose graphics processors and accelerator cards have smaller memories. When they are used for parallel fault simulation, problems such as memory explosion will occur. Moreover, they are prone to data competition and storage conflicts between threads when performing parallel reading and writing of shared memory. The data competition problem causes some currently simulated faults to be unable to be passed to the lower layer. These faults that cannot be passed to the lower layer need to be re-simulated, resulting in reduced fault simulation performance; and the storage conflict problem will lead to frequent data exchanges, thereby offsetting the computing power advantage of the graphics processor. Summary of the invention

[0007] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0008] To this end, an object of the present invention is to provide a parallel fault simulation method, system and medium for heterogeneous computing.

[0009] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0010] On the one hand, an embodiment of the present invention provides a parallel fault simulation method for heterogeneous computing, comprising the following steps:

[0011] Acquire device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated;

[0012] The multiple fault processors include multiple first processors and multiple second processors, the first processors and the second processors are heterogeneous, and the first fault set includes multiple faults to be simulated and their numbers;

[0013] Determine the fault simulation mode of each fault processor according to the device parameters of each fault processor;

[0014] Wherein, the fault simulation mode includes any one of the first simulation mode or the second simulation mode;

[0015] Determining whether the test vector set contains at least one test vector group;

[0016] When the test vector set has at least one test vector group, a current test vector group is obtained from the test vector set, multiple circuit netlists of the digital circuit are initialized to a fault-free state, a corresponding fault group is assigned to each fault processor according to the device parameters of each fault processor, and under the current test vector group, fault simulation is performed on multiple circuit netlists according to the fault simulation mode of each fault processor and the assigned fault group, and the first fault set and the second fault set are updated;

[0017] Determine whether the first fault set is an empty set; if not, return to the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor; if so, delete the current test vector group from the test vector set, select the next test vector group as the current test vector group, and when the second fault set is not empty, obtain the second fault set as the first fault set, and return to the step of determining whether the test vector set has at least one test vector group;

[0018] When the test vector set or the second fault set is an empty set, the fault simulation result of the digital circuit is output.

[0019] On the other hand, an embodiment of the present invention further provides a parallel fault simulation system for heterogeneous computing, including:

[0020] An acquisition module, used to acquire device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated; wherein the plurality of fault processors include a plurality of first processors and a plurality of second processors, the first processors and the second processors are heterogeneous, and the first fault set includes a plurality of faults to be simulated and their numbers;

[0021] A first processing module, used to determine a fault simulation mode of each fault processor according to a device parameter of each fault processor; wherein the fault simulation mode includes any one of a first simulation mode or a second simulation mode;

[0022] A first judging module, used to judge whether there is at least one test vector group in the test vector set;

[0023] A second processing module is used for obtaining a current test vector group from the test vector set when there is at least one test vector group in the test vector set, initializing multiple circuit netlists of the digital circuit to a fault-free state, assigning a corresponding fault group to each fault processor according to a device parameter of each fault processor, performing fault simulation on multiple circuit netlists according to a fault simulation mode of each fault processor and the assigned fault group under the current test vector group, and updating the first fault set and the second fault set;

[0024] A second judgment module, used to judge whether the first fault set is an empty set;

[0025] A third processing module is used for, when the first fault set is not empty, returning to the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor; when the first fault set is an empty set, deleting the current test vector group from the test vector set, and selecting the next test vector group as the current test vector group;

[0026] A third judgment module is used to judge whether the second fault set is an empty set;

[0027] A fourth processing module, configured to obtain the second fault set as the first fault set when the second fault set is not empty, and return to the step of determining whether the test vector set contains at least one test vector group;

[0028] An end module is used to output a fault simulation result of the digital circuit when the test vector set or the second fault set is an empty set.

[0029] On the other hand, an embodiment of the present invention provides a storage medium storing a program executable by a processor, wherein the program executable by the processor is used to implement the above-mentioned parallel fault simulation method for heterogeneous computing when executed by the processor.

[0030] The beneficial effects of the present invention are: providing a parallel fault simulation method, system and medium for heterogeneous computing, which maximizes the use of the memory and computing power of each computing device for multi-threaded parallel fault simulation through the collaborative work of computing devices with heterogeneous architectures, and can break through the data competition and storage capacity constraints that occur when computing devices such as general-purpose image processors perform fault simulations. It effectively solves the problems of large memory overhead and insufficient utilization of high-performance computing power in the prior art that only relies on homogeneous parallel computing to handle fault simulation processes, and greatly improves resource utilization and fault simulation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a flow chart of a parallel fault simulation method for heterogeneous computing provided by the present invention;

[0032] Figure 2 is a flow chart of a distribution fault simulation method provided by the present invention;

[0033] Figure 3 is a schematic diagram of FFR provided by the present invention;

[0034] Figure 4 is a schematic diagram of an FFR directed graph provided by the present invention;

[0035] Figure 5 It is a schematic diagram of the FFR transmission domain provided by the present invention;

[0036] Figure 6 is another schematic diagram of the FFR transmission domain provided by the present invention;

[0037] Figure 7 is a flow chart of heterogeneous fault simulation provided by the present invention;

[0038] Figure 8 is a schematic diagram of heterogeneous fault simulation provided by the present invention;

[0039] Fig. 9 is an application diagram of performing parallel fault simulation using the second simulation method provided by the present invention;

[0040] Fig.10 It is a schematic diagram of the FFR directed graph and the FFR transmission domain provided by the present invention;

[0041] Fig.11 It is a schematic diagram of an array identifier of an event management mechanism for parallel fault simulation provided by the present invention. DETAILED DESCRIPTION

[0042] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. The described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0043] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0044] 1) Many-core processors are a special type of multi-core processor designed for highly parallel processing, containing many simpler, independent processor cores (from dozens of cores to thousands or more). Many-core processors differ from multi-core processors in that they are optimized from the beginning for a higher degree of explicit parallelism and higher throughput (or lower power consumption), but at the expense of latency and lower single-threaded performance. Many-core processors are widely used in embedded computers and high-performance computing.

[0045] 2) General-purpose computing on graphics processing units (GPGPU) is a type of graphics processor that uses graphics processing tasks to calculate general computing tasks that were originally handled by the central processing unit (CPU). These general-purpose calculations often have nothing to do with graphics processing. Due to the powerful parallel processing capabilities and programmable pipelines of modern graphics processors, stream processors can process non-graphic data, especially when facing single instruction stream multiple data streams (SIMD) and the amount of data processing operations is far greater than the needs of data scheduling and transmission, general-purpose graphics processors greatly surpass traditional central processing unit applications in performance.

[0046] 3) Parallel Pattern Single Fault Simulation (PPSFP) is a parallel fault simulation method. For a host with a data width of several bits, the signal values ​​of several test vector groups are packaged into a data word. For fault-free or faulty circuits, several test vectors can be simulated in parallel using bit logic operations. It is particularly effective for combinational circuits or full-scan sequential circuits.

[0047] In view of the defects and problems existing in the related technologies, the embodiments of the present invention propose a parallel fault simulation method, system and medium for heterogeneous computing, and adopt the idea of ​​PPSFP and the fault simulation strategy of competition inclusion and dimensional fusion to realize parallel fault simulation under heterogeneous architecture. The faults that can be simulated include but are not limited to single fixed faults, bridging faults, jump delay faults, etc., breaking through the bottleneck of data competition and laying a solid foundation for realizing efficient parallel fault simulation under heterogeneous architecture.

[0048] The parallel fault simulation method for heterogeneous computing provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] The method in the embodiment of the present invention can be applied to a terminal or a server, or can be software running in a terminal or a server. The terminal can be a tablet computer, a laptop computer, a desktop computer, etc., but is not limited thereto. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0050] Reference Figure 1 , Figure 1 : is a flow chart of a parallel fault simulation method for heterogeneous computing provided by the present invention, and the method may include but is not limited to the following steps:

[0051] S100, obtaining device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated.

[0052] It should be noted that the multiple fault processors include multiple first processors and multiple second processors, the first processors and the second processors are heterogeneous, that is, the architectures of the first processor and the second processor are different, and the device parameters of each fault processor may include but are not limited to the available memory information and the number of threads of the fault processor.

[0053] Optionally, the first processor is a many-core processor.

[0054] Optionally, the second processor may include but is not limited to a general-purpose graphics processor, an accelerator card, or other processors other than a multi-core processor. The processor referred to by the second processor may be selected according to actual conditions, and the present invention does not specifically limit this.

[0055] In addition, the first fault set may include but is not limited to multiple faults to be simulated and their numbers, and the test vector set may include but is not limited to multiple test vector groups, each test vector group includes at least one test vector, and the test vector refers to the logical value input into the digital circuit during fault detection, such as "01111011", "10110000", etc.

[0056] The embodiment of the present invention adopts the idea of ​​PPSFP to perform fault simulation, and each time multiple vectors are used to simulate a fault in parallel, and multiple vectors are used to simulate the next fault in parallel after the current fault is detected. If the byte length of the processor is W, then one fault simulation can use W vectors to simulate or detect a fault in parallel. In the embodiment of the present invention, these W vectors are called a test vector group.

[0057] S200, determining a fault simulation mode of each fault processor according to device parameters of each fault processor.

[0058] It should be noted that the fault simulation method includes any one of the first simulation method and the second simulation method.

[0059] In this step, the available memory information and the number of threads of each fault processor are used to determine the method for each fault processor to process the fault simulation task.

[0060] S300, determine whether the test vector set contains at least one test vector group. If yes, go to step S310; if no, output the fault simulation result of the digital circuit and end the fault simulation.

[0061] In this step, when the test vector set is an empty set, it means that there are no more test vector groups available for fault detection, and the fault detection is terminated at this time.

[0062] S310, obtaining a current test vector group from a test vector set, and initializing multiple circuit netlists of a digital circuit to a fault-free state.

[0063] S320, assign a corresponding fault group to each fault processor according to the device parameters of each fault processor, and under the current test vector group, perform fault simulation on multiple circuit netlists according to the fault simulation method of each fault processor and the assigned fault group, and update the first fault set and the second fault set.

[0064] In this step, first, the multiple faults to be simulated that are most likely to cause conflicts in the first fault set are assigned to the fault processors using the first simulation method, and based on the FFR directed graph of the digital circuit, the remaining faults to be simulated in the first fault set are assigned to the fault processors using the second simulation method, so that each fault processor is assigned a corresponding fault group. Then, a group of faults is inserted into each circuit netlist; then, fault simulation is performed on multiple circuit netlists according to the fault simulation method of each fault processor and the assigned fault group, and then the first fault set and the second fault set are updated.

[0065] S330, determine whether the first fault set is an empty set; if not, return to step S320; if so, delete the current test vector group from the test vector set, select the next test vector group as the current test vector group, and enter step S340;

[0066] S340, determine whether the second fault set is an empty set; if so, output the fault simulation result of the digital circuit and end the fault simulation; if not, obtain the second fault set as the first fault set and return to step S300.

[0067] In the above steps, when the first fault set is an empty set, it means that the current test vector group has completed the simulation or detection of all faults to be simulated. At this time, the current test vector group is deleted from the test vector set, and the next test vector group is selected as the current test vector group. Afterwards, it is determined whether the second fault set is an empty set. When the second fault set is an empty set, it means that all faults to be simulated are in a completed state, and the fault simulation of the digital circuit to be simulated has been completed. At this time, the fault simulation result of the digital circuit is output; when the second fault set is not an empty set, it means that there are still faults to be simulated that have not been simulated. At this time, the first fault set is equal to the second fault set, the second fault set is cleared, and then the step S300 is returned. In addition, when the first fault set is not empty, it means that there are still faults to be simulated under the current test vector group that have not been simulated. At this time, the step S320 is returned.

[0068] In some embodiments of the present invention, in step S100, the step of obtaining device parameters of multiple fault processors and a first fault set and a test vector set of a digital circuit to be simulated mainly includes:

[0069] S110, obtaining a plurality of to-be-simulated faults of the digital circuit and their numbers as a first fault set of the digital circuit, and simultaneously obtaining a plurality of test vector groups of the digital circuit as a test vector set of the digital circuit.

[0070] In this step, first, the circuit level of the digital circuit is determined according to its structure. The smaller the circuit level where the fault is located, the greater the level distance between the fault to be simulated and the output end of the digital circuit. Then, multiple faults to be simulated are numbered according to the size of the circuit level. The numbering rule is that the lower the circuit level where the fault is located, the smaller the fault number; the higher the circuit level where the fault is located, the larger the fault number.

[0071] S120, obtaining a plurality of first processors and a plurality of second processors as a plurality of fault processors, and using available memory information and the number of threads of the fault processors as device parameters of the fault processors.

[0072] In some embodiments of the present invention, reference Figure 2 , Figure 2 1 is a flow chart of the fault simulation mode of the present invention. In step S200, the steps of determining the fault simulation mode of each fault processor according to the device parameters of each fault processor mainly include:

[0073] S210, determine whether the faulty processor is the first processor; if so, go to step S220; if not, go to step S240.

[0074] In this step, the type of the faulty processor is determined, that is, whether the faulty processor is a multi-core processor, so as to select an appropriate simulation method to perform fault simulation according to the type of the processor.

[0075] S220, calculating the fault simulation memory of the fault processor according to the device parameters of the fault processor.

[0076] In this step, the fault simulation memory of the many-core processor is calculated according to the available memory information and the number of threads of the many-core processor.

[0077] S230, determining whether the fault simulation memory of the fault processor satisfies the first memory. If so, adopting the first simulation method as the fault simulation method of the fault processor; if not, adopting the second simulation method as the fault simulation method of the fault processor.

[0078] It should be noted that the first memory is defined as the memory required for performing fault simulation using the first simulation method.

[0079] In this step, when the fault simulation memory of the multi-core processor is greater than or equal to the first memory, it means that the fault simulation memory of the fault processor satisfies the first memory, and the first simulation method is selected as the fault simulation method of the multi-core processor, and the first simulation method is a data parallel fault simulation strategy. When the fault simulation memory of the multi-core processor is less than the first memory, it means that the fault simulation memory of the fault processor does not satisfy the first memory, and the second simulation method is selected as the fault simulation method of the multi-core processor, and the second simulation method is a fault simulation strategy of competitive inclusion and dimensional fusion. Among them, the data parallel fault simulation strategy and the fault simulation strategy of competitive inclusion and dimensional fusion will be described in detail later.

[0080] S240, calculating a fault simulation memory of the fault processor according to the device parameters of the fault processor.

[0081] In this step, the fault simulation memory of the non-many-core processor is calculated according to the available memory information and the number of threads of the non-many-core processor. It can be understood that the non-many-core processor is a processor other than the many-core processor, which can be a general-purpose graphics processor, or other processors such as a graphics processor, an accelerator card, etc.

[0082] S250, determining whether the fault simulation memory of the fault processor satisfies the second memory. If so, adopting the second simulation mode as the fault simulation mode of the fault processor; if not, treating the fault processor as a fault processor that does not participate in fault simulation.

[0083] It should be noted that the second memory is defined as the memory required for performing fault simulation using the second simulation method.

[0084] In this step, when the fault simulation memory of the non-many-core processor is greater than or equal to the second memory, it means that the fault simulation memory of the non-many-core processor meets the second memory, and the second simulation method is selected as the fault simulation method of the non-many-core processor, and the second simulation method is a fault simulation strategy of competitive inclusion and dimension fusion. When the fault simulation memory of the non-many-core processor is less than the second memory, it means that the current non-many-core processor is not suitable for running the current fault simulation, and the current non-many-core processor is used as a fault processor that does not participate in the fault simulation.

[0085] Furthermore, the information required to be stored for fault simulation using the first simulation method may include but is not limited to circuit netlist information, logic gate simulation values, fault sources, and event-driven management information, and the memory required to store this information is called memory demand. For all faults to be simulated in the same group of faults simulated using the first simulation method, in addition to the circuit netlist being shared by the same group, the logic gate simulation value, fault source, and event-driven management information corresponding to each fault to be simulated need to be stored separately. Therefore, the first memory is determined by the circuit netlist, logic gate simulation value, fault source, and memory demand for event-driven management, as well as the number of threads.

[0086] In addition, the change of fault type will change the memory required for fault simulation. If it is a bridging fault, the memory required for its simulation is basically the same as the memory required for single fixed-type fault simulation. If it is a transition delay fault, the memory that needs to be considered in its simulation also includes the memory required to insert timing devices and the memory required to increase the logic gate simulation value space.

[0087] Exemplarily, when the fault type is a single stuck-at fault, the first memory satisfies:

[0088] First memory = memory requirement of circuit netlist + number of threads × (memory requirement of logic gate simulation value + memory requirement of fault source + memory requirement of event-driven management);

[0089] Among them, the number of threads refers to the number of threads of the fault processor; the circuit netlist information includes the input, output and information of each gate of the circuit and the connection relationship between them. Therefore, the memory requirement of the circuit netlist satisfies: the memory requirement of the circuit netlist = port memory + gate device memory + connection relationship memory. The ports and gate devices need to store identification numbers, types, fan-in connection line information and fan-out connection line information. The connection lines need to store identification numbers, input device information, fan-out number and driver device information; the memory requirement of the logic gate simulation value satisfies: single simulation value memory × number of gates × 2. The single simulation value memory is related to the use of several-value logic simulation. If 4-value logic is used, 2 bits of memory are required. "×2" is because in addition to storing the simulation value with faults, the simulation value without faults is also stored; in addition to recording the fault simulation value, it is also necessary to record the corresponding fault source information. The memory requirement of the fault source satisfies: single fault identification memory × number of gates; event-driven management information stores the gate identification and level identification of the digital circuit. The memory requirement of event-driven management satisfies: gate device identification memory + level identification memory.

[0090] Furthermore, the information required to be stored for fault simulation using the second simulation method may include but is not limited to circuit netlist information, logic gate simulation values, fault sources, and event-driven management information, and the memory required to store this information is called memory demand. For all faults to be simulated in the same group of faults that use the second simulation method for fault simulation, they share circuit netlist information, logic gate simulation values, fault sources, and event-driven management information. Therefore, the second memory is determined by circuit netlist information, logic gate simulation values, fault sources, and event-driven management information.

[0091] In addition, the change of fault type will change the memory required for fault simulation. If it is a bridging fault, the memory required for its simulation is basically the same as the memory required for single fixed-type fault simulation. If it is a transition delay fault, the memory that needs to be considered in its simulation also includes the memory required to insert timing devices and the memory required to increase the logic gate simulation value space.

[0092] Exemplarily, when the fault type is a single stuck-at fault, the second memory satisfies:

[0093] Second memory = thread coefficient × (memory requirement of circuit netlist + memory requirement of logic gate simulation value + memory requirement of fault source + memory requirement of event-driven management);

[0094] The thread coefficient is defined as a ratio of a memory requirement for fault simulation using the second simulation method to a memory requirement for fault simulation using the first simulation method.

[0095] The selection of fault simulation method is explained by taking the transition delay fault simulation of a typical 20 million gate digital circuit as an example.

[0096] The table below shows the memory requirements for a typical 20 million gate digital circuit for transition delay fault simulation.

[0097]

[0098] Assuming that each multi-core processor uses 32 threads to perform parallel fault simulation simultaneously, the memory required for each multi-core processor to perform data parallel fault simulation is: 1GB+32×(0.32GB×6+200MB)=68.84GB. If the memory of a multi-core processor meets 64.84GB, the multi-core processor adopts the data parallel fault simulation strategy to handle the fault. If the memory of a multi-core processor is less than 64.84GB, the multi-core processor adopts the fault simulation strategy of competitive inclusion and dimension fusion to handle the fault. For the multi-core processor that adopts the fault simulation strategy of competitive inclusion and dimension fusion, the memory required to simulate a group of fault groups is slightly larger than the memory required for a single thread. If the thread coefficient is 1.5, the memory consumed is only 1.5×(1GB+0.32GB×6+200MB)=4.68GB. That is, for other non-many-core processors such as general-purpose graphics processors, if their memory meets 4.68GB, the non-many-core processor adopts the fault simulation strategy of competitive inclusion and dimension fusion to handle the fault, otherwise the non-many-core processor is not suitable for running the current fault simulation.

[0099] In addition, a computing device that selects the fault simulation strategies of competitive inclusion and dimensional fusion can determine whether it can simulate multiple fault groups based on its own memory. For each additional fault group simulation, its memory requirement needs to increase by 1.5×(0.32GB×6+200MB)=3.18GB. The fault simulation memory of a computing device that selects the fault simulation strategies of competitive inclusion and dimensional fusion can determine the number of fault groups that the computing device can execute.

[0100] In some embodiments of the present invention, in step S310, the step of initializing multiple circuit netlists of the digital circuit to a fault-free state mainly includes:

[0101] S311, obtaining a current test vector group from a test vector set, and performing a fault-free simulation on multiple circuit netlists of a digital circuit to be simulated, so as to initialize all circuit netlists to a fault-free state.

[0102] In some embodiments of the present invention, in step S320, the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor mainly includes:

[0103] S321, according to the device parameters of the fault processor using the first simulation method, part of the faults to be simulated in the first fault set are allocated to the fault processor using the first simulation method, and a fault group of the fault processor using the first simulation method is generated, with the unallocated faults to be simulated in the first fault set as the fault set to be allocated.

[0104] In this step, firstly, the fault to be simulated that is most likely to cause fault simulation conflict is selected as the fault group of the fault processor using the first simulation method, wherein the number of faults to be simulated in the fault group of the fault processor using the first simulation method is equal to the number of threads of the fault processor using the first simulation method.

[0105] S322, dividing the digital circuit into a plurality of non-fan-out regions, taking the non-fan-out regions as basic units, and using directed line segments to represent connections and data flows between the non-fan-out regions, thereby constructing an FFR directed graph of the digital circuit.

[0106] In this step, according to the definition of fan-out free network proposed by John P. Hayes and the concept of circuit partitioning proposed by Kurt J. Antreich, the fan-out free region (FFR) of the digital circuit is defined as follows: if a region of the digital circuit has only one output terminal, and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line of the circuit in the region is connected to at most one input of a logic gate, then the circuit region is called a fan-out free region.

[0107] That is, FFR is a circuit area in a digital circuit that has only one output terminal and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line in each non-fan-out area is connected to at most one input terminal of a logic gate.

[0108] For example, refer to Figure 3 , Figure 3 is a schematic diagram of the FFR provided by the present invention. According to the distribution of the fan-out terminal and the logic output terminal, Figure 3 There are seven FFRs in the digital circuit shown, among which the area where logic gates G1 and G4 are located constitutes FFR1, the left area of ​​the fan-out end connected to logic gate G7 forms FFR2, the area where logic gate G2 is located constitutes FFR3, the right area of ​​the fan-out end connected to logic gate G4 (not the area where logic gate G7 is located) constitutes FFR4, the area where logic gate G7 is located constitutes FFR5, the area where logic gates G5, G8 and G9 are located constitutes FFR6, and the area where logic gates G3 and G6 are located constitutes FFR7.

[0109] After dividing the digital circuit into multiple FFRs, the embodiment of the present invention constructs a directed graph of the non-fan-out area of ​​the digital circuit according to the multiple FFRs, and the directed graph of the non-fan-out area is called an FFR directed graph. In the FFR directed graph, FFR is used as a unit, which is represented by a circle, and the connection relationship between different FFRs is represented by a directed line segment, and the arrow of the directed line segment represents the data flow direction between different FFRs.

[0110] For example, refer to Figure 4 , Figure 4 is a schematic diagram of the FFR directed graph provided by the present invention, Figure 4 The FFR directed graph shown corresponds to Figure 3 The no fan-out area distribution shown, Figure 3 The seven FFRs in the figure are represented by circles, and the connection relationship and data flow direction between the seven FFRs are represented by directed lines, thus obtaining the following: Figure 4 The FFR directed graph is shown.

[0111] In addition, the FFR directed graph has a hierarchical structure, with FFRs located in the same column as FFRs of the same FFR level. The greater the distance between the FFR and the output terminal of the digital circuit, the lower the FFR level at which the FFR is located.

[0112] For example, refer to Figure 4 In the FFR directed graph shown, FFR1, FFR2 and FFR3 are located in the same column and are farthest from the output end of the digital circuit, so FFR1, FFR2 and FFR3 are located in the first FFR level, i.e., level 1; while FFR4, FFR5, FFR6 and FFR7 are located in the same column and are closest to the output end of the digital circuit, so FFR4, FFR5, FFR6 and FFR7 are located in the second FFR level, i.e., level 2, thereby making the FFR directed graph have a hierarchical structure.

[0113] S323, allocating multiple to-be-simulated faults in the to-be-allocated fault set to multiple circuit netlists of digital circuits through an FFR directed graph to obtain initial fault groups of the multiple circuit netlists.

[0114] In this step, based on the FFR directed graph, starting from the first layer FFR, m non-overlapping FFR transmission domains containing faults are divided according to the grouping principle. A fault is selected in one FFR transmission domain to form a fault group G. f1 , and then form the fault group G in the same way f2 ~G fk ,According to the priority principle, the priority of each group of faults is set, and then the initial fault groups of multiple circuit netlists are formed.

[0115] It should be noted that, in one embodiment of the present invention, all faults to be simulated in the fault set to be assigned are assigned to the corresponding circuit netlist, but in other embodiments of the present invention, some of the faults to be simulated in the fault set to be assigned are assigned to the corresponding circuit netlist, and there are still some faults to be simulated in the fault set to be assigned that have not been assigned.

[0116] S324, allocating a plurality of initial fault groups to the fault processor using the second simulation method according to device parameters of the fault processor using the second simulation method, thereby generating fault groups corresponding to the fault processor using the second simulation method.

[0117] In this step, corresponding initial fault groups are allocated to the fault processors using the second simulation method according to the number of threads of the fault processors using the second simulation method, wherein the number of faults to be simulated in the fault groups allocated to each fault processor using the second simulation method is equal to the number of threads of each fault processor using the second simulation method, and the number of fault groups allocated to each fault processor using the second simulation method is determined by its fault simulation memory.

[0118] For example, assume that the first fault set of the digital circuit has 2000 faults to be simulated, there are 4 many-core processors and 2 graphics processors, each many-core processor has 32 available threads, each graphics processor has tens of thousands of available threads, the many-core processor uses the first simulation method to perform fault simulation, the graphics processor uses the second simulation method to perform fault simulation, and each graphics processor can handle at most two fault groups. After the previous steps determine the fault simulation method of each fault processor, the multiple faults to be simulated in the first fault set are grouped according to the number of threads of the heterogeneous device. The specific process is as follows:

[0119] First, each many-core processor can handle 32 faults to be simulated, and 4 many-core processors can handle 128 faults to be simulated. Therefore, 128 faults to be simulated that are most likely to cause conflicts are selected from the 2000 faults to be simulated, and corresponding fault groups are assigned to the fault processors using the first simulation method. The number of faults to be simulated in the fault group assigned to each fault processor using the first simulation method is 32.

[0120] Then, the remaining 1872 faults to be simulated in the first fault set are grouped. Based on the FFR directed graph, the 1872 faults to be simulated are divided into 5 initial fault groups. The numbers of faults to be simulated contained in the 5 initial fault groups are 600, 450, 300, 270 and 252 respectively. These 5 initial fault groups are processed by 2 graphics processors.

[0121] Optionally, the initial fault groups are randomly assigned to the corresponding graphics processors according to the maximum number of fault groups that each graphics processor can handle. For example, each graphics processor can handle at most two fault groups, so the first initial fault group and the second initial fault group are randomly assigned to the first graphics processor, and the first graphics processor needs to use 1050 threads to handle these two fault groups; the third initial fault group and the fourth initial fault group are randomly assigned, and the second graphics processor needs to use 570 threads to handle these two fault groups; and the last initial fault group will be simulated in the second round of fault simulation.

[0122] In some embodiments of the present invention, in step S323, for each circuit netlist, a plurality of to-be-simulated faults in the to-be-allocated fault set are allocated to the circuit netlist through the FFR directed graph, and the implementation process of obtaining the initial fault group of the circuit netlist mainly includes the following steps:

[0123] S3231, determine the transmission parameters of the circuit netlist.

[0124] It should be noted that the transmission parameters are pre-set circuit parameters.

[0125] S3232: construct multiple fan-out-free transmission domains of a circuit netlist according to the FFR directed graph and the transmission parameters.

[0126] It should be noted that a transmission domain without fan-out is called an FFR transmission domain, wherein two adjacent FFR transmission domains do not overlap each other, and each FFR transmission domain includes at least one fault to be simulated and at least two FFRs.

[0127] For example, refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of an FFR transmission domain provided by the present invention, wherein a gray triangle represents an FFR transmission domain. Figure 5 Only part of the FFR transmission domain is shown in the figure; the two FFR transmission domains with black dashed lines on the periphery do not overlap each other, and the two FFRs with black solid lines have overlapping domains. FFR1 and FFR4 form one FFR transmission domain, and FFR3 and FFR7 form the second FFR transmission domain. These two FFR transmission domains do not overlap each other. The area formed by FFR8, FFR12 and FFR9 and the area formed by FFR9, FFR13 and FFR10 overlap each other, that is, there is an overlapping domain in these two areas, so only one of these two areas can be an FFR transmission domain.

[0128] S3233, select at least one fault to be simulated from each fan-out-free transmission domain in turn.

[0129] In this step, according to the number of faults to be simulated, non-overlapping FFR transmission domains that meet the number requirement are selected, and a fault to be simulated is selected from each selected FFR transmission domain in turn. However, it should be noted that the number of faults to be simulated cannot be greater than the first value.

[0130] S3234, determining the priority of the selected fault to be simulated according to the number of the selected fault to be simulated, and using the fault to be simulated and its priority as the initial fault group of the circuit netlist.

[0131] It should be noted that each circuit netlist is correspondingly assigned an initial fault group, and the initial fault group includes a plurality of faults to be simulated and their priorities.

[0132] In this step, the priority is related to the fault number. The faults with small numbers are located at a low circuit level, and the path of fault transmission to the output end is often longer. They should be simulated first, so the faults with small numbers have high priority. That is, the priority of the faults with small numbers is higher than the priority of the faults with large numbers. After that, the faults to be simulated and their priorities are used as the initial fault group of the circuit netlist.

[0133] In some embodiments of the present invention, the transmission parameters of the circuit netlist may include but are not limited to the depth and width of the FFR transmission domain included in the circuit netlist, wherein the width and depth of each FFR transmission domain in the circuit netlist are the same.

[0134] More specifically, the depth of the FFR transmission domain refers to the number of FFR layers in the FFR transmission domain. The number of layers refers to the number of FFR levels. FFRs in the same column have the same FFR level, and the lower the FFR level, the greater the distance between the FFR in the FFR transmission domain and the output end of the digital circuit.

[0135] For example, refer to Figure 6 , Figure 6 This is the second schematic diagram of the FFR transmission domain provided by the present invention. In the figure, FFR transmission domain 1 includes two layers of FFR, and FFR transmission domain 2 includes three layers of FFR. Therefore, the depth of FFR transmission domain 1 is 2, and the depth of FFR transmission domain 2 is 3.

[0136] More specifically, the width of the FFR transmission domain refers to the sum of the number of FFRs having only one child node in the FFR transmission domain except the FFR at the bottom of the FFR transmission domain and the number of FFRs at the bottom of the FFR transmission domain.

[0137] For example, refer to Figure 6For FFR transmission domain 1, FFR7 has only one child node, and FFR3 is located at the bottom layer of FFR transmission domain 1, so the width of FFR transmission domain 1 is 2; for FFR transmission 2, FFR4, FFR5, and FFR6 are all located at the bottom layer of the transmission domain, so the width of FFR transmission domain 2 is 3.

[0138] In the embodiment of the present invention, the FFR transmission domain indicates the range in which the output FFR is affected by other FFRs. When the FFR transmission domains where multiple faults are located do not overlap with each other and are in the same FFR layer, these faults will not conflict within their FFR transmission domains during parallel simulation. Although there is still a probability of conflict when these faults are transmitted outside their FFR transmission domains, this probability is extremely small and can be ignored.

[0139] Alternatively, considering that the number of faults that can be successfully transmitted to the output end is limited, for circuits of general size, when the depth of the FFR transmission domain is greater than 4, the probability of conflict caused by parallel simulation of multiple faults will be very low.

[0140] In some embodiments of the present invention, in step S3232, the step of constructing multiple fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters mainly includes:

[0141] According to the hierarchical structure of the FFR directed graph, any fan-out-free area is taken as the output point, the FFR level before the FFR level where the output point is located is taken as the to-be-selected level, the output point and the fan-out-free area in the to-be-selected level that meets the transmission parameters and is connected to the output point are selected as the fan-out-free transmission domain, and then multiple fan-out-free transmission domains of the circuit netlist are constructed.

[0142] In this step, according to the hierarchical structure of the FFR directed graph, take any FFR as the output point, go forward several FFR levels, find all FFRs connected to the output point in the several FFR levels ahead, and then form an FFR transmission domain that meets the preset FFR transmission domain width and depth.

[0143] For example, refer to Figure 5, if the depth and width of the FFR transmission domain are set to 2, and FFR4 is used as the output point, the connected FFR1 is found in the previous FFR level, so FFR1 and FFR4 constitute an FFR transmission domain. From FFR5 as the output point, the connected FFR1 and FFR2 are found in the previous FFR level, so FFR1, FFR2 and FFR5 constitute another FFR transmission domain, and so on, 11 FFR transmission domains can be drawn. However, among these FFR transmission domains, there are overlapping FFR transmission domains, such as the area formed by FFR8, FFR12 and FFR9 and the area formed by FFR9, FFR13 and FFR10 overlap each other, then one of every two overlapping FFR transmission domains is selected and retained, and then multiple non-overlapping FFR transmission domains in the circuit netlist are obtained.

[0144] Again, for example, refer to Figure 6 , if the depth and width of the FFR transmission domain are set to 2, with FFR7 as the output point, FFR3 connected to FFR7 is found in the previous FFR level, thereby forming an FFR transmission domain 1 with a width and depth of 2. For another example, if the width and depth of the FFR transmission domain are set to 3, with FFR12 as the output point, FFR8 and FFR9 connected to FFR12 are found in the previous FFR level, with FFR8 and FFR9 as the output points, FFR4 and FFR5 connected to FFR8 are found in the previous FFR level, and FFR5 and FFR6 connected to FFR9 are found in the previous FFR level, thereby forming an FFR transmission domain 2 with a width and depth of 3.

[0145] In some embodiments of the present invention, in step S3234, a fault group corresponding to each circuit netlist is formed, and the maximum value of the number of faults to be simulated in the fault group, i.e., the first value, is related to the circuit structure and can be calculated by the following calculation formula:

[0146]

[0147] Among them, N (i)FFR represents the number of FFRs in the i-th layer, and the FFR level of the FFR directed graph is but l (i,j) represents the width of the jth FFR transmission domain of the i-th FFR layer, j = 1, 2, 3, ..., N (i+1)FFR ; Indicates the maximum width of the FFR transmission domain in the i-th layer FFR. Take the FFR transmission domain with the largest width in the i-th layer FFR as the denominator and the number of FFRs in the i-th layer as the numerator. The integer is rounded to indicate the minimum number of non-overlapping FFR transmission domains in this layer. FFR transmission domains do not overlap, then for any layer of FFR, there are at least FFR transmission domains do not overlap. That is, for any layer of FFR, there are at least m FFR transmission domains that do not overlap. Based on this, m can be used as the maximum value of the number of faults to be simulated in the fault group, that is, the first value.

[0148] Furthermore, for common circuit structures, the width of the FFR transmission domain increases with its depth rather than strictly increasing, so the above formula can be simplified to the following formula:

[0149]

[0150] Although the simplified formula loses some of the characteristics of the circuit structure and has certain deviations, it can greatly reduce the computational complexity of fault simulation. In addition, multiple experiments can be conducted on a certain type of circuit to correct the parameters. Later, when encountering the same type of circuit, the simplified formula can be directly used and the parameters can be applied, which reduces the computational complexity while ensuring a certain accuracy.

[0151] In some embodiments of the present invention, reference Figure 7 , Figure 7 : is a flowchart of heterogeneous fault simulation provided by the present invention. In step S320, under the current test vector group, fault simulation is performed on multiple circuit netlists according to the fault simulation mode of each fault processor and the assigned fault group, and the steps of updating the first fault set and the second fault set mainly include:

[0152] S325, insert each fault group into the corresponding circuit netlist.

[0153] Specifically, for a circuit netlist that performs fault simulation by a fault processor using a first simulation method, a fault to be simulated in a fault group assigned by the fault processor using the first simulation method is inserted into each circuit netlist. In addition, for a circuit netlist that performs fault simulation by a fault processor using a second simulation method, a group of fault groups assigned by the fault processor using the second simulation method is inserted into each circuit netlist.

[0154] Exemplarily, netlists 1 to m are circuit netlists for fault simulation by a fault processor using a first simulation method. The fault group assigned by the fault processor using the first simulation method is G, and G includes m faults to be simulated. Then, each fault to be simulated in G is inserted into netlists 1 to m in sequence. Netlist 1 is inserted with fault 1 in fault group G, ..., netlist m is inserted with fault m in fault group G, and each netlist is inserted with a fault to be simulated. Netlists m+1 to k are circuit netlists for fault simulation by a fault processor using a second simulation method. The fault group assigned by the fault processor using the second simulation method is G.f(m+1) ~G fk , insert fault group G into netlist m+1 f(m+1) , ..., insert fault group G into netlist k fk .

[0155] It should be emphasized that in other embodiments of the present invention, after the fault group is inserted into the corresponding circuit netlist, there may be some faults to be simulated in the first fault set that are not grouped in the aforementioned steps and do not participate in this round of fault simulation.

[0156] S326, under the current test vector group, perform fault simulation on the digital circuit according to the fault simulation mode of each fault processor and the assigned fault group to obtain the detection status of each fault to be simulated.

[0157] It should be noted that the detection status includes any one of a completed status, an undetectable status or an abandoned status.

[0158] Specifically, if the fault effect caused by a fault can be transmitted to the output end under the test vector, the fault can be detected and it is a completed state; if a fault cannot be transmitted to the output end under the test vector, or it is transmitted to the output end but the fault simulation value is consistent with the correct value, then the fault cannot be detected and it is an undetectable state; if a fault cannot be transmitted to the output end due to the influence of other faults in the group, then the fault is abandoned and it is an abandoned state.

[0159] S327, add the to-be-simulated faults in the first fault set that are in the undetectable state to the second fault set, delete the to-be-simulated faults in the first fault set that are in the completed state and the undetectable state, and retain the to-be-simulated faults in the first fault set that are in the abandoned state, so as to update the first fault set and the second fault set.

[0160] In this step, the updated first fault set includes the fault groups that have not been inserted into the circuit netlist and the faults to be simulated that are in the abandoned state, and the second fault set includes the faults to be simulated that are in the undetectable state.

[0161] S328, initializing each circuit netlist to a fault-free state under the current test vector group.

[0162] In this step, under the current measurement vector group, each netlist fault point is restored to a fault-free value, and then a fault-free simulation is performed on each netlist, thereby initializing each circuit netlist to a fault-free state.

[0163] Further, refer to Figure 7 and Figure 8 , Figure 8is a schematic diagram of heterogeneous fault simulation provided by the present invention. In step S326, the steps of performing fault simulation on the digital circuit according to the fault simulation mode of each fault processor and the assigned fault group mainly include:

[0164] The fault simulation is performed in parallel on the multiple to-be-simulated faults in the assigned fault group by using multiple threads of the fault processor in the first simulation mode.

[0165] It should be noted that each thread of the fault processor using the first simulation mode is used to simulate at most one fault to be simulated.

[0166] In this step, each thread of the computing device using the data parallel fault simulation strategy takes out a fault to be simulated from the fault group for fault simulation. The data parallel fault simulation strategy refers to using one thread to perform a fault simulation of a fault to be simulated, and the fault simulation of each thread is performed in parallel. If the fault to be simulated can be detected, after all threads have completed this fault simulation, check whether there are any faults to be simulated in the first fault set. If the fault to be simulated cannot be detected, put the undetected fault to be simulated into the second fault set so that the next vector group can detect it.

[0167] Furthermore, in step S326, the step of performing fault simulation on the digital circuit according to the fault simulation mode of each fault processor and the assigned fault group also includes:

[0168] The fault simulation is performed in parallel on all the faults to be simulated in the assigned fault group by using multiple threads of the fault processor using the second simulation mode.

[0169] It should be noted that the fault processor using the second simulation mode is used to process at least one fault group, and the multithreading of the fault processor using the second simulation mode is used to simulate all the to-be-simulated faults in the processed fault group.

[0170] In this step, the multi-threaded computing device using the competitive inclusion and dimension fusion fault simulation strategy performs fault simulation on one or more fault groups. One thread participates in the fault simulation of at least one fault group, and the fault simulation of each thread is performed in parallel. If the fault to be simulated can be detected, after all threads have completed this fault simulation, check whether there are any faults to be simulated in the first fault set. If the fault to be simulated cannot be detected, two reasons need to be considered. One is that the fault can be simulated but cannot be detected. In this case, the fault is in an undetectable state, and the undetected fault to be simulated is placed in the second fault set to facilitate the next vector group to detect it; the second is that the fault is abandoned due to conflict during the simulation process. In this case, it is put back into the first fault set so that the current vector group can perform the next round of fault simulation on it.

[0171] Furthermore, the steps of performing parallel fault simulation on all to-be-simulated faults in the assigned fault group by using multiple threads of the fault processor using the second simulation mode mainly include:

[0172] Acquire a logic gate in the circuit netlist whose circuit level identifier and logic identifier are a second value as a logic gate to be simulated;

[0173] According to the hierarchical structure in the circuit netlist, the to-be-simulated logic gates in the circuit netlist are activated in sequence in an increasing manner of the circuit hierarchy using the to-be-simulated faults in the fault group, so as to perform fault simulation on the to-be-simulated logic gates.

[0174] In an embodiment of the present invention, a competitive inclusion and dimensional fusion fault simulation strategy is adopted to realize fault simulation of a circuit netlist. The competitive inclusion and dimensional fusion fault simulation strategy refers to that multiple faults to be simulated in each fault group share a simulation value storage space and an event management mechanism to perform event-driven hierarchical fault parallel simulation. The competitive inclusion and dimensional fusion fault simulation strategy is mainly divided into two aspects: event management mechanism and shared simulation value storage space.

[0175] Specifically, in the related art, a fault simulation requires a complete circuit simulation value storage space, while the number of logic gates activated by the event-driven simulation of the fault circuit is very limited. For a circuit of 20 million gates, the circuit simulation value storage space for the transition delay fault simulation can reach 2GB. If each fault simulation requires 2GB of memory, the memory consumption is very large. In this regard, the embodiment of the present invention is based on the aforementioned fault grouping step. When the paths of fault activation in the circuit netlist are not intertwined and independent of each other, all faults to be simulated in the fault group inserted into the circuit netlist are subjected to fault simulation using the same simulation value storage space, so that all faults in the same group can share the circuit simulation value storage space, that is, the parallel simulation of multiple faults only requires 2GB of memory, which greatly reduces the memory consumption of parallel fault simulation.

[0176] More specifically, when the simulation value storage space of the logic gate is N, the logic gate can store simulation values ​​of N faults at most.

[0177] Specifically, the event management mechanism uses a one-dimensional array circuit level identifier level_flag[N L ], two-dimensional array logic gate identifier eval_flag[N gate ][N netlist ], guiding multiple faults to perform event-driven fault simulation in a circuit-level incremental manner. L is the number of circuit levels, N gate is the number of circuit logic gates, N netlist is the number of netlists.

[0178] When a certain logic gate needs to be fault simulated, the value of its corresponding circuit level identifier and logic gate identifier is a second value. Optionally, the second value is 1. When performing fault simulation, when a certain circuit level identifier is detected to be 1, all logic gate identifiers of the circuit level are detected, and then the logic gates with circuit level identifiers and logic identifiers of 1 in the circuit netlist are obtained, which are used as the logic gates to be simulated, and fault simulation is performed on the logic gates to be simulated. If the fault effect is transmitted to the same logic gate, the corresponding identifier is only set to 1 multiple times, and the common problem of data competition when the same logic gate is activated by event-driven simulation will not occur. The embodiment of the present invention has the advantage of competition inclusion.

[0179] In addition, when the simulation value storage space of the logic gate is N, the logic gate can store the simulation values ​​of N faults at most. When there are N+1 fault simulations passing through the logic gate, that is, N+1 faults activate the same logic gate at the same time, then the simulation values ​​of N+1 faults need to be stored, and then a storage conflict problem will occur. In order to solve the problem of insufficient simulation value storage space of the logic gate caused by multiple faults activating the same logic gate at the same time, the embodiment of the present invention introduces a priority simulation mechanism in parallel fault simulation on the basis of competitive inclusion and dimensional fusion fault simulation strategies. The priority simulation mechanism is: when multiple faults to be simulated activate the same logic gate to be simulated, the faults to be simulated with a priority greater than the third value are retained for activation of the next circuit level, and the abandoned state is used as the detection state of the faults to be simulated with a priority less than or equal to the third value. It should be noted that the third value is determined by the simulation value storage space of the logic gate. In the priority simulation mechanism, according to the priorities of multiple to-be-simulated faults that simultaneously activate the same logic gate, the to-be-simulated faults with high priorities are used as to-be-simulated faults that can be transferred to the next circuit level, while the to-be-simulated faults with low priorities are abandoned in this round of fault simulation, which is defined as the abandoned state. The abandoned low-priority to-be-simulated faults will be reassigned later and fault simulation will be performed again.

[0180] For example, assuming that the storage space of each logic gate is 1, the logic gate can store at most one fault simulation value. If two fault simulations pass through the logic gate, both faults need to store simulation values, and there is a problem of insufficient space. At this time, the fault to be simulated is determined based on the priority of the two faults, and the fault simulation value with a high priority is retained, and the fault simulation with a low priority is abandoned.

[0181] The following is an example to illustrate the implementation process of the contention inclusion and dimension fusion fault simulation strategy proposed in the embodiment of the present invention.

[0182] Reference Fig. 9 , Fig. 9 The second simulation method provided by the present invention is used to Figure 3 The application diagram of the digital circuit for parallel fault simulation is shown in FIG. Fig. 9 The digital circuit shown has two circuit netlists, where Fig. 9 (a) is netlist 1, Fig. 9 (b) is Netlist 2. Both Netlist 1 and Netlist 2 have four circuit levels, namely L1 to L4. Fig. 9 In the test vector, the gray box represents the transmission of the fault effect, the white box represents the simulation value when there is no fault, and the number of circuit levels N L is 4, the number of logic gates in the circuit is N gate is 9, the number of netlists is N netlist is 2.

[0183] Assume that the fault processor includes a general-purpose graphics processor, and no multi-core processor participates in this round of fault simulation. Create the first fault set Finit = {a, c1, e, g}, and the test vector set Tinit = {(01111011, 10110000)}. Due to limited space, the test vector set in this embodiment only sets one set of test vectors. The faults are sorted by circuit level as a, e, g, c1, and the faults are numbered 1 to 4 in this order.

[0184] like Figure 3 The digital circuit shown can be divided into 7 FFRs, and the output of each FFR is a logic output or a fan-out. Fig.10 The FFR directed graph and FFR transmission domain shown in FIG. 1 are faulty. Since the circuit scale is small, the FFR transmission domain depth is set to 2 in this embodiment. The formula can be used to calculate Therefore, the maximum number of faults in a fault group is 2. In addition, the FFR levels of the FFR directed graph are level 1 and level 2, where FFR1 to FFE3 are located at level 1, and FFR4 to FFR7 are located at level 2.

[0185] Reference Fig.11 , Fig.11 It is a schematic diagram of the array identification of the event management mechanism provided by the present invention. Specifically, for netlist 1, non-overlapping FFR transmission domains containing faults are divided from the first layer FFR according to the grouping principle to obtain transmission domain 1 and transmission domain 3, and faults a and e are selected as one of the fault groups of the general graphics processor and inserted into netlist 1. At the same time, the fault priority within the group is set, and the faults are sorted from high to low as a and e. For netlist 2, transmission domains 2 and 4 are selected according to the grouping principle, and faults c1 and g are selected as another fault group of the general graphics processor and inserted into netlist 2. At the same time, the fault priority within the group is set, and the faults are sorted from high to low as c1 and g.

[0186] Afterwards, fault simulation is performed on the fault groups of the two netlists simultaneously through multiple threads of the general purpose graphics processor.

[0187] Under a set of test vectors (01111011, 10110000), netlist 1 and netlist 2 set the circuit level identifiers and logic gate identifiers corresponding to faults a, e, c1, and g to 1. When the circuit level identifier of L1 is detected as 1, the identifiers of the first layer G1_0 and G2_0 in netlist 1 are detected, and the identifier of the first layer G3_1 in netlist 2 is detected; when the identifiers of the first layer G1_0 and G2_0 in netlist 1 are detected as 1, the fault simulation is performed on the logic gates G1 and G2 of netlist 1, and when the identifier of the first layer G3_1 in netlist 2 is detected as 1, the fault simulation is performed on the logic gate G3 of netlist 2.

[0188] Afterwards, the flags of L1, G1_0, G2_0, and G3_1 are reset to 0. Faults a and e in netlist 1 are transferred to logic gates G4, G5, and G6 of L2, respectively. Fault group G in netlist 2 is transferred to logic gate G6 of L2, so the flags of L2, G4_0, G5_0, G6_0, and G6_1 are set to 1.

[0189] When the circuit level identification of L2 is detected as 1, the identifications of the second layer G4_0, G5_0, and G6_0 in netlist 1 are detected, and the identification of the second layer G6_1 in netlist 2 is detected; when the identifications of the second layer G4_0, G5_0, and G6_0 in netlist 1 are detected as 1, fault simulation is performed on the logic gates G4, G5, and G6 of netlist 1, and when the identification of the second layer G6_1 in netlist 2 is detected as 1, fault simulation is performed on the logic gate G6 of netlist 2.

[0190] Afterwards, the flags of L2, G4_0, G5_0, G6_0, and G6_1 are reset to 0, and the fault e in netlist 1 is transferred to the logic gate G8 of L3, so the flag of L3, G8_0 is set to 1, and the fault group G in netlist 2 is transferred to the output end.

[0191] When the circuit level identifier of L3 is detected as 1, the identifier of the third layer G8_0 in netlist 1 is detected, and the identifier of the third layer G7_1 in netlist 2 is detected; when the identifier of the third layer G8_0 in netlist 1 is detected as 1, a fault simulation is performed on the logic gate G8 of netlist 1, and when the identifier of the third layer G7_1 in netlist 2 is detected as 1, a fault simulation is performed on the logic gate G7 of netlist 2.

[0192] Afterwards, the flags of L3, G8_0, and G7_1 are set to 0. Fault e in netlist 1 is transmitted to logic gate G9 of L4, so the flag of L4, G9_0 is set to 1.

[0193] When the circuit level identification of L4 is detected as 1, the identification of the fourth layer G9_0 in netlist 1 is detected; when the identification of the fourth layer G9_0 in netlist 1 is detected as 1, the logic gate G9 of netlist 1 is simulated. However, there is no logic gate identification 1 in the L4 layer of netlist 2, so the L4 layer of netlist 2 does not need to be simulated.

[0194] Afterwards, the flags of L4 and G9_0 are set to 0, and this round of fault simulation ends.

[0195] Through this round of fault simulation, fault a in netlist 1 cannot be transmitted to the output end under this set of test vectors, and fault e transmitted to output end p is a detectable fault, among which there is no abandoned fault. Therefore, faults a and e are deleted from the first fault set Finit, and fault a is placed in the second fault set Fund. Faults c1 and g in netlist 2 cannot be detected by this test vector, so c1 and g are deleted from the first fault set Finit and placed in the second fault set Fund. At this time, the second fault set Fund = {a, c1, g}.

[0196] After this round of fault simulation is finished, the first fault set Finit is empty, the current test vector group is deleted from the test vector set T, the first fault set Finit = Fund = {a, c1, g} is set, and the second fault set Fund is cleared. However, since the test vector set T is an empty set, the fault simulation ends.

[0197] In addition, an embodiment of the present invention further provides a parallel fault simulation system for heterogeneous computing, including:

[0198] An acquisition module, used to acquire device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated; wherein the plurality of fault processors include a plurality of first processors and a plurality of second processors, the first processors and the second processors are heterogeneous, and the first fault set includes a plurality of faults to be simulated and their numbers;

[0199] A first processing module, used to determine a fault simulation mode of each fault processor according to a device parameter of each fault processor; wherein the fault simulation mode includes any one of a first simulation mode or a second simulation mode;

[0200] A first judging module, used to judge whether there is at least one test vector group in the test vector set;

[0201] A second processing module is used for obtaining a current test vector group from the test vector set when there is at least one test vector group in the test vector set, initializing multiple circuit netlists of the digital circuit to a fault-free state, assigning a corresponding fault group to each fault processor according to a device parameter of each fault processor, performing fault simulation on multiple circuit netlists according to a fault simulation mode of each fault processor and the assigned fault group under the current test vector group, and updating the first fault set and the second fault set;

[0202] A second judgment module, used to judge whether the first fault set is an empty set;

[0203] A third processing module is used for, when the first fault set is not empty, returning to the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor; when the first fault set is an empty set, deleting the current test vector group from the test vector set, and selecting the next test vector group as the current test vector group;

[0204] A third judgment module is used to judge whether the second fault set is an empty set;

[0205] A fourth processing module, configured to obtain the second fault set as the first fault set when the second fault set is not empty, and return to the step of determining whether the test vector set contains at least one test vector group;

[0206] An end module is used to output a fault simulation result of the digital circuit when the test vector set or the second fault set is an empty set.

[0207] The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0208] An embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to execute the above-mentioned parallel fault simulation method for heterogeneous computing.

[0209] Similarly, the contents of the above method embodiments are all applicable to the present storage medium embodiments. The functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0210] In summary, in the prior art, multi-core processors generally use a data parallel fault simulation strategy to handle faults, that is, different computing cores can independently simulate different faults, but each fault simulation requires a large amount of storage space. Insufficient space will cause frequent memory and hard disk data exchanges, which greatly reduces performance. Therefore, this homogeneous parallel fault simulation places high demands on the system's storage capacity and has high hardware costs.

[0211] The embodiments of the present invention provide a parallel fault simulation method, system and medium for heterogeneous computing. Different computing devices will determine the strategy to be adopted for handling the current fault group based on the memory size they can provide and the memory size required to simulate the current fault group. For multi-core processors, if there is sufficient memory, a general data parallel fault simulation strategy is adopted, which can make full use of memory resources and efficiently complete fault simulation; if the memory resources available to the multi-core processor are insufficient, or if it is other devices with limited memory, a competitive inclusion and dimensional fusion fault handling strategy is adopted, which can ensure that various processors can make full use of current resources to handle faults in parallel and achieve performance optimization.

[0212] The present invention utilizes the computing devices of heterogeneous architectures to work together and maximizes the use of the memory of each computing device for multi-threaded parallel fault simulation. It can overcome the data competition and storage capacity constraint problems that occur when computing devices such as general-purpose image processors perform fault simulation. It effectively solves the problems of high memory overhead and insufficient utilization of high-performance computing power in the prior art that only relies on homogeneous parallel computing to handle fault simulation, and greatly improves resource utilization and fault simulation performance.

[0213] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0214] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A parallel fault simulation method for heterogeneous computing, characterized in that: The following steps are involved: Acquire device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated; The multiple fault processors include multiple first processors and multiple second processors, the first processors and the second processors are heterogeneous, and the first fault set includes multiple faults to be simulated and their numbers; Determine the fault simulation mode of each fault processor according to the device parameters of each fault processor; Wherein, the fault simulation mode includes any one of the first simulation mode or the second simulation mode; Determining whether the test vector set contains at least one test vector group; When the test vector set has at least one test vector group, a current test vector group is obtained from the test vector set, multiple circuit netlists of the digital circuit are initialized to a fault-free state, a corresponding fault group is assigned to each fault processor according to the device parameters of each fault processor, and under the current test vector group, fault simulation is performed on multiple circuit netlists according to the fault simulation mode of each fault processor and the assigned fault group, and the first fault set and the second fault set are updated; Determine whether the first fault set is an empty set; if not, return to the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor; if so, delete the current test vector group from the test vector set, select the next test vector group as the current test vector group, and when the second fault set is not empty, obtain the second fault set as the first fault set, and return to the step of determining whether the test vector set has at least one test vector group; When the test vector set or the second fault set is an empty set, outputting a fault simulation result of the digital circuit; Wherein, under the current test vector group, fault simulation is performed on multiple circuit netlists according to the fault simulation mode of each fault processor and the assigned fault group, and the first fault set and the second fault set are updated, including: Inserting each of the fault groups into a corresponding circuit netlist; Under the current test vector group, the digital circuit is fault simulated according to the fault simulation mode of each fault processor and the assigned fault group to obtain the detection state of each fault to be simulated; The detection status includes any one of a completed status, an undetectable status or an abandoned status; Add the to-be-simulated faults in the first fault set that belong to the undetectable state to the second fault set, and delete the to-be-simulated faults in the first fault set that belong to the completed state and the undetectable state; Each of the circuit netlists is initialized to a non-fault state under the current test vector group.

2. The parallel fault simulation method for heterogeneous computing according to claim 1, characterized in that: The method of determining the fault simulation mode of each fault processor according to the device parameters of each fault processor includes: When the fault processor is a first processor, the fault simulation memory of the fault processor is calculated according to the device parameters of the fault processor, when the fault simulation memory of the fault processor satisfies the first memory, the first simulation method is used as the fault simulation method of the fault processor, and when the fault simulation memory of the fault processor does not satisfy the first memory, the second simulation method is used as the fault simulation method of the fault processor; When the fault processor is a second processor, the fault simulation memory of the fault processor is calculated according to the device parameters of the fault processor. When the fault simulation memory of the fault processor satisfies the second memory, the second simulation method is adopted as the fault simulation method of the fault processor. When the fault simulation memory of the fault processor does not satisfy the second memory, the fault processor is used as a fault processor that does not participate in fault simulation.

3. The parallel fault simulation method for heterogeneous computing according to claim 1, characterized in that: The step of allocating a corresponding fault group to each fault processor according to the device parameters of each fault processor includes: According to the device parameters of the fault processor using the first simulation method, part of the faults to be simulated in the first fault set are allocated to the fault processor using the first simulation method, and a fault group of the fault processor using the first simulation method is generated, and the unallocated faults to be simulated in the first fault set are used as the fault set to be allocated; Dividing the digital circuit into a plurality of non-fan-out regions, taking the non-fan-out regions as basic units, and representing the connections and data flows between the non-fan-out regions by directed line segments, thereby constructing an FFR directed graph of the digital circuit; The FFR directed graph has a hierarchical structure, the non-fan-out area is a circuit area in the digital circuit that has only one output terminal and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line in each non-fan-out area is connected to at most one input terminal of a logic gate; Allocating multiple to-be-simulated faults in the to-be-allocated fault set to multiple circuit netlists of the digital circuit through the FFR directed graph to obtain initial fault groups of the multiple circuit netlists; According to the device parameters of the fault processor using the second simulation mode, the plurality of initial fault groups are allocated to the fault processor using the second simulation mode, thereby generating the fault groups corresponding to the fault processor using the second simulation mode.

4. The parallel fault simulation method for heterogeneous computing according to claim 3, characterized in that: For each circuit netlist, the step of assigning multiple to-be-simulated faults in the to-be-assigned fault set to the circuit netlist through the FFR directed graph to obtain an initial fault group of the circuit netlist includes: Determining transmission parameters of the circuit netlist; According to the FFR directed graph and the transmission parameters, construct a plurality of fan-out-free transmission domains of the circuit netlist, wherein two adjacent fan-out-free transmission domains do not overlap each other, and each of the fan-out-free transmission domains includes at least one fault to be simulated and at least two fan-out-free areas; Selecting at least one fault to be simulated from each of the fan-out-free transmission domains in turn; Determine the priority of the selected fault to be simulated according to the number of the selected fault to be simulated, wherein the priority of the fault to be simulated with a smaller number is higher than the priority of the fault to be simulated with a larger number; The faults to be simulated and their priorities are used as the initial fault group of the circuit netlist.

5. The parallel fault simulation method for heterogeneous computing according to claim 4, characterized in that: The step of constructing a plurality of fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters comprises: According to the hierarchical structure of the FFR directed graph, any of the fan-out-free areas is used as an output point, and an FFR layer located before the FFR layer where the output point is located is used as a to-be-selected layer. The output point and the fan-out-free area in the to-be-selected layer that meets the transmission parameters and is connected to the output point are selected as fan-out-free transmission domains, thereby constructing multiple fan-out-free transmission domains of the circuit netlist.

6. The parallel fault simulation method for heterogeneous computing according to claim 1, characterized in that: The performing fault simulation on the digital circuit according to the fault simulation mode of each fault processor and the assigned fault group includes: Performing fault simulation on multiple to-be-simulated faults in the assigned fault group in parallel by using multiple threads of the fault processor using the first simulation mode, wherein each thread of the fault processor using the first simulation mode is used to perform fault simulation on at most one to-be-simulated fault; Fault simulation is performed in parallel on all faults to be simulated in the assigned fault group by using multiple threads of a fault processor using the second simulation method, wherein the fault processor using the second simulation method is used to process at least one fault group, and the multiple threads of the fault processor using the second simulation method are used to perform fault simulation on all faults to be simulated in the processed fault group.

7. The parallel fault simulation method for heterogeneous computing according to claim 6, characterized in that: The method of performing parallel fault simulation on all to-be-simulated faults in the assigned fault group by using multiple threads of the fault processor using the second simulation mode includes: Acquire a logic gate in the circuit netlist whose circuit level identifier and logic identifier are a second value as a logic gate to be simulated; According to the hierarchical structure in the circuit netlist, the to-be-simulated logic gates in the circuit netlist are activated in sequence in an increasing manner of circuit hierarchy using the to-be-simulated faults in the fault group to perform fault simulation on the to-be-simulated logic gates.

8. The parallel fault simulation method for heterogeneous computing according to claim 6, characterized in that: The method of performing parallel fault simulation on all to-be-simulated faults in the assigned fault group by using multiple threads of the fault processor using the second simulation mode also includes: When the fault-activated paths in the circuit netlist are not interlaced and are independent of each other, the same simulation value storage space is used to perform fault simulation on all to-be-simulated faults in the fault group inserted into the circuit netlist.

9. The parallel fault simulation method for heterogeneous computing according to claim 6, characterized in that: The method of performing parallel fault simulation on all to-be-simulated faults in the assigned fault group by using multiple threads of the fault processor using the second simulation mode also includes: When multiple faults to be simulated activate the same logic gate to be simulated, the faults to be simulated with a priority greater than the third value are retained for activation of the next circuit level, and the abandoned state is used as the detection state of the faults to be simulated with a priority less than or equal to the third value.

10. Parallel fault simulation system for heterogeneous computing, characterized in that: The method for parallel fault simulation for heterogeneous computing as claimed in any one of claims 1 to 9 comprises: An acquisition module, used to acquire device parameters of a plurality of fault processors and a first fault set and a test vector set of a digital circuit to be simulated; wherein the plurality of fault processors include a plurality of first processors and a plurality of second processors, the first processors and the second processors are heterogeneous, and the first fault set includes a plurality of faults to be simulated and their numbers; A first processing module, used to determine a fault simulation mode of each fault processor according to a device parameter of each fault processor; wherein the fault simulation mode includes any one of a first simulation mode or a second simulation mode; A first judging module, used to judge whether there is at least one test vector group in the test vector set; A second processing module is used for obtaining a current test vector group from the test vector set when there is at least one test vector group in the test vector set, initializing multiple circuit netlists of the digital circuit to a fault-free state, assigning a corresponding fault group to each fault processor according to a device parameter of each fault processor, performing fault simulation on multiple circuit netlists according to a fault simulation mode of each fault processor and the assigned fault group under the current test vector group, and updating the first fault set and the second fault set; A second judgment module, used to judge whether the first fault set is an empty set; A third processing module is used for, when the first fault set is not empty, returning to the step of assigning a corresponding fault group to each fault processor according to the device parameters of each fault processor; when the first fault set is an empty set, deleting the current test vector group from the test vector set, and selecting the next test vector group as the current test vector group; A third judgment module is used to judge whether the second fault set is an empty set; A fourth processing module, configured to obtain the second fault set as the first fault set when the second fault set is not empty, and return to the step of determining whether the test vector set contains at least one test vector group; An end module is used to output a fault simulation result of the digital circuit when the test vector set or the second fault set is an empty set.

Images