A data transmission method and system for Ethernet media access control layer

Abstract

The present invention provides a data transmission method and system for an Ethernet media access control layer, the method comprising: in a data receiving direction, receiving a serial data stream from a physical layer, converting it into parallel data of a set bit width through a serial-to-parallel converter, performing bit width conversion on the parallel data and adding an enable control signal, descrambling, sampling, and latching the data through an Ethernet physical layer receiver, and then decoding and converting the data format through a decoder and transmitting it to a receiver of a media access control layer. In the sending direction, the inverse operation of the receiving direction is performed. The present invention uses a synchronous GearBox to replace an asynchronous GearBox, and adds an enable control signal, which can reduce the MAC delay value.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet communication protocols, and in particular to a data transmission method and system for an Ethernet media access control layer. Background Art

[0002] The existing open source Ethernet MAC (Media Access Control) refers to the part of the Ethernet protocol stack responsible for the data link layer based on the open source principle. Ethernet is a common local area network technology used to transmit data in computer networks. As a standardized local area network technology, Ethernet was first jointly developed by companies such as Xerox, Intel and DEC (Digital Equipment Corporation), and was standardized as the IEEE 802.3 protocol by the IEEE (Institute of Electrical and Electronics Engineers) in 1983. This protocol defines the physical layer and data link layer specifications of Ethernet, among which the MAC sublayer in the data link layer is responsible for implementing the encapsulation, decapsulation and media access control of data frames. The GearBox module is used at the Ethernet physical layer interface to realize the conversion between data bit widths and rate matching. In the prior art, the synchronous mode GearBox module is usually used, which has the problem of high MAC delay value. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a data transmission method and system for an Ethernet media access control layer to eliminate the problem of a gap in the effective signal on the encoding side after replacing the asynchronous GearBox with the synchronous GearBox in the prior art, thereby reducing the MAC delay value.

[0004] One aspect of the present invention provides a method for receiving data at an Ethernet media access control layer, the method comprising the following steps:

[0005] Receiving a serial data stream from a physical medium layer by a high-speed transceiver interface, wherein the serial data stream has a first set bit width;

[0006] The serial data stream is converted into a first parallel data stream of a second set bit width by a serial-to-parallel converter, wherein the serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to perform data stream rate conversion;

[0007] Converting the second parallel data stream of the set bit width into a second parallel data stream of the third set bit width, and adding an enable control signal to indicate valid data headers and data content in the second parallel data stream; the second parallel data stream meets the coding processing standard requirements of the Ethernet physical layer receiver;

[0008] The Ethernet physical layer receiver descrambles and samples the second parallel data stream, and latches the correct data header and data content;

[0009] Outputting the descrambled second parallel data stream to a decoder and converting it into a third parallel data stream in a standard interface format that meets the requirements of the media access control layer; inserting a cyclic redundancy check module into the media access control layer interface to detect whether the data packet contains error information; the standard interface format is XGMII, and the standard protocol format is AXI;

[0010] Converting the third parallel data stream into the second set bit width;

[0011] The third parallel data stream is converted into a standard protocol format by a receiver module of the media access control layer.

[0012] In some embodiments of the present invention, the first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter is a SerDes converter.

[0013] In some embodiments of the present invention, the Ethernet physical layer receiver includes: a descrambling module, a PRBCheck module, a frame synchronization detection module, a bit error rate monitoring module and a WatchDog module.

[0014] Another aspect of the present invention provides a method for sending data at an Ethernet media access control layer, the method comprising the following steps:

[0015] The third parallel data stream is received by the media access control layer interface, and the third parallel data stream is converted from the standard protocol format to the standard interface format, wherein the third parallel data stream has a second set bit width; a cyclic redundancy check module is inserted into the media access control layer interface to detect whether the data packet contains error information; the standard interface format is XGMII, and the standard protocol format is AXI;

[0016] Converting the third parallel data stream from the second set bit width to a third set bit width;

[0017] Transmitting the third parallel data stream of the third set bit width to an encoder to convert it into a second parallel data stream;

[0018] scrambling the second parallel data stream via an Ethernet physical layer transmitter;

[0019] Converting the second parallel data stream of the third set bit width into a first parallel data stream of the second set bit width, and adding an enable control signal to indicate valid data headers and data content in the first parallel data stream;

[0020] The first parallel data stream is converted into a serial data stream with a first set bit width by a serial-to-parallel converter and sent to a high-speed transceiver interface; the serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to convert the data stream rate.

[0021] In some embodiments of the present invention, the first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter is a SerDes converter.

[0022] In some embodiments of the present invention, the Ethernet physical layer transmitter includes: a pseudo-random code module and a scrambling code module.

[0023] Another aspect of the present invention provides a data transmission system for an Ethernet media access control layer, comprising a processor and a memory, the system being used for receiving and sending data at the media access control layer in Ethernet, the memory storing computer instructions, the processor being used for executing the computer instructions stored in the memory, and when the computer instructions are executed by the processor, the system implements the steps of any one of the above methods.

[0024] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the steps of any one of the above methods.

[0025] The beneficial effects of the present invention are at least:

[0026] The present invention provides a data transmission method and system for an Ethernet media access control layer, the method comprising: in a data receiving direction, receiving a serial data stream from a physical layer, converting it into parallel data of a set bit width through a serial-to-parallel converter, performing bit width conversion on the parallel data and adding an enable control signal, descrambling, sampling, and latching the data through an Ethernet physical layer receiver, and then decoding and converting the data format through a decoder and transmitting it to a receiver of the media access control layer. The sending direction performs the inverse operation of the receiving direction. In the present invention, a synchronous GearBox is used to replace an asynchronous GearBox, and after the GearBox is replaced, an enable control signal is added to the data subsequently processed by it. The present invention solves the problem of an effective signal gap on the encoding side after the synchronous GearBox replaces the asynchronous GearBox, and can reduce the MAC delay value at the same time.

[0027] Additional advantages, purposes, and features of the present invention will be described in part in the following description, and will become apparent to those skilled in the art after studying the following, or may be learned from the practice of the present invention. The purposes and other advantages of the present invention may be achieved and obtained by the structures specifically indicated in the specification and the accompanying drawings.

[0028] Those skilled in the art will appreciate that the objectives and advantages that can be achieved with the present invention are not limited to the above specific description, and the above and other objectives that can be achieved by the present invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of the present application, and do not constitute a limitation of the present invention. In the drawings:

[0030] Figure 1 The present invention is a flowchart of a method for receiving data in an Ethernet media access control layer according to an embodiment of the present invention.

[0031] Figure 2 The present invention is a flowchart of a method for sending data in an Ethernet media access control layer according to an embodiment of the present invention.

[0032] Figure 3 This is a diagram of the data transmission process of the Ethernet media access control layer according to another embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the data sending direction of the Ethernet media access control layer according to another embodiment of the present invention.

[0034] Figure 5 This is a schematic diagram of the data receiving direction of the Ethernet media access control layer according to another embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0036] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0037] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0038] It should also be noted that, unless otherwise specified, the term “connection” herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0040] Ethernet MAC (Media Access Control) is a communication protocol for local area networks (LANs). It defines how data is transmitted and accessed on shared media. Ethernet MAC address is a hardware address that uniquely identifies a network device and is represented by a 48-bit binary number. MAC addresses are usually expressed in hexadecimal and consist of 6 bytes, each byte represented by two hexadecimal digits. In Ethernet, data packets are encapsulated in frames with source and destination MAC addresses. Network devices such as switches and routers use MAC addresses to determine the transmission path and destination device of data packets. The MAC layer is responsible for managing and controlling the transmission of data frames, and works in conjunction with the physical layer to ensure reliable data transmission.

[0041] An aspect of an embodiment of the present invention provides a method for receiving data at an Ethernet media access control layer, the method comprising the following steps S101-S107:

[0042] Step S101: a high-speed transceiver interface receives a serial data stream from a physical medium layer, where the serial data stream has a first set bit width.

[0043] Step S102: The serial data stream is converted into a first parallel data stream of a second set bit width by a serial-to-parallel converter, and the serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to convert the data stream rate.

[0044] Among them, the serial-to-parallel converter is used to connect the transmission medium between two devices, so that data can be transmitted between different hardware. It can input multiple parallel signals through the parallel input port and convert these signals into high-speed serial data stream output. Similarly, it can also parse the received high-speed serial data stream into parallel signals and output them to the target device.

[0045] Step S103: convert the parallel data stream of the second set bit width into a second parallel data stream of the third set bit width, and add an enable control signal to indicate the valid data header and data content in the second parallel data stream; the second parallel data stream meets the coding processing standard requirements of the Ethernet physical layer receiver.

[0046] Step S104: The Ethernet physical layer receiver descrambles and samples the second parallel data stream, and latches the correct data header and data content.

[0047] Among them, the Ethernet physical layer receiver is responsible for receiving and processing the data stream transmitted from the sender, and providing the valid data to the subsequent processing module for further processing and forwarding. Its functions include: descrambling to restore the original data stream, sampling and analyzing data, window latching to capture the header information and valid data of the data packet, parsing the header information, and continuing to parse the valid data part after obtaining the header information.

[0048] Step S105: output the descrambled second parallel data stream to the decoder and convert it into a third parallel data stream in a standard interface format that meets the requirements of the media access control layer.

[0049] Among them, the standard interface format is XGMII. XGMII (10Gigabit Media Independent Interface) is a commonly used interface standard in network communication, used to transmit data between the MAC (Media Access Control) layer and the physical layer. XGMII usually uses a 32-bit parallel data interface.

[0050] Step S106: Convert the third parallel data stream into a second set bit width.

[0051] Step S107: The receiver module of the media access control layer converts the third parallel data stream into a standard protocol format. The standard protocol format is AXI. AXI (Advanced eXtensible Interface) is a bus protocol. This protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency.

[0052] In some embodiments of the present invention, the first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter adopts a SerDes converter.

[0053] In some embodiments of the present invention, it further includes: inserting a cyclic redundancy check module in the media access control layer interface to detect whether the data packet contains error information.

[0054] Among them, the cyclic redundancy check (CRC) module is a technology used for error detection in data communication and storage. Its main function is to detect the data integrity during data transmission or storage to ensure that the data has not been damaged or tampered with during transmission or storage. The cyclic redundancy check (CRC) module is usually attached to the end of the data frame. The receiver uses CRC to verify the integrity of the data frame to determine whether valid data has been received.

[0055] In some embodiments of the present invention, the Ethernet physical layer receiver includes: a descrambling module, a PRBCheck module, a frame synchronization detection module, a bit error rate monitoring module and a WatchDog module.

[0056] Among them, the descrambling module implements the descrambling operation of the physical coding sublayer to adapt to the data transmission form of the physical medium. The PRBCheck module is used to send pseudo-random sequences and checks. The frame synchronization detection module is used to control the GearBox to search and synchronize data blocks. The bit error rate monitoring module monitors high bit error rates. When the headers of the set number of data frames received continuously are not control signals, they are recorded as high bit error rate status. The WatchDog module is used to monitor and record the synchronization status, bit error rate and whether there are errors in the decoding module during data transmission. When specific conditions are met, the Watchdog module will reset the receiving end to ensure the reliability and stability of data transmission.

[0057] Another aspect of the present invention provides a method for sending data at an Ethernet media access control layer, the method comprising the following steps S201-S206:

[0058] Step S201: receiving a third parallel data stream through a media access control layer interface, converting the third parallel data stream from a standard protocol format to a standard interface format, wherein the third parallel data stream has a second set bit width.

[0059] Among them, the standard protocol format is AXI and the standard interface format is XGMII.

[0060] AXI (Advanced eXtensible Interface) is a bus protocol. It is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth and low latency.

[0061] XGMII (10Gigabit Media Independent Interface) is a commonly used interface standard in network communications, used to transmit data between the MAC (Media Access Control) layer and the physical layer. XGMII usually uses a 32-bit parallel data interface.

[0062] Step S202: converting the third parallel data stream from the second set bit width to the third set bit width;

[0063] Step S203: transmitting the third parallel data stream with the third set bit width to the encoder to convert it into a second parallel data stream.

[0064] Step S204: scramble the second parallel data stream via the Ethernet physical layer transmitter.

[0065] Among them, scrambling increases the randomness and anti-interference ability of data by changing the data bit pattern, thereby improving the reliability and anti-interference of data transmission. Changing the data bit pattern does not change the actual content and meaning of the data, but only rearranges or transforms the bits of the data.

[0066] Step S205: converting the second parallel data stream of the third set bit width into the first parallel data stream of the second set bit width, and adding an enable control signal to indicate the valid data header and data content in the first parallel data stream.

[0067] Step S206: The serial-to-parallel converter converts the first parallel data stream into a serial data stream with a first set bit width and sends it to the high-speed transceiver interface. The serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to convert the data stream rate.

[0068] In some embodiments of the present invention, the first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter is a SerDes converter.

[0069] In some embodiments of the present invention, it further includes: inserting a cyclic redundancy check module in the media access control layer interface to detect whether the data packet contains error information.

[0070] In some embodiments of the present invention, the Ethernet physical layer transmitter includes: a pseudo-random code module and a scrambling code module.

[0071] The pseudo-random code module is used to generate a pseudo-random sequence to detect and avoid data conflicts, and the scrambling module is used to randomize the data stream to ensure data security and confidentiality.

[0072] Another aspect of the present invention provides a data transmission system of an Ethernet media access control layer, comprising a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps in the above method.

[0073] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program implements the steps in the above method when executed by a processor.

[0074] Another embodiment of the present invention provides a data control method and system for an Ethernet media access control layer, and the specific implementation method is as follows:

[0075] The embodiment of the present invention uses a synchronous GearBox to replace the asynchronous GearBox. According to official technical support materials, the delay can be reduced by about 50ns. GearBox is a gearbox that realizes the conversion between arbitrary data bit widths. Regarding the encoding process, refer to the following example: If two 32 bits are transmitted from the physical coding sublayer XGMII, they are added together to 64 bits, and encoded by the encoder to obtain the encoded data D0-D7, and generate the synchronization header 01. Then, D0-D7 without the synchronization header passes through the scrambler to obtain the data S0-S7 after scrambling by the expression X58+X39+1.

[0076] Among them, the role of GearBox in PHY (Ethernet physical layer) is to cut the data and then convert it into 64-bit data plus 2-bit header for output. The interface of GearBox close to the serial end is processed in the form of 8, 16, 32, 64 widths, while the interface of GearBox close to the 64 / 66b encoding side is in the form of 32 or 64 plus 2-bit headers. The asynchronous GearBox uses asynchronous clocks on both sides, and each row output to the encoding side is valid, and no enable is required for indication. The synchronous GearBox uses synchronous clocks on both sides, which leads to gaps in valid signals on the encoding side. Therefore, after replacing the GearBox, it is necessary to add enable control signals to all the data processed later.

[0077] The principle of the present invention is very similar to gated clock logic. By adding an enable in each clock-controlled logic, the correct logic can be achieved by storing and maintaining the signal when the enable is not enabled.

[0078] The data transmission process is as follows Figure 3 As shown, specifically including:

[0079] Receiving direction:

[0080] (1) The high-speed interface receives 1-bit serial data and converts it into 32-bit parallel data through the SerDes IP.

[0081] (2) Convert the received 32-bit data into 64-bit data and comply with 64 / 66 encoding.

[0082] (3) The data is descrambled and sampled by the ETH_PHY_RX module, the corresponding window is found, and the correct header information and data information are latched.

[0083] (4) The data is decoded by the decoder module and converted into the XGMII format.

[0084] (5) The 64-bit XGMII data is converted to 32-bit bit width.

[0085] (6) The data is converted into AXI format data through the mac_rx module and sent to other modules.

[0086] Sending direction:

[0087] (1) MAC receives AXI format data sent by other modules and converts it into XGMII format data through the mac_tx module.

[0088] (2) The 32-bit data in XGMII format is converted into 64-bit data.

[0089] (3) The data passes through the decoder module and is converted into corresponding data and header information.

[0090] (4) The data is scrambled by the ETH_PHY_TX module.

[0091] (5) The data is converted to a 32-bit bit width and complies with 64 / 66 encoding.

[0092] (6) The parallel data is converted into serial data by the SerDes IP and sent to the interface.

[0093] Among them, the GT transceiver selects IP, and the SerDes selects the synchronous Sync mode to replace the original asynchronous Async mode. The Sync mode has a faster clock frequency than the Async mode.

[0094] To explain further, a GT transceiver is a high-speed serial communication interface that transfers data between chips or boards. SerDes is a circuit that converts parallel data into serial data (and vice versa). It is often used in high-speed communications to transfer data from a parallel bus to a serial bus, or vice versa. Synchronous Mode is a communication mode in which the transmission of data is based on the synchronization of a clock signal. In this mode, the transmission and reception of data are performed according to the specific timing of the clock signal. Asynchronous Mode is another communication mode in which the transmission of data does not rely on strict clock synchronization. In asynchronous mode, techniques such as start bits and stop bits are usually used to mark the beginning and end of data.

[0095] The clock frequency of asynchronous Async mode is 312.5MHz;

[0096] XCLK rate = line rate / 64;

[0097] Tx / Rxusrclk2 rate=10.3125 / 33=312.5MHz;

[0098] The clock frequency of synchronous Sync mode is 322.3MHz;

[0099] XCLK rate=line Rate / 64(pma parallel);

[0100] Tx / Rxusrclk2 rate=10.3125 / 32=322.3MHz.

[0101] Among them, XCLK rate refers to the external clock frequency; line rate refers to the line rate, that is, the data transmission rate on the transmission medium; Tx / Rxusrclk2 rate refers to the frequency of user clock 2 used for sending and receiving; pma parallel refers to parallel transmission or parallel processing.

[0102] Furthermore, since the data interface of the open source MAC is 64 bits and the user interface is 32 bits, it is necessary to do bit width conversion in gt-SerDes. When converting between 64 bits and 32 bits, the high bit of the 64 bits needs to correspond to the first 32 bits of data, and the low bit needs to correspond to the second 32 bits of data. The specific method of GT bit width conversion is as follows:

[0103] (1) The data flow in the sending direction (Tx direction) is as follows Figure 4 As shown:

[0104] The tx direction of SerDes needs to be indicated by the txsequence_out signal. Since the data bit width is 32 bits, the signal changes from 0 to 32, each maintaining 2 beats. The synchronous GearBox needs to ensure that when txsequence_out = 32, the data is invalid.

[0105] (2) The data flow in the receiving direction (Rx direction) is as follows Figure 5 As shown:

[0106] In the rx direction of SerDes, there are two valids to indicate whether the data and header are valid. It should be noted that only one header is valid for every 64 bits of data, that is, in the 32-bit bit width data mode, only one header is valid in two beats of data.

[0107] Among them, ETH_PHY_TX (transmitter) and ETH_PHY_RX (receiver) work together to implement the physical layer functions of Ethernet communication and ensure that data is reliably transmitted and received in Ethernet.

[0108] ETH_PHY_TX is the transmitter of the Ethernet physical layer (PHY), which converts the data received by the logical layer into electrical signals and sends the data through physical media (such as cables). ETH_PHY_TX includes the following modules:

[0109] (1) PRBS module: PRBS can send and check pseudo-random sequences.

[0110] (2) Scrambling module: The Scrambler module implements the scrambling operation of the PCS layer.

[0111] ETH_PHY_RX, the receiving end of the Ethernet physical layer (PHY), includes the following modules:

[0112] (1) Descrambling module: The Descrambler module implements the descrambling operation of the PCS layer.

[0113] (2) PRBCheck module: Prbs_check can send pseudo-random sequences and check

[0114] (3) FrameSyn module: Frame_syn is used to control GearBox to search for data blocks and make synchronization judgments. After reset, the first rx_bitslip pulse is generated to adjust the received data sampling position. If rx_header is still not ctl / data after adjustment, an rx_bitslip pulse is generated every fixed time (8clk) to adjust the received data sampling position. If rx_headr receives 0x40 consecutive ctl / data, it is determined that the PHY is now in the block_lock state and no other adjustments are made.

[0115] (4) Ber_Mon module: The Ber_mon module monitors the high bit error rate. If the rx_header receives more than 16 consecutive bits that are not ctl / data, it is judged to enter the High_Ber state; after the timing reaches 125us, if the rx_header is ctl / data, the High_Ber state is released.

[0116] (5) WatchDog module: The Watchdog module collects synchronization and bit error rate information as well as error information from the decoding module, and resets the rx end of the GTH when necessary. It determines that the rx_bad_block and rx_sequence_error signals are pulled high for 125us, and counts 16 times continuously to generate a reset.

[0117] Among them, the encoding and decoding module includes:

[0118] (1) Encoder in Tx direction: The Encoder module implements 64 / 66B encoding and converts the interface from XGMII to header+data format.

[0119] (2) Rx direction Decoder: The Decode module implements XGMII encoding and converts the interface from header+data to XGMII format.

[0120] Furthermore, the MAC module performs the following operations:

[0121] (1) Tx direction: Mac_tx implements the conversion from AXIS interface to XGMII interface and implements MAC layer processing such as inserting CRC and Ethernet preamble delimiter.

[0122] (2) Rx direction: Mac_rx is the reverse operation of Mac_tx.

[0123] Furthermore, the system sets an alarm process, the specific process is as follows:

[0124] (1) After receiving the LOS (Loss of Signal) and LOF (Loss of Frame) signals, the local device pulls up the LocalFault (local fault) signal, stops sending data, and sends a RemoteFault (remote fault) sequence to the outside;

[0125] (2) After receiving RemoteFault, the peer device raises the RemoteFault signal and sends an Idle sequence.

[0126] (3) After the local device receives a certain amount of IDLE (idle state) sequences and no longer receives fault sequences, a linkup (reconnection) occurs.

[0127] Specifically, a register switch is used to control whether the alarm is sent. The sending switch is turned on by default, and the status of the RemoteFault and LocalFault signals are connected to the register for observation.

[0128] RemoteFault Sequence: 0x0200009C

[0129] LocalFault Sequence: 0x0100009C

[0130] After an alarm is detected, normal frames cannot be blocked. All frames in the fifo (First In First Out) buffer queue need to be read out but not sent to the line. At the same time, the current frame must be transmitted before the corresponding alarm sequence is sent.

[0131] In summary, the present invention provides a data transmission method and system for an Ethernet media access control layer, the method comprising: in the data receiving direction, receiving a serial data stream from the physical layer, converting it into parallel data of a set bit width through a serial-to-parallel converter, performing bit width conversion on the parallel data and adding an enable control signal, descrambling, sampling, and latching the data through an Ethernet physical layer receiver, and then decoding and converting the data format through a decoder and transmitting it to a receiver of the media access control layer. The inverse operation of the receiving direction is performed in the sending direction. The present invention uses a synchronous GearBox to replace an asynchronous GearBox, and adds an enable control signal, which solves the problem of an effective signal gap on the encoding side after the synchronous GearBox replaces the asynchronous GearBox, and can reduce the MAC delay value at the same time.

[0132] Corresponding to the above method, the present invention also provides a system, which includes a computer device, the computer device includes a processor and a memory, the memory stores computer instructions, the processor is used to execute the computer instructions stored in the memory, and when the computer instructions are executed by the processor, the system implements the steps of the method described above.

[0133] The embodiment of the present invention also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned edge computing server deployment method are implemented. The computer-readable storage medium can be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0134] It should be understood by those skilled in the art that the exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0135] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention.

[0136] In the present invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with features of other embodiments or replace features of other embodiments.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data receiving method of an Ethernet media access control layer, characterized in that: The method comprises the following steps: Receiving a serial data stream from a physical medium layer by a high-speed transceiver interface, wherein the serial data stream has a first set bit width; The serial data stream is converted into a first parallel data stream of a second set bit width by a serial-to-parallel converter, wherein the serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to perform data stream rate conversion; Converting the second parallel data stream of the set bit width into a second parallel data stream of the third set bit width, and adding an enable control signal to indicate valid data headers and data content in the second parallel data stream; the second parallel data stream meets the coding processing standard requirements of the Ethernet physical layer receiver; The Ethernet physical layer receiver descrambles and samples the second parallel data stream, and latches the correct data header and data content; Outputting the descrambled second parallel data stream to a decoder and converting it into a third parallel data stream in a standard interface format that meets the requirements of the media access control layer; inserting a cyclic redundancy check module into the media access control layer interface to detect whether the data packet contains error information; Converting the third parallel data stream into the second set bit width; The receiver module of the media access control layer converts the third parallel data stream into a standard protocol format; the standard interface format is XGMII, and the standard protocol format is AXI.

2. The data receiving method of the Ethernet media access control layer according to claim 1, characterized in that: The first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter is a SerDes converter.

3. The data receiving method of the Ethernet media access control layer according to claim 1, characterized in that: The Ethernet physical layer receiver includes: a descrambling module, a PRBCheck module, a frame synchronization detection module, a bit error rate monitoring module and a WatchDog module.

4. A data transmission method of Ethernet media access control layer, characterized in that: The method comprises the following steps: The third parallel data stream is received by the media access control layer interface, and the third parallel data stream is converted from the standard protocol format to the standard interface format, wherein the third parallel data stream has a second set bit width; a cyclic redundancy check module is inserted into the media access control layer interface to detect whether the data packet contains error information; the standard interface format is XGMII, and the standard protocol format is AXI; Converting the third parallel data stream from the second set bit width to a third set bit width; Transmitting the third parallel data stream of the third set bit width to an encoder to convert it into a second parallel data stream; scrambling the second parallel data stream via an Ethernet physical layer transmitter; Converting the second parallel data stream of the third set bit width into a first parallel data stream of the second set bit width, and adding an enable control signal to indicate valid data headers and data content in the first parallel data stream; The first parallel data stream is converted into a serial data stream with a first set bit width by a serial-to-parallel converter and sent to a high-speed transceiver interface; the serial-to-parallel converter uses a GearBox module based on synchronous clocks on both sides to convert the data stream rate.

5. The data transmission method of the Ethernet media access control layer according to claim 4, characterized in that: The first set bit width is 1 bit, the second set bit width is 32 bits, and the third set bit width is 64 bits; the serial-to-parallel converter is a SerDes converter.

6. The method for sending data at the Ethernet media access control layer according to claim 4, characterized in that: The Ethernet physical layer transmitter includes: a pseudo-random code module and a scrambling code module.

7. A data transmission system for Ethernet media access control layer, comprising a processor and a memory, the system is used for receiving and sending data at the media access control layer in Ethernet, characterized in that: The memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps of the method as claimed in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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