Electrostatic protection device and electrostatic protection circuit

Abstract

The present application relates to an electrostatic protection device and an electrostatic protection circuit. The electrostatic protection device includes: a substrate; an isolation ring, arranged in the substrate; an isolation ring lead-out area is provided in the isolation ring, and an isolation ring heavily doped area is provided in the isolation ring lead-out area; a transistor area is provided in the substrate inside the isolation ring and is spaced apart from the isolation ring; a first well area is provided in the substrate between the isolation ring and the transistor area, and is spaced apart from the isolation ring and the transistor area; a first heavily doped area is provided in the first well area. The present application can improve the holding current of the electrostatic protection device and improve the latch protection performance.

Description

Technical Field

[0001] The present application relates to the technical field of electrostatic protection for integrated circuits, and in particular to an electrostatic protection device and an electrostatic protection circuit. Background Art

[0002] Electrostatic protection has always been a major problem that plagues integrated circuit layout design. For this reason, countless electrostatic protection devices have been designed in combination with relevant processes and layout structures to ensure that integrated circuits (ICs) will not be damaged by electrostatic discharge (ESD) in actual use.

[0003] SCR (Silicon Controlled Rectifier) ​​is a commonly used ESD protection device and is widely used in various ESD protection designs. In the relevant technology, a composite structure combining SCR and PNP transistor is usually adopted to achieve latch immunity. However, this ESD protection device cannot achieve a higher holding current, resulting in the ESD protection device not being suitable for situations where the power supply is relatively large. In addition, while improving the protection capability of the ESD protection device, it cannot occupy too much chip layout area, otherwise it will significantly increase the chip cost, thereby limiting the promotion and application of the chip. Summary of the invention

[0004] Based on this, it is necessary to provide an electrostatic protection device and an electrostatic protection circuit to address at least one of the above problems.

[0005] In order to achieve the above-mentioned purpose or other purposes, in a first aspect, the present application provides an electrostatic protection device, the electrostatic protection device comprising:

[0006] a substrate having a first conductivity type;

[0007] An isolation ring is arranged in the substrate; an isolation ring lead-out region is arranged in the isolation ring, and an isolation ring heavily doped region is arranged in the isolation ring lead-out region;

[0008] A transistor region is disposed in the substrate inside the isolation ring and spaced apart from the isolation ring;

[0009] A first well region is provided in the substrate between the isolation ring and the transistor region, and is spaced apart from the isolation ring and the transistor region; a first heavily doped region is provided in the first well region;

[0010] The first well region and the isolation ring heavily doped region both have a first conductivity type; the isolation ring, the isolation ring lead-out region and the first heavily doped region all have a second conductivity type; the second conductivity type is opposite to the first conductivity type.

[0011] In one embodiment, the substrate in the transistor region is provided with a second well region and a third well region arranged at intervals along a first direction; the second well region is provided with a second heavily doped region; the third well region is provided with a third heavily doped region;

[0012] The second well region, the second heavily doped region and the third heavily doped region all have the first conductivity type; the third well region has the second conductivity type;

[0013] The first direction is perpendicular to a thickness direction of the substrate.

[0014] In one embodiment, the number of the first well regions is two, and the two first well regions are arranged at intervals along the first direction.

[0015] In one of the embodiments, the isolation ring heavily doped region is located on the ring segment of the isolation ring in the first direction;

[0016] And / or, the isolation ring heavily doped region is located on a ring segment of the isolation ring in a second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate.

[0017] In one embodiment, the first well region is disposed on both sides of the transistor region along the first direction and on both sides of the transistor region along the second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate.

[0018] In one embodiment, the first well region is ring-shaped and surrounds the transistor region.

[0019] In one embodiment, the number of the first well regions is four, wherein two of the first well regions are located on both sides of the transistor region along the first direction, and the other two of the first well regions are located on both sides of the transistor region along the second direction.

[0020] In one embodiment, the number of the isolation ring heavily doped regions is multiple, and the multiple isolation ring heavily doped regions are arranged at intervals along the extension direction of the isolation ring lead-out region;

[0021] The first well region is located in the substrate between the isolation ring heavily doped region and the transistor region.

[0022] In one embodiment, the number of the second well region and the number of the third well region are both plural, and the difference between the number of the second well region and the number of the third well region is 1;

[0023] A plurality of the second well regions and a plurality of the third well regions are alternately arranged, and each of the third well regions is located between two adjacent second well regions.

[0024] In one embodiment, the isolation ring lead-out region, the third heavily doped region, and the isolation ring heavily doped region are all electrically connected to the anode;

[0025] The first heavily doped region and the second heavily doped region are both electrically connected to a cathode.

[0026] In a second aspect, the present application provides an electrostatic protection circuit, comprising a plurality of electrostatic protection devices according to the first aspect, wherein the plurality of electrostatic protection devices are connected in series.

[0027] The above-mentioned electrostatic protection device and electrostatic protection circuit, through the isolation ring heavily doped area, isolation ring, part of the substrate, the first well area and the first heavily doped area, together constitute a thyristor. On the one hand, the thyristor and the transistor in the transistor area are independent of each other (the two have no shared doping area or well area), and the thyristor and the transistor can be designed independently. In this way, after the transistor is triggered, it enters the conduction area, the slope of the conduction area increases and the resistance decreases. The transistor needs to be turned on to a higher current before the voltage reaches the trigger voltage of the thyristor. After the thyristor is triggered, it enters Snap back, which can increase the power of the thyristor trigger point while the thyristor trigger voltage remains unchanged. After Snap back, the maintenance current is also increased accordingly, so that the electrostatic protection device can be used in situations where the power of the power supply is relatively large. On the other hand, by parasitizing part of the thyristor on the isolation ring, a more streamlined structural design can be achieved, the size of the electrostatic protection device can be reduced, and it is conducive to the promotion and application of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a structural schematic diagram of an ESD protection device in the related art;

[0030] Figure 2 for Figure 1 Equivalent circuit diagram of

[0031] Figure 3A schematic top view of an electrostatic protection device provided in one embodiment of the present application;

[0032] Figure 4 for Figure 3 AA cross-sectional diagram of ;

[0033] Figure 5 for Figure 4 A partial schematic diagram of

[0034] Figure 6 for Figure 3 Equivalent circuit diagram of

[0035] Figure 7 A schematic top view of another electrostatic protection device provided in one embodiment of the present application;

[0036] Figure 8 A schematic top view of another electrostatic protection device provided in one embodiment of the present application;

[0037] Fig. 9 A schematic top view of another electrostatic protection device provided in an embodiment of the present application;

[0038] Fig.10 for Figure 3 TLP curve diagram of the electrostatic protection device and the comparative example;

[0039] Fig.11 for Figure 3 TLP curves of ESD protection devices in different sizes;

[0040] Fig.12 A TLP curve diagram provided in one embodiment of the present application;

[0041] Fig.13 An equivalent circuit diagram of an electrostatic protection circuit provided in one embodiment of the present application.

[0042] Description of reference numerals:

[0043] 1'-ESD protection device; 10'-substrate; 101'-first P-doped region; 102'-second P-doped region; 103'-first N-doped region; 104'-second N-doped region; 105'-P+ doped region; 106'-third N-doped region;

[0044] 1-electrostatic protection device; 10-substrate; 101-buried layer; 102-isolation ring; 103-isolation ring lead-out area; 1031-first ring segment; 1032-second ring segment; 104-first well region; 105-first heavily doped region; 106-second well region; 107-second heavily doped region; 108-third well region; 109-third heavily doped region; 110-isolation ring heavily doped region; 20-anode; 30-cathode; 40-thyristor. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0051] Reference Figure 1 and Figure 2 , Figure 1 The figure shows a schematic diagram of the structure of an ESD protection device in the related art. Figure 2The equivalent circuit diagram of the ESD protection device is shown. The substrate 10' of the ESD protection device 1' is provided with a first P-doped region 101', a first N-doped region 103', a second P-doped region 102' and a third N-doped region 106' arranged at intervals, and the second P-doped region 102' is provided with a second N-doped region 104' and a P+-doped region 105' arranged at intervals. The first P-doped region 101', the first N-doped region 103' and the second P-doped region 102' together constitute a PNP transistor, the second P-doped region 102', the second N-doped region 104', the P+-doped region 105' and the third N-doped region 106' together constitute an SCR, and the PNP transistor and the SCR share the second P-doped region 102'.

[0052] However, in the ESD protection device 1', since the PNP transistor and the SCR share the second P-doped region 102', the PNP transistor cannot implement a multi-finger design. If the PNP transistor is to be designed with multiple fingers, the SCR part will also change accordingly, which is equivalent to being unable to change the PNP transistor or the SCR alone, so the minimum unit is a composite structure of a PNP transistor and SCR with one finger.

[0053] It can be understood that multi-finger design is a method to change the slope of the discharge interval on the TLP (Transmission Line Pulse) curve of the ESD protection device. If the PNP transistor in the ESD protection device cannot implement a multi-finger design, then the ESD protection device cannot achieve a higher holding current, thereby affecting the latch protection performance, resulting in the ESD protection device being unsuitable for use in situations where the power supply is relatively large.

[0054] In addition, while improving the protection capability of ESD protection devices, they cannot occupy too much chip layout area, otherwise the chip cost will increase significantly, thereby limiting the promotion and application of the chip.

[0055] In view of this, in order to solve at least one of the above problems, an embodiment of the present application provides an electrostatic protection device and an electrostatic protection circuit.

[0056] In a first aspect, the present application provides an electrostatic protection device, referring to Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the electrostatic protection device 1 includes a substrate 10, a buried layer 101, an isolation ring 102, a first well region 104 and a transistor region (not shown in the figure), wherein the buried layer 101, the isolation ring 102, the first well region 104 and the transistor region are all arranged inside the substrate 10. The transistor region can be understood as: a region where a PNP transistor is arranged.

[0057] The substrate 10 has a first conductivity type. The material of the substrate 10 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), etc., or other materials known to those skilled in the art, and the substrate 10 can provide a supporting foundation for the structural layer on the substrate 10.

[0058] The buried layer 101 has a second conductivity type. The second conductivity type is opposite to the first conductivity type. In the embodiment of the present application, the first conductivity type is P type and the second conductivity type is N type.

[0059] The isolation ring 102 is located on one side of the buried layer 101 along the thickness direction of the substrate 10, and one end of the isolation ring 102 close to the buried layer 101 is connected to the buried layer 101. In this way, the isolation ring 102 and the buried layer 101 can enclose an isolation area, and the main device of the electrostatic protection device 1 can be arranged in the isolation area. In addition, an isolation ring lead-out area 103 is also provided in the isolation ring 102, and an isolation ring heavily doped area 110 is provided in the isolation ring lead-out area 103. The isolation ring heavily doped area 110 has a first conductivity type, and the isolation ring 102 and the isolation ring lead-out area 103 both have a second conductivity type. The doping concentration of the isolation ring heavily doped area 110 is greater than the doping concentration of the isolation ring lead-out area 103, and the doping concentration of the isolation ring lead-out area 103 is greater than the doping concentration of the isolation ring 102. It should be noted that the isolation ring lead-out region 103 is located "inside" the isolation ring 102, which means that the isolation ring lead-out region 103 is located in the body of the isolation ring 102, not that the isolation ring lead-out region 103 is located on the inner side of the isolation ring 102. It is understandable that N-type ions can be implanted into the substrate 10 by ion implantation to form the isolation ring 102 and the isolation ring lead-out region 103, respectively.

[0060] The first well region 104 is disposed in the substrate 10 and is located between the isolation ring 102 and the transistor region. At the same time, the first well region 104 is spaced apart from the isolation ring 102 and the transistor region. A first heavily doped region 105 is disposed in the first well region 104. The first well region 104 has a first conductivity type, and the first heavily doped region 105 has a second conductivity type.

[0061] Combination Figure 3 and Figure 4 As shown, the isolation ring heavily doped region 110, the isolation ring 102, a portion of the substrate 10, the first well region 104 and the first heavily doped region 105 together constitute the thyristor 40, wherein: Figure 3 The arrows in Figure 4 The solid arrow in shows the path of the thyristor 40 .

[0062] The electrostatic protection device 1 provided in the embodiment of the present application makes the isolation ring heavily doped region 110, the isolation ring 102, a part of the substrate 10, the first well region 104 and the first heavily doped region 105 together constitute the thyristor 40. On the one hand, the thyristor 40 and the transistors in the transistor region are independent of each other (the two have no shared doping region or well region), so that the thyristor 40 and the transistors can be designed independently of each other.

[0063] In this way, after the transistor is triggered, it enters the conduction region, the slope of the conduction region increases and the resistance decreases, and the transistor needs to conduct to a higher current before the voltage reaches the trigger voltage of the thyristor 40. After the thyristor 40 is triggered, it enters snap back, and the power at the trigger point of the thyristor 40 can be increased while the trigger voltage of the thyristor 40 remains unchanged. After snap back, the maintenance current also increases accordingly, so that the electrostatic protection device 1 can be applied to the case where the power of the power supply is relatively large.

[0064] On the other hand, by parasitizing a part of the thyristor 40 on the isolation ring 102, a more streamlined structural design can be achieved, and the size of the electrostatic protection device 1 can be reduced, which is beneficial to the promotion and application of the chip.

[0065] In one embodiment, the substrate 10 in the transistor region is provided with a second well region 106 and a third well region 108 arranged at intervals along the first direction a. The second well region 106 is provided with a second heavily doped region 107, and the third well region 108 is provided with a third heavily doped region 109. The second well region 106, the second heavily doped region 107, and the third heavily doped region 109 all have the first conductivity type, and the third well region 108 has the second conductivity type. The first direction a is perpendicular to the thickness direction of the substrate 10.

[0066] Combination Figure 3 , Figure 4 and Figure 5 As shown, the second heavily doped region 107, the second well region 106, a portion of the substrate 10, the third well region 108 and the third heavily doped region 109 together constitute a PNP transistor. Figure 4 The hollow arrow in the figure indicates the path of the PNP transistor. In this embodiment, the equivalent circuit diagram of the PNP transistor and the thyristor 40 is as follows: Figure 6 shown.

[0067] In other embodiments, an epitaxial layer with a first conductivity type may be disposed on the substrate 10 , and the buried layer 101 , the isolation ring 102 , the first well region 104 and the transistor region are all disposed in the epitaxial layer.

[0068] In the embodiment of the present application, the isolation ring lead-out region 103 is annular, and the isolation ring lead-out region 103 is arranged outside the first well region 104 and the transistor region. That is, the isolation ring 102 is arranged outside the first well region 104 and the transistor region, and the isolation ring lead-out region 103 is also arranged outside the first well region 104 and the transistor region.

[0069] Specifically, the isolation ring lead-out area 103 includes two first ring segments 1031 and two second ring segments 1032, which are arranged alternately in sequence along the circumferential direction of the isolation ring 102 and connected end to end, wherein the two first ring segments 1031 are arranged opposite to each other in the first direction a and extend along the second direction b. The two second ring segments 1032 are arranged opposite to each other in the second direction b and extend along the first direction a. The second direction b is perpendicular to the first direction a and the thickness direction of the substrate 10. Here, "arranged alternately in sequence and connected end to end" means that the isolation ring lead-out area 103 is arranged in this "first ring segment 1031, second ring segment 1032, first ring segment 1031, second ring segment 1032" arrangement mode, and together form a ring shape, and are connected end to end in sequence. It should be noted that the isolation ring lead-out region 103 may also be a discontinuous structure, that is, a plurality of isolation ring lead-out regions 103 arranged at intervals are provided in the extending direction of the isolation ring 102 .

[0070] It can be understood that the number of the first well region 104 can be one.

[0071] In one example, the first well region 104 can be located on one side of the transistor region in the first direction a. In this case, the isolation ring heavily doped region 110 is located on at least one first ring segment 1031, and the first ring segment 1031 and the first well region 104 are located on the same side of the transistor region in the first direction a.

[0072] In another example, the first well region 104 can be located on one side of the transistor region in the second direction b. In this case, the isolation ring heavily doped region 110 is located on at least one second ring segment 1032, and the second ring segment 1032 and the first well region 104 are located on the same side of the transistor region in the second direction b.

[0073] In one embodiment, referring to Figure 3 and Figure 4 As shown, the number of first well regions 104 is two, and the two first well regions 104 are arranged at intervals along the first direction b. That is, the transistor region is located between the two first well regions 104. In this way, thyristors 40 can be formed on both sides of the transistor region along the first direction a, increasing the number of thyristors 40 and further improving the performance of the electrostatic protection device 1.

[0074] In one embodiment, referring to Figure 3As shown in FIG. 1 , the isolation ring heavily doped region 110 is located on the ring segment of the isolation ring 102 in the first direction a. That is, the isolation ring heavily doped region 110 is disposed in the first ring segment 1031 of the isolation ring lead-out region 103. The path of the thyristor 40 formed by the isolation ring heavily doped region 110, the isolation ring 102, a portion of the substrate 10, the first well region 104 and the first heavily doped region 105 is shown in FIG. Figure 3 As indicated by the arrow in .

[0075] In another embodiment, referring to Figure 7 As shown in FIG. 1 , the isolation ring heavily doped region 110 is located on the ring segment of the isolation ring 102 in the second direction b. That is, the isolation ring heavily doped region 110 is disposed in the second ring segment 1032 of the isolation ring lead-out region 103. The path of the thyristor 40 formed by the isolation ring heavily doped region 110, the isolation ring 102, a portion of the substrate 10, the first well region 104 and the first heavily doped region 105 is shown in FIG. Figure 7 As shown by the arrow in . The second direction b is perpendicular to the first direction a and the thickness direction of the substrate 10 .

[0076] In one embodiment, there are multiple isolation ring heavily doped regions 110, and the multiple isolation ring heavily doped regions 110 are arranged at intervals along the extension direction of the isolation ring lead-out region 103. The first well region 104 is located in the substrate 10 between the isolation ring heavily doped region 110 and the transistor region.

[0077] In one example, referring to Figure 3 As shown, a plurality of isolation ring heavily doped regions 110 are arranged in the first ring segment 1031 of the isolation ring lead-out region 103, and the plurality of isolation ring heavily doped regions 110 are arranged at intervals along the second direction b. In this arrangement, by adjusting the extension length L of the isolation ring heavily doped region 110 in the second direction b and the spacing S between adjacent isolation ring heavily doped regions 110, the conduction cross section of the thyristor 40 can be adjusted to change the current discharge capacity of the thyristor 40, thereby achieving adjustment of the performance of the electrostatic protection device 1.

[0078] In another embodiment, referring to Figure 8 As shown, the isolation ring heavily doped region 110 in the first ring segment 1031 of the isolation ring lead-out region 103 is a continuous structure, that is, an isolation ring heavily doped region 110 is arranged in each first ring segment 1031, and the isolation ring heavily doped region 110 extends along the second direction b. In this arrangement, the preparation of the isolation ring heavily doped region 110 can be made simpler, and the preparation difficulty of the electrostatic protection device 1 can be reduced.

[0079] In one embodiment, referring to Fig. 9As shown, first well regions 104 are provided on both sides of the transistor region along the first direction a and on both sides of the transistor region along the second direction b. The second direction b is perpendicular to the first direction a and the thickness direction of the substrate 10. It can be understood that, in this arrangement, isolation ring heavily doped regions 110 are provided on both sides of the transistor region along the first direction a and on both sides of the transistor region along the second direction b, so that thyristors 40 can be formed around the PNP transistor, the number of thyristors 40 is increased, and the performance of the electrostatic protection device 1 is further improved.

[0080] In one example, referring to Fig. 9 As shown, the first well region 104 is annular and surrounds the transistor region. The first heavily doped region 105 is also annular, so that multiple thyristors 40 can be arranged around the PNP transistor.

[0081] In another example, the number of the first well regions 104 is four, wherein two first well regions 104 are located on both sides of the transistor region along the first direction a, and the other two first well regions 104 are located on both sides of the transistor region along the second direction b. In this way, the first well regions 104 around the PNP transistor are intermittently arranged, and multiple thyristors 40 can also be arranged around the PNP transistor.

[0082] In one embodiment, referring to Figure 3 and Fig. 9 As shown, the number of the second well regions 106 and the number of the third well regions 108 are both multiple, and the difference between the number of the second well regions 106 and the number of the third well regions 108 is 1. That is, the number of the second well regions 106 is always one more than the number of the third well regions 108. The multiple second well regions 106 and the multiple third well regions 108 are alternately arranged, and each third well region 108 is located between two adjacent second well regions 106.

[0083] Since one third well region 108 can form two PNP transistors with two adjacent second well regions 106, this arrangement can form multiple PNP transistors. In this way, a multi-finger design of the thyristor 40 and the PNP transistor can be realized, so that the conduction condition of the PNP transistor after being triggered can be adjusted.

[0084] Specifically, after the PNP transistor is triggered, it enters the conduction region, the slope of the conduction region increases and the resistance decreases. The PNP transistor needs to conduct to a higher current before the voltage reaches the trigger voltage of the thyristor 40. According to the principle of power (P=U*I) continuity on the TLP curve, the thyristor 40 enters snap back after being triggered, and the power at the holding point is equivalent to the power at the trigger point of the thyristor 40. When the trigger voltage of the thyristor 40 remains unchanged, the current at the holding point increases due to the design of more fingers of the PNP transistor, so the power at the trigger point of the thyristor 40 also increases. After snap back, the holding current also increases accordingly, so that the electrostatic protection device 1 can be applied to the case where the power of the power supply is relatively large.

[0085] It is understandable that, in the specific setting process, the number of fingers of the PNP transistor can be adjusted by adjusting the number of the second well region 106 and the third well region 108, so as to realize the electrostatic protection device 1 with different holding currents and more flexible design. The embodiment of the present application does not limit the number of the second well region 106 and the third well region 108.

[0086] Reference Figure 5 As shown, in the embodiment of the present application, the breakdown voltage of the thyristor 40 can be adjusted by adjusting the distance a between the inner side of the isolation ring heavily doped region 110 and the inner side of the isolation ring 102, the distance b between the isolation ring 102 and the first well region 104, and the distance c between the side of the first heavily doped region 105 close to the isolation ring 102 and the side of the first well region 104 close to the isolation ring 102, thereby adjusting the trigger voltage of the thyristor 40. The breakdown voltage of the PNP transistor can be adjusted by adjusting the distance d between the side of the second heavily doped region 107 close to the third well region 108 and the side of the second well region 106 close to the third well region 108, the distance e between the second well region 106 and the third well region 108, and the distance f between the side of the third heavily doped region 109 close to the second well region 106 and the side of the third well region 108, thereby adjusting the trigger voltage of the PNP transistor.

[0087] For example, at least one of a, b and c, and at least one of d, e and f can be adjusted so that the breakdown voltage of the thyristor 40 is greater than the breakdown voltage of the PNP transistor. Figure 6 As shown, the PNP transistor is triggered first and then turned on for discharge. As the energy of the ESD signal gradually increases, after the PNP transistor is turned on to a certain extent, the thyristor 40 path is turned on, so that the PNP transistor path and the thyristor 40 path discharge current at the same time, thereby increasing the discharge current and further improving the electrostatic protection performance.

[0088] In one embodiment, referring to Figure 4As shown, the isolation ring lead-out region 103, the third heavily doped region 109 and the isolation ring heavily doped region 110 are all electrically connected to the anode 20. The first heavily doped region 105 and the second heavily doped region 107 are all electrically connected to the cathode 30. It can be understood that a first contact hole can be provided on the isolation ring lead-out region 103, the third heavily doped region 109 and the isolation ring heavily doped region 110, and the isolation ring lead-out region 103, the third heavily doped region 109 and the isolation ring heavily doped region 110 are electrically connected to the anode 20 through the first contact hole; a second contact hole can be provided on the first heavily doped region 105 and the second heavily doped region 107, and the first heavily doped region 105 and the second heavily doped region 107 are electrically connected to the cathode 30 through the second contact hole.

[0089] Reference Fig.10 , shown is a TLP curve diagram of the electrostatic protection device 1 provided in the embodiment of the present application and the comparative example. It can be seen from the figure that compared with the SCR (thyristor), the PNP transistor + SCR (thyristor 40) structure has a higher holding current and holding voltage, and both improvements are beneficial to latch protection; compared with the PNP transistor, the curve of the PNP transistor + SCR (thyristor 40) structure has a narrower design window because of the snap back. In addition, since the PNP transistor and the thyristor 40 discharge current in two paths at the same time, the electrostatic protection device 1 (PNP transistor + thyristor) provided in the embodiment of the present application can achieve a higher discharge current.

[0090] Reference Fig.11 As shown, it is a TLP curve diagram of the electrostatic protection device 1 provided in the embodiment of the present application at different sizes. It can be seen from the figure that when the PNP transistor under different TW (total width, TW = finger number x finger width) is turned on to discharge the ESD current, its slope is different. The larger the TW, the greater the slope, and the greater the current used to reach the thyristor 40 (SCR) trigger voltage point, and the corresponding TLP power is also greater. Since the power of adjacent points on the IV curve cannot change suddenly under the TLP test, when the thyristor 40 is triggered to generate a snap back, the holding current of the corresponding point is also higher, thereby having a higher holding current. As shown Fig.10 As shown in the PNP TLP curve, for the structure that cannot implement multi-finger design, the maintenance current is not significantly improved. Therefore, after the PNP transistor is fully turned on, the current capability is also smaller than the structure with multi-finger design.

[0091] On the other hand, the more fingers a PNP transistor has, the better it is. If the PNP transistor is not designed properly, the PNP transistor will experience secondary breakdown (thermal breakdown) while the voltage has not yet reached the trigger voltage of the thyristor 40. Fig.12 As shown in the figure, in this case, the PNP transistor and the thyristor 40 cannot be turned on at the same time.

[0092] In a second aspect, the present application provides an electrostatic protection circuit, referring to Fig.13 As shown, the electrostatic protection circuit includes a plurality of electrostatic protection devices 1 in the first aspect, and the plurality of electrostatic protection devices 1 are connected in series. The electrostatic protection circuit includes an anode and a cathode, wherein the isolation ring lead-out region 103, the third heavily doped region 109 and the isolation ring heavily doped region 110 are all electrically connected to the anode. The first heavily doped region 105 and the second heavily doped region 107 are both electrically connected to the cathode.

[0093] It is understandable that protection at different voltage levels can be achieved by adjusting the number of electrostatic protection devices 1. The embodiment of the present application does not limit the number of electrostatic protection devices 1.

[0094] The above-mentioned electrostatic protection circuit makes the isolation ring heavily doped region 110, the isolation ring 102, part of the substrate 10, the first well region 104 and the first heavily doped region 105 together constitute the thyristor 40. On the one hand, the thyristor 40 and the transistor are independent of each other (the two have no shared doping region or well region), and the thyristor 40 and the transistor can be designed independently. In this way, after the transistor is triggered, it enters the conduction region, the slope of the conduction region increases and the resistance decreases. The transistor needs to be turned on to a higher current before the voltage reaches the trigger voltage of the thyristor 40. After the thyristor 40 is triggered, it enters snap back, which can increase the power of the thyristor 40 trigger point when the trigger voltage of the thyristor 40 remains unchanged. After snap back, the maintenance current is also increased accordingly, so that the electrostatic protection device 1 can be suitable for the situation where the power of the power supply is relatively large. On the other hand, by parasitizing a part of the thyristor 40 on the isolation ring 102, a more streamlined structural design can be achieved, and the size of the electrostatic protection device 1 can be reduced, which is conducive to the promotion and application of the chip.

[0095] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0096] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An electrostatic protection device, characterized in that: include: a substrate having a first conductivity type; An isolation ring is arranged in the substrate; an isolation ring lead-out region is arranged in the isolation ring, and an isolation ring heavily doped region is arranged in the isolation ring lead-out region; A transistor region is disposed in the substrate inside the isolation ring and spaced apart from the isolation ring; A first well region is provided in the substrate between the isolation ring and the transistor region, and is spaced apart from the isolation ring and the transistor region; a first heavily doped region is provided in the first well region; The first well region and the isolation ring heavily doped region both have a first conductivity type; the isolation ring, the isolation ring lead-out region and the first heavily doped region all have a second conductivity type; the second conductivity type is opposite to the first conductivity type.

2. The electrostatic protection device according to claim 1, characterized in that: The substrate in the transistor region is provided with a second well region and a third well region arranged at intervals along a first direction; the second well region is provided with a second heavily doped region; the third well region is provided with a third heavily doped region; The second well region, the second heavily doped region and the third heavily doped region all have the first conductivity type; the third well region has the second conductivity type; The first direction is perpendicular to a thickness direction of the substrate.

3. The electrostatic protection device according to claim 2, characterized in that: The number of the first well regions is two, and the two first well regions are arranged at intervals along the first direction.

4. The electrostatic protection device according to claim 3, characterized in that: The isolation ring heavily doped region is located on the ring segment of the isolation ring in the first direction; And / or, the isolation ring heavily doped region is located on a ring segment of the isolation ring in a second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate.

5. The electrostatic protection device according to claim 2, characterized in that: The first well regions are disposed on both sides of the transistor region along the first direction and on both sides of the transistor region along the second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate.

6. The electrostatic protection device according to claim 5, characterized in that: The first well region is ring-shaped and surrounds the transistor region.

7. The electrostatic protection device according to claim 5, characterized in that: The number of the first well regions is four, wherein two of the first well regions are located on both sides of the transistor region along the first direction, and the other two of the first well regions are located on both sides of the transistor region along the second direction.

8. The electrostatic protection device according to any one of claims 1 to 7, characterized in that: There are multiple isolation ring heavily doped regions, and the multiple isolation ring heavily doped regions are arranged at intervals along the extension direction of the isolation ring lead-out region; The first well region is located in the substrate between the isolation ring heavily doped region and the transistor region.

9. The electrostatic protection device according to any one of claims 2 to 6, characterized in that: The number of the second well region and the number of the third well region are both plural, and the difference between the number of the second well region and the number of the third well region is 1; A plurality of the second well regions and a plurality of the third well regions are arranged alternately, and each of the third well regions is located between two adjacent second well regions.

10. The electrostatic protection device according to any one of claims 2 to 7, characterized in that: The isolation ring lead-out region, the isolation ring heavily doped region and the third heavily doped region are all electrically connected to the anode; The first heavily doped region and the second heavily doped region are both electrically connected to a cathode.

11. An electrostatic protection circuit, characterized in that: The invention comprises a plurality of electrostatic protection devices according to any one of claims 1 to 10, wherein the plurality of electrostatic protection devices are connected in series.

Images