Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The method comprises: providing a substrate, a surface of the substrate is formed with first interval layers arranged at intervals along a first direction and extending along a second direction, the first interval layers comprising first mask layers and first sidewall layers located on both sides of the first mask layers along the first direction; forming first sacrificial layers in gaps between the first interval layers; wherein surfaces of the first interval layers and the first sacrificial layers are flush; the first mask layers, the first sidewall layers and the first sacrificial layers constitute a first pattern layer; forming a second pattern layer on a surface of the first pattern layer; the second pattern layer comprises at least second sidewall layers arranged at intervals along the first direction and extending along a third direction; the first direction, the second direction and the third direction are any three directions in a plane of the substrate; transferring an initial pattern defined by the second sidewall layers and the first sidewall layers into the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor structure manufacturing technology, photoresist and mask layers are usually used in combination with photolithography and etching processes to form the desired pattern. However, due to the limitations of photolithography, the desired pattern is easily deviated, which affects the yield of semiconductor structure fabrication.

[0003] Taking the manufacturing of Dynamic Random Access Memory (DRAM) as an example, in the process of forming the capacitors in DRAM, Self-Aligned Quadruple Patterning (SAQP) is typically used for pattern transfer. As the critical dimension (CD) of the pattern continuously shrinks, the sidewalls are prone to tilting and collapsing during wet cleaning, leading to pattern damage and inaccurate transfer. Furthermore, as the process node shrinks, residual photoresist can easily remain in the gaps between the sidewalls after development, ultimately preventing the pattern from fully opening. Additionally, due to the limitations of photolithography, dummy holes are easily generated in the corners of the array area, causing abnormal patterns at the edges of the array area, thus affecting the performance and fabrication yield of the DRAM. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided, the surface of which is formed with a first spacer layer spaced apart along a first direction and extending along a second direction, the first spacer layer including a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction;

[0007] A first sacrificial layer is formed in the gaps between the first spacer layers; wherein the first spacer layers are flush with the surface of the first sacrificial layer; the first mask layer, the first sidewall layer and the first sacrificial layer constitute a first pattern layer;

[0008] A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least two sidewall layers spaced apart along the first direction and extending along a third direction; the first direction, the second direction, and the third direction are any three directions in the plane where the substrate is located;

[0009] The initial pattern defined by the second sidewall layer and the first sidewall layer is transferred to the substrate.

[0010] In some embodiments, a first sacrificial layer is formed in the gaps between the first spacer layers, including:

[0011] A first initial sacrificial layer is formed in the gaps between the first spacer layers and on the surface of the first spacer layer;

[0012] The first initial sacrificial layer is etched back until the surface of the first mask layer is exposed, thus forming the first sacrificial layer.

[0013] In some embodiments, the first spacer layer is formed by the following steps:

[0014] A first initial mask layer and a second initial mask layer are sequentially formed on the surface of the substrate;

[0015] The second initial mask layer is etched to form a second initial spacer layer spaced apart along the first direction;

[0016] A first covering layer is formed on the sidewall of the second initial spacer layer;

[0017] The first initial mask layer is etched through the first cover layer to form the first mask layer spaced apart along the first direction;

[0018] A second initial cover layer is formed covering the first mask layer and the substrate;

[0019] The second initial cover layer located on the top surface of the first mask layer and the surface of the substrate is removed, and the second initial cover layer located on the sidewall of the first mask layer is retained to form the first sidewall layer.

[0020] In some embodiments, the second initial spacer layer is formed by the following steps:

[0021] A first photoresist layer having a first preset pattern is formed on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along the first direction and extending along the second direction, and the first sub-patterns expose a portion of the second initial mask layer;

[0022] Remove the second initial mask layer exposed by the first sub-pattern to form the second initial spacer layer.

[0023] In some embodiments, the second pattern layer is formed by the following steps:

[0024] A second spacer layer is formed on the surface of the first pattern layer at intervals along the first direction. The second spacer layer includes a second mask layer and second sidewall layers located on both sides of the second mask layer along the first direction.

[0025] A second sacrificial layer is formed in the gaps between the second spacer layers, wherein the second spacer layers are flush with the surface of the second sacrificial layer; the second mask layer, the second sidewall layer and the second sacrificial layer constitute the second pattern layer.

[0026] In some embodiments, forming a second sacrificial layer in the gaps between the second spacer layers includes:

[0027] A second initial sacrificial layer is formed in the gaps between the second spacers and on the surface of the second spacers;

[0028] The second initial sacrificial layer is etched back until the surface of the second mask layer is exposed, forming the second sacrificial layer.

[0029] In some embodiments, the second spacer layer is formed by the following steps:

[0030] A third initial mask layer and a fourth initial mask layer are sequentially formed on the surface of the first pattern layer;

[0031] The fourth initial mask layer is etched to form a fourth initial spacer layer spaced apart along the first direction;

[0032] A third covering layer is formed on the sidewall of the fourth initial spacer layer;

[0033] The third initial mask layer is etched through the third capping layer to form the second mask layer spaced apart along the first direction;

[0034] A fourth initial overlay layer is formed, covering the second mask layer and the first pattern layer;

[0035] The fourth initial cover layer located on the top surface of the second mask layer and the surface of the first pattern layer is removed, and the fourth initial cover layer located on the sidewall of the second mask layer is retained to form the second sidewall layer.

[0036] In some embodiments, the fourth initial spacer layer is formed by the following steps:

[0037] A second photoresist layer with a second preset pattern is formed on the surface of the fourth initial mask layer; wherein, the second preset pattern includes a plurality of second sub-patterns arranged sequentially along the first direction and extending along the third direction, and the second sub-patterns expose a portion of the fourth initial mask layer;

[0038] The fourth initial mask layer exposed by the second sub-pattern is removed to form the fourth initial spacer layer.

[0039] In some embodiments, the substrate includes an array region and a peripheral region, and after forming the second patterned layer, the method further includes:

[0040] A third mask layer is formed on the surface of the second patterned layer;

[0041] A third photoresist layer with a third preset pattern is formed on the surface of the third mask layer, wherein the third preset pattern includes a portion of the array region that is exposed away from the peripheral region;

[0042] The initial pattern is transferred to the substrate corresponding to the array region exposed by the third preset pattern.

[0043] In some embodiments, the first mask layer includes a first masking layer and a first anti-reflection layer;

[0044] The etching selectivity between the first sacrificial layer and the substrate is equal to the etching selectivity between the first antireflective layer and the substrate.

[0045] In some embodiments, the second mask layer includes a third masking layer and a third anti-reflection layer;

[0046] The etching selectivity between the second sacrificial layer and the substrate is equal to the etching selectivity between the third antireflective layer and the substrate.

[0047] In some embodiments, the substrate includes a fourth mask layer; transferring an initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate includes:

[0048] Using the first sidewall layer and the second sidewall layer as masks, the initial pattern is transferred to the fourth mask layer to form a fourth mask layer having the initial pattern; the initial pattern includes multiple third sub-patterns.

[0049] In some embodiments, the substrate further includes a substrate, and the fourth mask layer is located on the surface of the substrate; after forming the fourth mask layer having the initial pattern, the method further includes:

[0050] The exposed portion of the substrate of the third sub-pattern is removed to transfer the initial pattern into the substrate.

[0051] In some embodiments, the substrate further includes a stacked structure, the fourth mask layer being located on the surface of the stacked structure; after forming the fourth mask layer having the initial pattern, the method further includes:

[0052] Remove the exposed portion of the stacked structure of the third sub-pattern to transfer the initial pattern into the stacked structure.

[0053] In some embodiments, after forming the first patterned layer and before forming the second patterned layer, the method for forming the semiconductor structure further includes:

[0054] A first dielectric layer is formed on the surface of the first patterned layer.

[0055] In some embodiments, the initial pattern includes a capacitor hole pattern.

[0056] In a second aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a substrate; the substrate comprising an initial pattern; the initial pattern being defined by a first sidewall layer in a first pattern layer and a second sidewall layer in a second pattern layer;

[0057] Wherein, the first pattern layer is located on the surface of the substrate, and the first pattern layer includes a first spacer layer and a first sacrificial layer that are alternately arranged along a first direction and extend along a second direction; the first spacer layer is flush with the surface of the first sacrificial layer; the first spacer layer includes a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction;

[0058] The second pattern layer is located on the surface of the first pattern layer, and the second pattern layer includes at least two sidewall layers that are spaced apart along the first direction and extend along a third direction; the first direction, the second direction and the third direction are any three directions in the plane where the substrate is located.

[0059] In some embodiments, the second patterned layer includes a second spacer layer and a second sacrificial layer that are alternately arranged along the first direction and extend along the third direction; the second spacer layer is flush with the bottom surface of the second sacrificial layer; the second spacer layer includes a second mask layer and a second sidewall layer located on both sides of the second mask layer along the first direction.

[0060] In some embodiments, the substrate further includes a substrate and a stacked structure located on the surface of the substrate.

[0061] In some embodiments, the initial pattern includes a capacitor hole pattern.

[0062] The semiconductor structure and its formation method provided in this disclosure improve the accuracy of pattern transfer and thus improve the yield of semiconductor structure fabrication during the formation of the first pattern layer. In the process of forming the first pattern layer, a first sacrificial layer is formed in the gap between the first spacer layers. As a result, the first sidewall layer will not collapse or be damaged during the formation of the first pattern layer. Attached Figure Description

[0063] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0064] Figures 1a to 1c This is a schematic diagram of the semiconductor structure formation process in related technologies;

[0065] Figure 2 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0066] Figures 3a to 3z This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. Detailed Implementation

[0067] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0068] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0069] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0070] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0071] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0072] In related technologies, the SAQP process is typically used to transfer patterns and form capacitor holes in the formation process of capacitor transistors in dynamic random access memory. Figures 1a to 1c This is a schematic diagram of the semiconductor structure formation process in related technologies, such as... Figure 1a As shown, the semiconductor structure in the related technology is divided into an array area (AA) and a peripheral area (PA). The semiconductor structure in the related technology includes a substrate 10, a first patterned layer A located on the surface of the substrate 10, and the first patterned layer A includes a pattern along the edge of the substrate 10. Figure 1a The sidewalls 111 are spaced apart along the X-axis. In related technologies, the sidewalls 111 are prone to tilting and collapsing during wet cleaning during pattern transfer, which can lead to damage to the final pattern and inaccurate transfer. The same problem will occur when forming the second pattern layer on the surface of the first pattern layer A.

[0073] like Figure 1bAs shown, a second pattern layer B is formed on the surface of the first pattern layer A, and the second pattern layer B includes a pattern layer along... Figure 1b The X-axis direction of the structure contains sacrificial strips 114 spaced apart and a cover layer 113 covering the surface of the sacrificial strips 114. In related technologies, after forming the second pattern layer B, the actual array area needs to be defined by a photoresist layer 112. At this time, after the photoresist layer 112 is developed, residual photoresist 112a is easily present in the sidewall gaps (i.e., the gaps between the cover layers 113), which ultimately leads to the pattern not being fully opened (e.g., ...). Figure 1c (As shown in the closed capacitor hole 102). Furthermore, during photoresist layer development, photoresist layer 112 should contact the adjacent capping layer 113. However, in actual processes, due to limitations in photolithography, photoresist layer 112 does not contact its adjacent capping layer 113, instead having a gap 115. Thus, during subsequent pattern transfer, the pattern at this gap 115 is also transferred, thereby forming a pseudo capacitor hole 101 in the substrate 10 (as shown in the closed capacitor hole 102). Figure 1c As shown in the figure, this causes abnormal edge patterns in the array region AA, which in turn affects the performance and fabrication yield of the dynamic random access memory.

[0074] To address the aforementioned technical problems, this disclosure provides a novel method for forming a semiconductor structure, which can reduce the tilting and damage of sidewalls during pattern transfer, enabling precise pattern transfer and reducing residual photoresist in the sidewall gaps, thus allowing the pattern to be fully opened. Furthermore, the semiconductor structure formation method provided by this disclosure can also reduce the formation of pseudo-capacitor holes in the substrate, prevent abnormal patterns at the edge of the array region, and thereby improve the yield of the semiconductor structure.

[0075] Before introducing the embodiments of this disclosure, let's define four directions that may be used in the following embodiments to describe the three-dimensional structure. The substrate may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the fourth direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies), three intersecting directions are defined. For example, the extension direction of the first spacer layer can be defined as the second direction, and the extension direction of the second sidewall layer can be defined as the third direction. The second direction forms an acute or obtuse angle with the third direction. The first direction intersects with the second and third directions. Based on the first, second, and third directions, the planar orientation of the substrate can be determined. In the embodiments of this disclosure, the first direction is defined as the X-axis direction, the second direction as the Y1-axis direction, the third direction as the Y2-axis direction, and the fourth direction as the Z-axis direction.

[0076] This disclosure provides a method for forming a semiconductor structure. Figure 2This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 2 As shown, the method for forming a semiconductor structure includes the following steps:

[0077] Step S201: A substrate is provided, and a first spacer layer is formed on the surface of the substrate, which is spaced apart along a first direction and extends along a second direction. The first spacer layer includes a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction.

[0078] In this embodiment, the substrate includes at least a substrate, which may include a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. In other embodiments, the substrate may also be an ion-doped substrate, such as a p-type doped substrate or an n-type doped substrate.

[0079] In some embodiments, the substrate may further include a stacked structure for forming capacitor holes in a semiconductor structure, the stacked structure including a bottom support layer, a bottom sacrificial layer, an intermediate support layer, a top sacrificial layer, and a top support layer.

[0080] In some embodiments, the substrate may further include a multilayer mask layer located on the surface of the substrate or the surface of the stacked structure, the multilayer mask layer being used to transfer a pattern to be transferred to the surface of the substrate or the stacked structure.

[0081] In some embodiments, the first spacer layers are spaced apart along a first direction and extend along a second direction, wherein the first direction and the second direction may form an acute angle or an obtuse angle. The first mask layer may be a single mask layer or a composite mask layer consisting of multiple mask layers stacked along a fourth direction.

[0082] In this embodiment of the disclosure, the material of the first masking layer may be a spin-on hard mask (SOH); the material of the first anti-reflective layer may be silicon oxynitride.

[0083] In this embodiment of the disclosure, the material of the first sidewall layer can be an oxide, for example, silicon oxide.

[0084] Step S202: A first sacrificial layer is formed in the gap between the first spacer layers; wherein the surface of the first spacer layer is flush with the surface of the first sacrificial layer; the first mask layer, the first sidewall layer and the first sacrificial layer constitute the first pattern layer.

[0085] In this embodiment of the present disclosure, the first sacrificial layer and the first spacer layer are alternately disposed along the first direction, and the first sacrificial layer may be an oxide layer or an SOH layer.

[0086] In this embodiment of the disclosure, the top and bottom surfaces of the first spacer layer and the first sacrificial layer are flush along the fourth direction.

[0087] Step S203: A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least a second sidewall layer that is spaced apart along a first direction and extends along a third direction.

[0088] In some embodiments, the second sidewall layers are spaced apart along the first direction and extend along the third direction, wherein the second direction and the third direction may form an acute angle or an obtuse angle, and the first direction and the second direction may form a right angle.

[0089] In this embodiment of the disclosure, a second patterned layer is formed on the surfaces of the first sidewall layer and the first sacrificial layer. The second patterned layer further includes a second sacrificial layer located between the second sidewall layers, wherein the surfaces of the second sidewall layers and the second sacrificial layer are flush, that is, the top and bottom surfaces of the second sidewall layers and the second sacrificial layer along the fourth direction are flush. The second sacrificial layer may be an SOH or silicon oxynitride layer.

[0090] Step S204: Transfer the initial pattern defined by the second sidewall layer and the first sidewall layer to the substrate.

[0091] In this embodiment of the disclosure, the included angle between the second direction and the third direction can be determined according to the layout design of the initial pattern. For example, the included angle between the second direction and the third direction can be 20 degrees (°) to 90°, such as 20°, 40°, 70° or 90°.

[0092] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0093] The semiconductor structure formation method provided in this embodiment improves the accuracy of pattern transfer and thus improves the semiconductor structure fabrication yield. In the process of forming the first pattern layer, a first sacrificial layer is formed in the gap between the first spacer layers. In this way, the first sidewall layer will not collapse or be damaged during the formation of the first pattern layer.

[0094] Figures 3a to 3z This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 3a to 3z The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0095] First, step S201 is performed, providing a substrate, on the surface of which a first spacer layer is formed, spaced apart along a first direction and extending along a second direction. The first spacer layer includes a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction.

[0096] like Figure 3a As shown, the substrate includes a fourth mask layer 12 and a second dielectric layer 13 located on the surface of the fourth mask layer 12. In this embodiment of the present disclosure, the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer 123. The first hard mask layer 121 may be a polysilicon layer, the second hard mask layer 122 may be a silicon oxide layer, and the third hard mask layer 123 may be an amorphous carbon layer (ACL) or a polysilicon layer. The second dielectric layer 13 may be a silicon nitride layer or a silicon oxynitride layer.

[0097] In some embodiments, the fourth mask layer 12 is used to transfer the initial pattern defined by the first sidewall layer and the second sidewall layer. Since the critical dimensions of the initial pattern shrink with each transfer during the transfer process, the initial pattern is transferred through the fourth mask layer 12, which has multiple hard mask layers, until the desired pattern size is reached. This allows for continuous miniaturization of the process node and improves the integration density of the semiconductor structure. Therefore, in this embodiment, the number of hard mask layers in the fourth mask layer 12 can be set according to actual needs. For example, the fourth mask layer 12 can also consist of one hard mask layer or five hard mask layers.

[0098] In other embodiments, the substrate may not include the second dielectric layer 13.

[0099] In this embodiment of the disclosure, please continue to refer to Figure 3a The substrate includes the array region AA and the peripheral region PA.

[0100] In some embodiments, the first spacer layer can be formed by the following steps: sequentially forming a first initial mask layer and a second initial mask layer on the surface of a substrate; etching the second initial mask layer to form second initial spacer layers spaced apart along a first direction; forming a first capping layer on the sidewall of the second initial spacer layer; etching the first initial mask layer through the first capping layer to form first mask layers spaced apart along the first direction; forming a second initial capping layer covering the first mask layer and the substrate; removing the second initial capping layer located on the top surface of the first mask layer and the surface of the substrate, and retaining the second initial capping layer located on the sidewall of the first mask layer to form a first sidewall layer.

[0101] Please continue reading Figure 3aA first initial mask layer 14 and a second initial mask layer 15 are sequentially formed on the substrate surface. The first initial mask layer 14 includes a first initial masking layer 141 and a first initial antireflective layer 142; the second initial mask layer 15 includes a second initial masking layer 151 and a second initial antireflective layer 152. Both the first initial masking layer 141 and the second initial masking layer 151 can be made of SOH; both the first initial antireflective layer 142 and the second initial antireflective layer 152 can be made of silicon oxynitride. In this embodiment, the first and second initial mask layers can be formed by any of the following suitable deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0102] In other embodiments, the first initial mask layer 14 may consist only of the first initial masking layer 141, and the second initial mask layer 15 may consist only of the second initial masking layer 151.

[0103] In some embodiments, the second initial spacer layer can be formed by the following steps: forming a first photoresist layer having a first preset pattern on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along a first direction and extending along a second direction, the first sub-patterns exposing a portion of the second initial mask layer; removing the second initial mask layer exposed by the first sub-patterns to form the second initial spacer layer.

[0104] In this embodiment of the disclosure, Figure 3b This is a top view of the first photoresist layer. Please continue reading. Figure 3a and Figure 3b A first photoresist layer 16 with a first preset pattern is formed on the surface of the second initial mask layer 15; wherein the first preset pattern includes a plurality of first sub-patterns E located in the array region AA and arranged sequentially along the X-axis direction and extending along the Y1-axis direction, and the first sub-patterns E expose a portion of the second initial mask layer 15.

[0105] like Figure 3c As shown, the second initial mask layer 15 is etched by the first photoresist layer 16 to remove the second initial mask layer 15 (including the second initial anti-reflection layer 152 and the second initial masking layer 151 located in the projection area of ​​the second initial anti-reflection layer 152 along the Z-axis) exposed by the first sub-pattern E, forming a second initial spacer layer 17. The second initial spacer layer 17 includes a second masking layer 171 and a second anti-reflection layer 172 located on the surface of the second masking layer 171.

[0106] In some embodiments, please continue to see Figure 3c After forming the second initial spacer layer 17, the method for forming the semiconductor structure further includes removing the first photoresist layer 16 having a first preset pattern.

[0107] In some embodiments, forming a first cover layer on the sidewall of the second initial spacer layer may include the following steps: forming a first initial cover layer on the surfaces of the second initial spacer layer and the first initial mask layer; removing the first initial cover layer located on the top surface of the second initial spacer layer and the surface of the first initial mask layer, and retaining the first initial cover layer located on the sidewall of the second initial spacer layer to form the first cover layer.

[0108] like Figure 3d As shown, a first initial capping layer 18 is formed on the surfaces of the second initial spacer layer 17 and the first initial mask layer 14, wherein the first initial capping layer 18 covers the sidewalls and top surface of the second initial spacer layer 17 and the surface of the first initial mask layer 14. In this embodiment, the first initial capping layer 18 can be formed using an atomic layer deposition process to improve the film quality of the first initial capping layer 18. The first initial capping layer 18 can be an oxide layer, such as a silicon oxide layer.

[0109] In this embodiment of the present disclosure, after the first initial capping layer 18 is formed, a dry etching process is used to simultaneously remove the first initial capping layer 18 from the top surface of the second initial spacer layer 17 and the surface of the first initial mask layer 14. The remaining first initial capping layer 18 located on the sidewall of the second initial spacer layer 17 constitutes the first capping layer 181 (e.g., ...). Figure 3e (As shown).

[0110] Please continue reading Figure 3d and Figure 3e After forming the first capping layer 181, the method for forming the semiconductor structure further includes removing the second initial spacer layer 17. In some embodiments, the second initial spacer layer can be removed using a wet etching technique, for example, by etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0111] Please continue reading Figure 3e and Figure 3f The first initial mask layer 14 is etched through the first cover layer 181, that is, the portion of the first initial mask layer 14 exposed by the first cover layer 181 (including the first initial anti-reflection layer 142 and the first initial masking layer 141 located in the projection area of ​​the first initial anti-reflection layer 142 along the Z-axis) is removed to form the first mask layer 19. The first mask layer 19 includes a first masking layer 191 and a first anti-reflection layer 192 located on the surface of the first masking layer 191.

[0112] like Figure 3gAs shown, a second initial capping layer 20 is formed covering the first mask layer 19 and the second dielectric layer 13; wherein the second initial capping layer 20 covers the sidewalls and top surface of the first mask layer 19 and the surface of the second dielectric layer 13. In this embodiment, the second initial capping layer 20 can be formed using an atomic layer deposition process to improve the film quality of the second initial capping layer 20. The second initial capping layer 20 can be an oxide layer, such as a silicon oxide layer.

[0113] like Figure 3g and Figure 3h As shown, after forming the second initial capping layer 20, the semiconductor structure formation method further includes: simultaneously removing the second initial capping layer 20 from the top surface of the first mask layer 19 and the surface of the second dielectric layer 13 using a dry etching process, with the remaining second initial capping layer 20 located on the sidewalls of the first mask layer 19 constituting the first sidewall layer 201. The first mask layer 19 and the first sidewall layers 201 located on both sides of the first mask layer 19 along the X-axis direction together constitute the first spacer layer 21.

[0114] Next, step S202 is performed to form a first sacrificial layer in the gap between the first spacer layers; wherein the surface of the first spacer layer is flush with the surface of the first sacrificial layer; the first mask layer, the first sidewall layer and the first sacrificial layer constitute the first pattern layer.

[0115] In some embodiments, the first sacrificial layer may be formed by the following steps: forming a first initial sacrificial layer in the gaps between the first spacers and on the surface of the first spacers; etching back the first initial sacrificial layer until the surface of the first mask layer is exposed, thereby forming the first sacrificial layer.

[0116] like Figure 3i As shown, a first sacrificial layer material is spin-coated into the gap between two adjacent first spacer layers 21, the surface of the first spacer layer 21, and the surface of the gap between the first spacer layers 21 to form a first initial sacrificial layer 22. The first sacrificial layer material can be SOH or other materials.

[0117] like Figure 3i and Figure 3j As shown, the first initial sacrificial layer 22 is etched back until the surface of the first mask layer 19 (i.e., the first masking layer 191) is exposed, and the remaining first initial sacrificial layer 22 located in the gap between two adjacent first spacer layers 21 constitutes the first sacrificial layer 23.

[0118] It should be noted that, since the first mask layer 19 in this embodiment includes a first masking layer 191 and a first anti-reflection layer 192, the surface exposed during the formation of the first sacrificial layer 23 can be either the surface exposed to the first anti-reflection layer 192 or the surface exposed to the first masking layer 191 (e.g., ...). Figure 3j (As shown).

[0119] In this embodiment of the present disclosure, the etching selectivity ratio between the first sacrificial layer 23 and the substrate is equal to the etching selectivity ratio between the first antireflection layer 192 and the substrate. Thus, when the first initial sacrificial layer 22 is etched back, the first antireflection layer 192 on the surface of the first masking layer 191 can be removed simultaneously, which simplifies the fabrication process of the first pattern layer and saves the manufacturing cost of the semiconductor structure.

[0120] In some embodiments, the first sacrificial layer 23 and the first masking layer 191 may be made of the same material. In this way, the first sacrificial layer 23 and the first masking layer 191 can be removed simultaneously in subsequent processes, which simplifies the semiconductor structure fabrication process.

[0121] The semiconductor structure formation method provided in this disclosure improves the accuracy of pattern transfer and thus improves the semiconductor structure fabrication yield by forming a first sacrificial layer in the gap between the first spacer layers during the formation of the first pattern layer.

[0122] In this embodiment of the disclosure, after the first sacrificial layer 23 is formed, the first pattern layer is also formed. The first pattern layer 300 includes a first mask layer 19 (e.g., a first masking layer 191), a first sidewall layer 201, and the first sacrificial layer 23.

[0123] Figure 3k This is a top view of the first pattern layer for ease of understanding. Figure 3k Only a limited number of the first sidewall layers are shown in the diagram, and Figure 3k The first masking layer 191 and the first sacrificial layer 23 in the first pattern layer are not shown. Figure 3k As shown, the first pattern layer 300 includes first sidewall layers 201 that are spaced apart along the X-axis and extend along the Y1-axis.

[0124] In this embodiment of the disclosure, the first mask layer is not removed by wet etching during the formation of the first pattern layer. This prevents the first sidewall layer from tilting or collapsing, and thus does not affect the subsequent pattern transfer process.

[0125] In some embodiments, after forming the first pattern layer 300, the method for forming a semiconductor structure further includes forming a first dielectric layer located above the first pattern layer.

[0126] like Figure 3l As shown, a first dielectric layer 24 is formed on the first pattern layer 300. The material of the first dielectric layer 24 can be silicon nitride or silicon oxynitride.

[0127] In other embodiments, the first dielectric layer 24 located above the first pattern layer may not be formed.

[0128] Next, step S203 is performed to form a second pattern layer on the surface of the first pattern layer; the second pattern layer includes at least a second sidewall layer that is spaced apart along a first direction and extends along a third direction.

[0129] In some embodiments, the second pattern layer may be formed by the following steps: forming second spacer layers spaced apart along a first direction on the surface of the first pattern layer, the second spacer layers including a second mask layer and second sidewall layers located on both sides of the second mask layer along the first direction; forming a second sacrificial layer in the gaps between the second spacer layers, wherein the second spacer layers are flush with the surface of the second sacrificial layer; the second mask layer, the second sidewall layer and the second sacrificial layer constitute the second pattern layer.

[0130] In some embodiments, the second spacer layer can be formed by the following steps: sequentially forming a third initial mask layer and a fourth initial mask layer on the surface of the first pattern layer; etching the fourth initial mask layer to form fourth initial spacer layers spaced apart along a first direction; forming a third capping layer on the sidewall of the fourth initial spacer layer; etching the third initial mask layer through the third capping layer to form second mask layers spaced apart along the first direction; forming a fourth initial capping layer covering the second mask layer and the first pattern layer; removing the fourth initial capping layer located on the top surface of the second mask layer and the surface of the first pattern layer, and retaining the fourth initial capping layer located on the sidewall of the second mask layer to form a second sidewall layer.

[0131] like Figure 3m As shown, a third initial mask layer 25 and a fourth initial mask layer 26 are sequentially formed on the surface of the first dielectric layer 24. The third initial mask layer 25 includes a third initial masking layer 251 and a third initial antireflective layer 252; the fourth initial mask layer 26 includes a fourth initial masking layer 261 and a fourth initial antireflective layer 262. The materials of the third initial masking layer 251 and the fourth initial masking layer 261 can both be SOH; the materials of the third initial antireflective layer 252 and the fourth initial antireflective layer 262 can both be silicon oxynitride. In this embodiment, the first and second initial mask layers can be formed by any suitable deposition process. In other embodiments, the third initial mask layer 25 may only include the third initial masking layer 251, and the fourth initial mask layer 26 may only include the fourth initial masking layer 261.

[0132] In some embodiments, the fourth initial spacer layer is formed by the following steps: forming a second photoresist layer having a second preset pattern on the surface of the fourth initial mask layer; wherein the second preset pattern includes a plurality of second sub-patterns arranged sequentially along a first direction and extending along a third direction, the second sub-patterns exposing a portion of the fourth initial mask layer; removing the fourth initial mask layer exposed by the second sub-patterns to form the fourth initial spacer layer.

[0133] In this embodiment of the disclosure, Figure 3n This is a top view of the second photoresist layer. Please continue reading. Figure 3m and Figure 3n A second photoresist layer 27 with a second preset pattern is formed on the surface of the fourth initial mask layer 26; wherein the second preset pattern includes a plurality of second sub-patterns F located in the array region AA and arranged sequentially along the X-axis direction and extending along the Y2-axis direction, and the second sub-patterns F expose a portion of the fourth initial mask layer 26.

[0134] Please continue reading Figure 3m and Figure 3n The fourth initial mask layer 26 is etched through the second photoresist layer 27 to remove the fourth initial mask layer 26 (including the fourth initial anti-reflection layer 262 and the fourth initial masking layer 261 located in the projection area of ​​the fourth initial anti-reflection layer 262 along the Z-axis) exposed by the second sub-pattern F, forming as shown in the figure. Figure 3o The fourth initial spacer layer 28 is shown. The fourth initial spacer layer 28 includes a fourth masking layer 281 and a fourth anti-reflective layer 282 located on the surface of the fourth masking layer 281.

[0135] In some embodiments, please continue to see Figure 3o After forming the fourth initial spacer layer 28, the method for forming the semiconductor structure further includes removing the second photoresist layer 27 having a second preset pattern.

[0136] In some embodiments, forming a third cover layer on the sidewall of the fourth initial spacer layer may include the following steps: forming a third initial cover layer on the surfaces of the fourth initial spacer layer and the third initial mask layer; removing the third initial cover layer located on the top surface of the fourth initial spacer layer and the surface of the third initial mask layer, and retaining the third initial cover layer located on the sidewall of the fourth initial spacer layer to form the third cover layer.

[0137] like Figure 3pAs shown, a third initial capping layer 29 is formed on the surfaces of the fourth initial spacer layer 28 and the third initial mask layer 25, wherein the third initial capping layer 29 covers the sidewalls and top surface of the fourth initial spacer layer 28 and the surface of the third initial mask layer 25. In this embodiment, the third initial capping layer 29 can be formed using an atomic layer deposition process to improve the film quality of the third initial capping layer 29. The third initial capping layer 29 can be an oxide layer, such as a silicon oxide layer.

[0138] In this embodiment of the present disclosure, after the third initial capping layer 29 is formed, a dry etching process is used to simultaneously remove the third initial capping layer 29 from the top surface of the fourth initial spacer layer 28 and the surface of the third initial mask layer 25. The remaining third initial capping layer 29 located on the sidewall of the fourth initial spacer layer 28 constitutes the third capping layer 291 (e.g., Figure 3q (As shown).

[0139] Please continue reading Figure 3q After forming the third capping layer 291, the method for forming the semiconductor structure further includes removing the fourth initial spacer layer 28. In some embodiments, a wet etching technique can be used to remove the second initial spacer layer, for example, using strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0140] Please continue reading Figure 3q and Figure 3r The third initial mask layer 25 is etched through the third cover layer 291, that is, the portion of the third initial mask layer 25 exposed by the third cover layer 291 (including the third initial anti-reflection layer 252 and the third initial masking layer 251 located in the projection area of ​​the third initial anti-reflection layer 252 along the Z-axis) is removed to form the second mask layer 30. The second mask layer 30 includes the third masking layer 301 and the third anti-reflection layer 302 located on the surface of the third masking layer 301.

[0141] like Figure 3s As shown, a fourth initial capping layer 31 is formed covering the second mask layer 30 and the first dielectric layer 24; wherein the fourth initial capping layer 31 covers the sidewalls and top surface of the second mask layer 30 and the surface of the first dielectric layer 24. In this embodiment, the fourth initial capping layer 31 can be formed using an atomic layer deposition process to improve the film quality of the fourth initial capping layer 31. The fourth initial capping layer 31 can be an oxide layer, such as a silicon oxide layer.

[0142] like Figure 3s and Figure 3tAs shown, after forming the fourth initial capping layer 31, the semiconductor structure formation method further includes: simultaneously removing the fourth initial capping layer 31 from the top surface of the second mask layer 30 and the surface of the first dielectric layer 24 using a dry etching process, and retaining the fourth initial capping layer 31 located on the sidewalls of the second mask layer 30 to form the second sidewall layer 311. The second mask layer 30 and the second sidewall layer 311 located on both sides of the second mask layer 30 along the X-axis direction constitute the second spacer layer 32.

[0143] In other embodiments, the third masking layer 301 and the second sidewall layers 311 located on both sides of the third masking layer 301 along the X-axis direction together constitute the second spacer layer 32.

[0144] In some embodiments, forming a second sacrificial layer in the gap between the second spacers may include the following steps: forming a second initial sacrificial layer in the gap between the second spacers and on the surface of the second spacers; etching back the second initial sacrificial layer until the surface of the second mask layer is exposed to form a second sacrificial layer.

[0145] Please continue reading Figure 3t A second sacrificial layer material is spin-coated into the gaps between the second spacers 32, the surface of the second spacers 32, and the surface of the gaps between the second spacers 32 to form a second initial sacrificial layer 33; the second sacrificial layer material can be SOH or other materials.

[0146] like Figure 3t and Figure 3u As shown, the second initial sacrificial layer 33 is etched back until the surface of the second mask layer 30 is exposed, and the remaining second initial sacrificial layer 33 located in the gaps between the second spacer layers 32 constitutes the second sacrificial layer 34.

[0147] It should be noted that, since the second mask layer 30 in this embodiment includes a third masking layer 301 and a third anti-reflection layer 302, the surface exposed during the formation of the second sacrificial layer 34 can be either the surface exposed to the third anti-reflection layer 302 or the surface exposed to the third masking layer 301 (e.g., ...). Figure 3u (As shown)

[0148] In this embodiment, the etching selectivity between the second sacrificial layer 34 and the substrate is equal to the etching selectivity between the third antireflection layer 302 and the substrate. Thus, when the second sacrificial layer 34 is etched back, the third antireflection layer 302 on the surface of the third masking layer 301 can be removed simultaneously, simplifying the fabrication process of the second pattern layer and saving the manufacturing cost of the semiconductor structure.

[0149] In some embodiments, the second sacrificial layer 34 and the third masking layer 301 may be made of the same material. In this way, the second sacrificial layer 34 and the third masking layer 301 can be removed simultaneously in subsequent processes, which simplifies the semiconductor structure fabrication process.

[0150] The semiconductor structure formation method provided in this disclosure improves the accuracy of pattern transfer and thus improves the semiconductor structure fabrication yield by forming a second sacrificial layer in the gap between the second spacer layers during the formation of the second pattern layer.

[0151] In this embodiment of the disclosure, after the second sacrificial layer 34 is formed, the second pattern layer is also formed. The second pattern layer 400 includes a second mask layer 30 (e.g., a third masking layer 301), a second sidewall layer 311, and a second sacrificial layer 34.

[0152] Figure 3v This is a top view of the second pattern layer for easier understanding. Figure 3v Only a limited number of second sidewall layers are shown in the diagram, and Figure 3v The third masking layer 301 and the second sacrificial layer 34 in the second pattern layer are not shown. Figure 3v As shown, the second pattern layer 400 includes second sidewall layers 211 that are spaced apart along the X-axis and extend along the Y2-axis.

[0153] In this embodiment of the disclosure, the second mask layer is not removed by wet etching during the formation of the second pattern layer. This prevents the second sidewall layer from tilting or collapsing, and thus does not affect the subsequent pattern transfer process.

[0154] In some embodiments, after forming the second patterned layer, the method for forming the semiconductor structure further includes: forming a third mask layer on the surface of the second patterned layer; forming a third photoresist layer having a third preset pattern on the surface of the third mask layer, wherein the third preset pattern includes a portion of the array region exposed away from the peripheral region.

[0155] like Figure 3w As shown, a third mask layer 35 is formed on the surface of the second pattern layer 400; a third photoresist layer 36 with a third preset pattern is formed on the surface of the third mask layer 35, wherein the third preset pattern includes a third sub-pattern G. The third mask layer 35 exposed by the third sub-pattern G is removed to form a third mask layer with the third preset pattern. In this embodiment, the third mask layer 35 may be a silicon oxide layer.

[0156] In this embodiment, the third mask layer 35 is exposed by etching away the third photoresist layer 36 with a third preset pattern, and the second sacrificial layer 34 and the third mask layer 301 in the second pattern layer 400, the first dielectric layer 24 located within the Z-axis projection area of ​​the second sacrificial layer 34 and the third mask layer 301, the first sacrificial layer 23 and the first mask layer 191 in the first pattern layer 300, and the second dielectric layer 13 located within the Z-axis projection area of ​​the first sacrificial layer 23 and the first mask layer 191 are formed as shown in the figure. Figure 3x The initial pattern H shown is defined by the first sidewall layer 201 and the second sidewall layer 311.

[0157] In this embodiment of the present disclosure, by forming a third mask layer on the surface of the second pattern layer and developing on the third mask layer, not only can the residue of the third photoresist layer in the second pattern layer be reduced, but also the abnormality of the pattern at the boundary of the peripheral region and the array region caused by the tilt of the third photoresist layer pattern at the boundary of the peripheral region and the array region, as well as the generation of pseudo-capacitor holes, can be reduced. Thus, the fabrication yield of the semiconductor structure can be improved.

[0158] Finally, step S204 is performed to transfer the initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate.

[0159] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0160] Combination Figure 3a , Figure 3y and Figure 3z As shown, the substrate includes a fourth mask layer 12, which includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer 123. In implementation, firstly, the initial pattern H is transferred to the third hard mask layer within the fourth mask layer. Secondly, the second hard mask layer 122 is etched through the third hard mask layer 123 containing the initial pattern H to transfer the initial pattern H to the second hard mask layer 122. Finally, the first hard mask layer 121 is etched through the second hard mask layer containing the initial pattern H to transfer the initial pattern H to the first hard mask layer 121, forming a first hard mask layer 121a with the initial pattern H, thereby achieving the transfer of the initial pattern H to the substrate. It should be noted that, for ease of understanding, Figure 3z The image only shows a portion of the hole structure formed by the initial pattern H.

[0161] The semiconductor structure formation method provided in this disclosure, during the formation of the first pattern layer, forms a first sacrificial layer in the gap between the first spacers, and during the formation of the second pattern layer, forms a second sacrificial layer in the gap between the second spacers. Thus, the first sidewall layer and the second sidewall layer will not collapse or be damaged during the formation of the first pattern layer and the second pattern layer, which can improve the accuracy of pattern transfer and thereby improve the yield of semiconductor structure fabrication.

[0162] In addition, in this embodiment of the present disclosure, after the formation of the second pattern layer, the development process is not performed directly on the second pattern layer. Instead, a third mask layer is formed on the surface of the second pattern layer. By developing on the third mask layer, not only can the residue of the third photoresist layer in the second pattern layer be reduced, but also the abnormality of the pattern at the boundary of the peripheral region and the array region caused by the tilt of the third photoresist layer pattern at the boundary of the peripheral region and the array region, as well as the generation of pseudo-capacitor holes, can be reduced, thereby improving the fabrication yield of the semiconductor structure.

[0163] In addition, this disclosure also provides a semiconductor structure, please refer to the following embodiments. Figures 3w to 3z The semiconductor structure includes: a substrate; the substrate includes an initial pattern H.

[0164] In this embodiment of the disclosure, please continue to refer to Figure 3w The substrate includes a fourth mask layer 12 and a second dielectric layer 13 located on the surface of the fourth mask layer 12; wherein the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122 and a third hard mask layer 123.

[0165] In other embodiments, the substrate further includes a substrate and a stacked structure located on the surface of the substrate.

[0166] Please continue to refer to this. Figure 3w The initial pattern H is defined by a first sidewall layer 201 in the first pattern layer 300 and a second sidewall layer 311 in the second pattern layer 400; the first pattern layer 300 is located on the surface of the substrate, and the first pattern layer 300 includes alternating patterns along the X-axis and along the Y1-axis (see reference). Figure 3k The first spacer layer and the first sacrificial layer 23 extend from each other; the surfaces of the first spacer layer and the first sacrificial layer 23 are flush (both the top and bottom surfaces are flush along the Z-axis). The first spacer layer includes a first mask layer and first sidewall layers 201 located on both sides of the first mask layer along the X-axis; the first mask layer includes a first masking layer 191.

[0167] Please continue to refer to this. Figure 3wThe second pattern layer 400 is located on the surface of the first pattern layer 300. The second pattern layer 400 includes a second spacer layer and a second sacrificial layer 34 that are alternately arranged along the X-axis and extend along the Y2 direction. The bottom surface of the second spacer layer is flush with the bottom surface of the second sacrificial layer 34 (both the top and bottom surfaces are flush along the Z-axis). The second spacer layer includes a second mask layer and second sidewall layers 311 located on both sides of the second mask layer along the X-axis direction. The second mask layer includes a third masking layer 301.

[0168] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0169] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0170] The semiconductor structure provided in this disclosure includes a substrate with an initial pattern, the initial pattern being defined by a first sidewall layer in a first pattern layer and a second sidewall layer in a second pattern layer. Since the semiconductor structure provided in this disclosure is formed using the above-described semiconductor structure formation method, the first and second sidewall layers in this disclosure will not collapse or be damaged during formation. That is, the first and second sidewall layers in this disclosure have vertical contour lines, thus improving the accuracy of initial pattern transfer and consequently increasing the yield of the fabricated semiconductor structure.

[0171] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0172] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the surface of which is formed with a first spacer layer spaced apart along a first direction and extending along a second direction, the first spacer layer including a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction; A first sacrificial layer is formed in the gaps between the first spacer layers; wherein the first spacer layers are flush with the surface of the first sacrificial layer; the first mask layer, the first sidewall layer and the first sacrificial layer constitute a first pattern layer; A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least two sidewall layers spaced apart along the first direction and extending along a third direction; the first direction, the second direction, and the third direction are any three directions in the plane where the substrate is located; The initial pattern defined by the second sidewall layer and the first sidewall layer is transferred to the substrate.

2. The method according to claim 1, characterized in that, A first sacrificial layer is formed in the gaps between the first spacer layers, comprising: A first initial sacrificial layer is formed in the gaps between the first spacer layers and on the surface of the first spacer layer; The first initial sacrificial layer is etched back until the surface of the first mask layer is exposed, thus forming the first sacrificial layer.

3. The method according to claim 2, characterized in that, The first spacer layer is formed by the following steps: A first initial mask layer and a second initial mask layer are sequentially formed on the surface of the substrate; The second initial mask layer is etched to form a second initial spacer layer spaced apart along the first direction; A first covering layer is formed on the sidewall of the second initial spacer layer; The first initial mask layer is etched through the first cover layer to form the first mask layer spaced apart along the first direction; A second initial cover layer is formed covering the first mask layer and the substrate; The second initial cover layer located on the top surface of the first mask layer and the surface of the substrate is removed, and the second initial cover layer located on the sidewall of the first mask layer is retained to form the first sidewall layer.

4. The method according to claim 3, characterized in that, The second initial spacer layer is formed by the following steps: A first photoresist layer having a first preset pattern is formed on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along the first direction and extending along the second direction, and the first sub-patterns expose a portion of the second initial mask layer; Remove the second initial mask layer exposed by the first sub-pattern to form the second initial spacer layer.

5. The method according to any one of claims 1 to 4, characterized in that, The second pattern layer is formed by the following steps: A second spacer layer is formed on the surface of the first pattern layer at intervals along the first direction. The second spacer layer includes a second mask layer and second sidewall layers located on both sides of the second mask layer along the first direction. A second sacrificial layer is formed in the gaps between the second spacer layers, wherein the second spacer layers are flush with the surface of the second sacrificial layer; the second mask layer, the second sidewall layer and the second sacrificial layer constitute the second pattern layer.

6. The method according to claim 5, characterized in that, A second sacrificial layer is formed in the gaps between the second spacer layers, comprising: A second initial sacrificial layer is formed in the gaps between the second spacers and on the surface of the second spacers; The second initial sacrificial layer is etched back until the surface of the second mask layer is exposed, forming the second sacrificial layer.

7. The method according to claim 6, characterized in that, The second spacer layer is formed by the following steps: A third initial mask layer and a fourth initial mask layer are sequentially formed on the surface of the first pattern layer; The fourth initial mask layer is etched to form a fourth initial spacer layer spaced apart along the first direction; A third covering layer is formed on the sidewall of the fourth initial spacer layer; The third initial mask layer is etched through the third capping layer to form the second mask layer spaced apart along the first direction; A fourth initial overlay layer is formed, covering the second mask layer and the first pattern layer; The fourth initial cover layer located on the top surface of the second mask layer and the surface of the first pattern layer is removed, and the fourth initial cover layer located on the sidewall of the second mask layer is retained to form the second sidewall layer.

8. The method according to claim 7, characterized in that, The fourth initial spacer layer is formed by the following steps: A second photoresist layer with a second preset pattern is formed on the surface of the fourth initial mask layer; wherein, the second preset pattern includes a plurality of second sub-patterns arranged sequentially along the first direction and extending along the third direction, and the second sub-patterns expose a portion of the fourth initial mask layer; The fourth initial mask layer exposed by the second sub-pattern is removed to form the fourth initial spacer layer.

9. The method according to claim 8, characterized in that, The substrate includes an array region and a peripheral region. After forming the second pattern layer, the method further includes: A third mask layer is formed on the surface of the second patterned layer; A third photoresist layer with a third preset pattern is formed on the surface of the third mask layer, wherein the third preset pattern includes a portion of the array region that is exposed away from the peripheral region; The initial pattern is transferred to the substrate corresponding to the array region exposed by the third preset pattern.

10. The method according to claim 5, characterized in that, The first mask layer includes a first masking layer and a first anti-reflection layer; The etching selectivity between the first sacrificial layer and the substrate is equal to the etching selectivity between the first antireflective layer and the substrate.

11. The method according to claim 5, characterized in that, The second mask layer includes a third masking layer and a third anti-reflection layer; The etching selectivity between the second sacrificial layer and the substrate is equal to the etching selectivity between the third antireflective layer and the substrate.

12. The method according to claim 11, characterized in that, The substrate includes a fourth mask layer; transferring the initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate includes: Using the first sidewall layer and the second sidewall layer as masks, the initial pattern is transferred to the fourth mask layer to form a fourth mask layer having the initial pattern; the initial pattern includes multiple third sub-patterns.

13. The method according to claim 12, characterized in that, The substrate further includes a substrate, and the fourth mask layer is located on the surface of the substrate; After forming the fourth mask layer having the initial pattern, the method further includes: The exposed portion of the substrate of the third sub-pattern is removed to transfer the initial pattern into the substrate.

14. The method according to claim 13, characterized in that, The substrate further includes a stacked structure, and the fourth mask layer is located on the surface of the stacked structure; After forming the fourth mask layer having the initial pattern, the method further includes: Remove the exposed portion of the stacked structure of the third sub-pattern to transfer the initial pattern into the stacked structure.

15. The method according to claim 14, characterized in that, After forming the first patterned layer and before forming the second patterned layer, the method for forming the semiconductor structure further includes: A first dielectric layer is formed on the surface of the first patterned layer.

16. The method according to claim 15, characterized in that, The initial pattern includes a capacitor hole pattern.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 16, wherein the semiconductor structure comprises: A substrate; the substrate includes an initial pattern; the initial pattern is defined by a first sidewall layer in a first pattern layer and a second sidewall layer in a second pattern layer; Wherein, the first pattern layer is located on the surface of the substrate, and the first pattern layer includes a first spacer layer and a first sacrificial layer that are alternately arranged along a first direction and extend along a second direction; the first spacer layer is flush with the surface of the first sacrificial layer; the first spacer layer includes a first mask layer and a first sidewall layer located on both sides of the first mask layer along the first direction; The second pattern layer is located on the surface of the first pattern layer, and the second pattern layer includes at least two sidewall layers that are spaced apart along the first direction and extend along a third direction; the first direction, the second direction and the third direction are any three directions in the plane where the substrate is located.

18. The semiconductor structure according to claim 17, characterized in that, The second pattern layer includes a second spacer layer and a second sacrificial layer that are alternately arranged along the first direction and extend along the third direction; the second spacer layer is flush with the bottom surface of the second sacrificial layer; the second spacer layer includes a second mask layer and a second sidewall layer located on both sides of the second mask layer along the first direction.

19. The semiconductor structure according to claim 18, characterized in that, The substrate also includes a substrate and a stacked structure located on the surface of the substrate.

20. The semiconductor structure according to any one of claims 17 to 19, characterized in that, The initial pattern includes a capacitor hole pattern.

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