A layout method for optimizing hold time

Abstract

The present application discloses a layout method for optimizing hold time, which relates to the field of FPGA technology. After the layout method arranges the FPGA chip according to the user input netlist to obtain the initial layout state, it determines the layout position of the logic units on each hold time critical path in the user input netlist, and then takes the logic units on the same hold time critical path as the optimization goal to move in a relatively distant trend, and legalizes the layout of the initial layout state. This method optimizes the layout legalization process under the overall layout idea of ​​combining global layout with local optimization to complete the legalization operation. In the local optimization process, the logic units on the same hold time critical path are made as discrete as possible to increase the delay, and then the hold time violation repair can be completed through layout legalization, so as to obtain a layout result in which all paths meet the setup time requirements and the hold time requirements, thereby improving the layout efficiency.

Description

Technical Field

[0001] The invention relates to the field of FPGA technology, and in particular to a layout method for optimizing holding time. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a chip that is widely used in daily household appliances, large machinery and even aerospace. In the design process of FPGA, the timing problem is one of the most concerned issues. In order to ensure the normal and stable operation of FPGA, it is necessary to ensure that the timing parameters of timing devices such as registers in FPGA meet the requirements. Setup time and hold time are two important timing parameters. Setup time refers to the time when the data is stable before the rising edge (or falling edge) of the register's clock signal arrives. If the setup time is not enough, the data will not be entered into the register at the rising edge (or falling edge) of the clock signal. Hold time refers to the time when the data is stable after the rising edge (or falling edge) of the register's clock signal arrives. If the hold time is not enough, the data cannot be entered into the register.

[0003] For the critical path between two sequential devices driven by the same clock signal, it is necessary to meet both the setup time and the hold time. The current traditional approach is to prioritize the setup time for layout and routing design. After the design is completed, static timing analysis is performed to determine the timing margin of the hold time for each path, so that the path with the hold time problem can be accurately located for correction and optimization, and the hold time violation can be repaired. However, with the continuous development of FPGA production technology, FPGA logic units and line delays are getting faster and faster, resulting in more and more hold time problems being exposed. This traditional method consumes a very long running time. In the case of large-scale design, it is not suitable for frequent static timing analysis, and the correction and optimization efficiency of hold time problems is low. Summary of the invention

[0004] In view of the above problems and technical requirements, the inventors have proposed a layout method for optimizing the holding time. The technical solution of the present invention is as follows:

[0005] A layout method for optimizing holding time, the layout method comprising:

[0006] Obtaining a user input netlist corresponding to the FPGA chip, and laying out the FPGA chip according to the user input netlist to obtain an initial layout state, where the initial layout state indicates a layout position of each logic unit in the user input netlist;

[0007] Determine the placement location of logic cells on each hold time critical path in the user input netlist, each hold time critical path being a path that is at risk of failing to meet hold time requirements;

[0008] With the optimization goal of moving the logic cells on the same hold time critical path in a relatively distant trend, the initial layout state is legalized to determine the updated layout position of each logic cell. After the layout legalization is completed, the layout results in which all paths meet the setup time requirements and the hold time requirements are obtained.

[0009] A further technical solution is that the layout legalization of the initial layout state includes:

[0010] For any logic unit on the hold time critical path, the farther the distance between the logic unit and other logic units on the same hold time critical path is within the exchange radius, the higher the selection probability of the layout position, and the closer the distance to other logic units on the same hold time critical path is, the lower the selection probability of the layout position is. According to the selection probability of each layout position, the updated layout position is selected and the layout position is optimized using the simulated annealing algorithm.

[0011] A further technical solution is to determine each critical path of the hold time in the user input netlist including:

[0012] It is determined that a path in the user input netlist, in which the number of levels of logic cells passed through is less than a predetermined threshold, is a hold time critical path.

[0013] A further technical solution is that each critical path for maintaining the time passes through two levels of logic units.

[0014] A further technical solution is that the layout legalization of the initial layout state includes:

[0015] When two logic units a and b on the same hold time critical path are also located on the same setup time critical path, and the preceding node Pre, logic unit a, logic unit b and subsequent node Next are connected in sequence along the data transmission direction on the setup time critical path, the initial layout state is legalized according to the reference connection from the preceding node Pre to the subsequent node Next, with the two logic units a and b on the same hold time critical path being moved relatively away from each other on the basis of optimizing the setup time of the setup time critical path as the optimization goal; wherein the setup time critical path is a path that has the risk of failing to meet the setup time requirement.

[0016] A further technical solution is that the initial layout state is legalized according to the reference connection from the previous node Pre to the next node Next, including:

[0017] The initial layout state is legalized by moving the logic unit a and the logic unit b relatively away from each other while keeping the distances between the logic unit a and the logic unit b and the reference connection line within a predetermined threshold as an optimization goal.

[0018] A further technical solution is that the layout legalization of the initial layout state according to the reference connection from the previous node Pre to the next node Next also includes:

[0019] On the basis of keeping the distance between the logic unit a and the reference line not exceeding a predetermined threshold, the logic unit a is taken as an optimization target in a direction close to the previous node Pre;

[0020] And / or, on the basis of keeping the distance between the logic unit b and the reference line not exceeding a predetermined threshold, moving the logic unit b in a direction close to the subsequent node Next is taken as an optimization target.

[0021] A further technical solution is that the layout optimization of the layout position of the logic unit a includes:

[0022] The smaller the distance between the logic unit a and the reference line within the exchange radius and the smaller the distance from the previous node Pre, the higher the selection probability of the layout position is set. According to the selection probability of each layout position within the exchange radius of the logic unit a, the updated layout position is selected and the layout position of the logic unit a is optimized using the simulated annealing algorithm.

[0023] A further technical solution is that the layout optimization of the layout position of the logic unit b includes:

[0024] The smaller the distance between the logic unit b and the reference line within the exchange radius and the smaller the distance to the subsequent node Next, the higher the selection probability of the layout position is set. According to the selection probability of each layout position within the exchange radius of the logic unit b, the updated layout position is selected and the layout position of the logic unit b is optimized using the simulated annealing algorithm.

[0025] The beneficial technical effects of the present invention are:

[0026] The present application discloses a layout method for optimizing hold time. The layout method optimizes the layout legalization process under the overall layout idea of ​​combining global layout with local optimization to complete the legalization operation. Before the layout legalization process, the layout positions of the logic units on the hold time critical path are screened out. Then, during the layout legalization, the logic units on the same hold time critical path are moved relatively far away as the optimization goal, so that the logic units on the same hold time critical path are as discrete as possible to increase the delay. Then, the hold time violation repair can be completed through layout legalization, so as to obtain a layout result in which all paths meet the setup time requirements and the hold time requirements, thereby improving the layout efficiency.

[0027] This method directly locates the critical path for holding time by analyzing the user input netlist according to the level of logic units passed by the path, without the need to perform static timing analysis again, further reducing time consumption and improving layout efficiency.

[0028] When this method repairs hold time violations during layout legalization, it will not have an impact on the path setup time that exceeds the acceptable error range. The entire method is still based on optimizing the setup time, and it will not sacrifice setup time and circuit performance while improving layout efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flow chart of a layout method according to an embodiment of the present application.

[0030] Figure 2 The diagram is a connection diagram of logic units a and b on a hold time critical path in an example and their preceding node Pre and succeeding node Next on the setup time critical path. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0032] This application discloses a layout method for optimizing hold time, please refer to Figure 1 The method comprises the following steps:

[0033] Step 1: Obtain a user input netlist corresponding to the FPGA chip, and layout the FPGA chip according to the user input netlist to obtain an initial layout state.

[0034] The obtained user input netlist is for the FPGA chip to be laid out, and the total logic resource demand of the user input netlist does not exceed the number of logic resources that the FPGA chip to be laid out can provide. The user input netlist is the netlist obtained after the user design completes the logic synthesis processing. The logic synthesis processing mainly includes four processes: reading, translation, optimization and mapping. It is a conventional process for developing FPGA chips using EDA tools. This application will not expand on the specific operations of the logic synthesis processing. The user input netlist indicates a number of logic units and the signal connection relationship between them. The logic unit in the user input netlist referred to in this application is the smallest basic unit of the user input netlist, corresponding to a slice-level module or a lookup table / register (LUT / REG) level module in the FPGA architecture.

[0035] In one embodiment, a force-directed quadratic placement (QP) algorithm based on a force-directed placement algorithm model is used to perform an initial global layout of the FPGA chip, so as to place each logic unit in the netlist input by the user on the FPGA chip and obtain the initial layout position of each logic unit. The quadratic linear placement algorithm is a commonly used placement algorithm, and this embodiment will not be described in detail.

[0036] The initial layout state obtained indicates the layout position of each logic unit in the user input netlist on the FPGA chip. In the initial layout state obtained, there are often problems with illegal layout, such as overlap between the layout positions of logic units. Therefore, after completing the initial layout, it is necessary to combine the layout legalization operation to perform local optimization. This application also adopts this classic layout method of global layout combined with local optimization, but this application optimizes the layout legalization process in the traditional layout process, so that the hold time can be optimized in the layout legalization process. In order to achieve this function, it is first necessary to locate each hold time critical path through step 2.

[0037] Step 2, determining the layout position of the logic cells on each hold time critical path in the user input netlist, each hold time critical path being a path that has a risk of failing to meet the hold time requirement.

[0038] The traditional approach uses static timing analysis to understand the hold time of a path, but this approach is time-consuming. This application directly analyzes the user input netlist to locate the hold time critical path. The greater the delay of the path, the more likely it is to have a setup time problem, and the less likely it is to have a hold time problem; conversely, the smaller the delay of the path, the less likely it is to have a setup time problem, but the more likely it is to have a hold time problem.

[0039] The delay of a path includes the time spent within a logical unit and the time spent between logical units. The time spent within a logical unit is relatively fixed. The fewer the number of logical units the path passes through, the shorter the delay. The closer the distance between logical units, the shorter the delay. Both of these situations will cause the path to easily have hold time problems.

[0040] Therefore, in one embodiment, the number of levels of logic units passed by each path in the user input netlist is analyzed, and whether the path has a hold time problem is determined based on the number of levels of logic units passed by each path, including: determining that a path in the user input netlist whose number of levels of logic units passed is less than a predetermined threshold is a hold time critical path, and the predetermined threshold is a custom value.

[0041] According to actual use experience, when the path passes through other logic units between the signal start point and the signal end point, the time consumption of the path is generally greater than the clock offset so that the path can meet the hold time requirement. Only when the signal start point and the signal end point do not pass through other logic units, the hold time problem is likely to occur. Therefore, in one embodiment, the predetermined threshold is 3, and each hold time critical path determined passes through two levels of logic units.

[0042] After each hold time critical path is screened out, the layout position of each logic unit on the hold time critical path in the initial layout state is recorded.

[0043] Step 3, with the optimization goal of moving the logic units on the same hold time critical path in a relatively distant trend, the initial layout state is layout legalized to determine the updated layout position of each logic unit, and the layout legalization is completed to obtain a layout result in which all paths meet the setup time requirements and the hold time requirements.

[0044] In one embodiment, a simulated annealing (SA) algorithm is used to perform local optimization to achieve layout legalization. The simulated annealing algorithm is a commonly used local optimization algorithm. This embodiment does not introduce the specific algorithm content of the simulated annealing algorithm in detail.

[0045] As mentioned above, the delay of a path is not only related to the number of logic units, but also to the distance between logic units. Therefore, the purpose of optimizing the delay of the path can be achieved by optimizing the layout position of each logic unit. In user design, the path between the starting logic module and the end logic module (usually two registers) driven by the same driving clock must simultaneously meet the two timing constraints of setup time and hold time: (1) The timing constraint of setup time is used to constrain the delay of the path to be less than the period of the driving clock of the starting logic module and the end logic module. Therefore, in order to make the path meet the timing constraint of setup time, it is hoped that the layout position of the logic modules on the path is as close as possible, so that the delay caused by the connection between the logic modules is as small as possible, and the delay of the entire path is also as small as possible, which can help to achieve the requirement of being less than the period of the driving clock. (2) The hold time timing constraint is used to constrain the path delay to be greater than the clock deviation between the starting logic module and the end logic module. Therefore, in order to make the path meet the hold time timing constraint, it is hoped that the layout position of the logic modules on the path is as far away as possible. In this way, the delay caused by the connection between the logic modules is as large as possible, and the delay of the entire path is also as large as possible, which can help to achieve the requirement of being greater than the clock deviation.

[0046] From the above theoretical analysis, it can be seen that in order to achieve the two timing constraints of setup time and hold time, the requirements for the distance of the layout position of the logic module on the path are relatively contradictory, which is why it is currently difficult to meet the two timing constraints at the same time directly through layout. Since the better the setup time, the better the circuit performance, and the hold time only needs to ensure that the requirements are met and there are no violations, and there are few actual hold time violations, the current layout ideas are to first gather the layout positions of the logic units, thereby reducing the line length between the logic units and optimizing the setup time of the path, so as to fully meet the timing constraints of the setup time, and then use timing analysis to understand the hold time situation to optimize the overall hold time, which leads to low layout efficiency.

[0047] When using the traditional simulated annealing algorithm for local legalization, for any logic unit, a layout position is randomly selected within the exchange radius of the logic unit, and the selected layout position is used as the updated layout position of the logic unit for position exchange for local optimization. The selection probability of all layout positions within the exchange radius of each logic unit is equal, which ensures that the selection within the exchange radius is random, and this random selection ensures the convergence of the algorithm.

[0048] In order to optimize the logic units on the same critical path of the hold time by moving them relatively far away from each other, the present application optimizes the above-mentioned exchange mechanism of the simulated annealing algorithm, including:

[0049] (1) Traverse a logic unit at a layout position to be optimized in a predetermined order.

[0050] (2) When the traversed logic unit is any logic unit on any hold time critical path, the selection probability of the layout position that is farther away from other logic units on the same hold time critical path within the exchange radius of the logic unit is set to be higher, and the selection probability of the layout position that is closer to other logic units on the same hold time critical path is set to be lower, and the updated layout position is selected according to the selection probability of each layout position, and the layout position is optimized using the simulated annealing algorithm. In this case, there are at least two layout positions with different selection probabilities within the exchange radius of each logic unit, thereby achieving unequal selection.

[0051] (3) When the traversed logic unit is not a logic unit on the critical path of the hold time, according to the conventional practice, the updated layout position is selected within the exchange radius of the logic unit according to the equal selection probability and the layout position is optimized using the simulated annealing algorithm.

[0052] Traverse sequentially until the traversal is completed and exit the local optimization.

[0053] Through the above optimization, the layout legalization process is optimized based on the layout positions of the logic cells on each hold time critical path determined in step 2, so that the logic cells on the same hold time critical path can be as far away as possible to meet the hold time requirement, so that the hold time problem can also be solved in the process of layout legalization, thereby improving layout efficiency.

[0054] When improving the process of local optimization using the simulated annealing algorithm, the present application still maintains the traditional simulated annealing algorithm to optimize the setup time as the main goal, so as to obtain a layout result that meets both the setup time requirement and the hold time requirement. There are two cases here:

[0055] 1. Two logic units a and b on the same hold time critical path are not located on the setup time critical path, which is a path that has the risk of failing to meet the setup time requirement. At this time, local optimization of a logic unit on a hold time critical path according to the method of this application does not affect the setup time, so the setup time requirement of the path can be met.

[0056] 2. The two logic units a and b on the same hold time critical path are also located on the same setup time critical path. At this time, the layout optimization of the logic units a and b may affect the setup time of the setup time critical path. In order to meet the basic requirement of the setup time, the embodiment further includes the following contents:

[0057] According to practical experience, the setup time critical path is mostly a long path, that is, the number of logic units passed by the setup time critical path reaches the level threshold and is large. As analyzed above, there are typically only two logic units on a hold time critical path. Therefore, the two logic units that are simultaneously located on the hold time critical path account for a small proportion of the entire setup time critical path. Discrete these two logic units will not have much impact on the timing of the entire setup time critical path.

[0058] For example, please refer to Figure 2 , the two logic units a and b on the same hold time critical path are also located on the same setup time critical path, and the preceding node Pre, logic unit a, logic unit b and the succeeding node Next are connected in sequence along the data transmission direction on the setup time critical path. The delay Delay(Pre→a→b→Next) of the preceding node Pre passing through logic unit a and logic unit b to the succeeding node Next is Delay(Pre→a→b→Next)=Delay(Pre→a)+Delay(a→b)+Delay(b→Next). When the logic units a and b on the discrete hold time critical path are connected, the delay Delay(a→b) between logic unit a and logic unit b will increase. However, by adjusting the delay Delay(Pre→a) between the preceding node Pre and logic unit a and the delay Delay(b→Next) between logic unit b and succeeding node Next, the overall delay Delay(Pre→a→b→Next) can still be guaranteed to meet the setup time requirement. In actual situations, the establishment time critical path will pass through more levels of logic units, and the increase in delay caused by discrete logic units a and logic units b will have a smaller impact on the overall situation. This shows that the present application will maintain the relative discreteness of the two logic units on the time critical path as an optimization goal and will not have too much impact on the establishment time, so that after introducing this mechanism, it can still be carried out on the basis of meeting the establishment time requirements of the establishment time critical path.

[0059] Furthermore, as mentioned above, if the path only requires that the hold time is not violated, but the setup time is expected to be superior, then when the layout position of the logic unit on the hold time critical path is updated, the setup time of the setup time critical path where it is located should also be optimized as much as possible. Figure 2 As shown, the reference line from the previous node Pre to the next node Next (such as Figure 2The delay Delay(Pre→Next) is less than Delay(Pre→a→b→Next) as shown by the dotted line, and the closer the logic unit a and the logic unit b are to the reference line from the preceding node Pre to the succeeding node Next, the closer Delay(Pre→a→b→Next) is to Delay(Pre→Next) and the smaller it is. This can reduce the delay of the critical path of the setup time as much as possible while satisfying the requirement of Delay(a→b) to optimize the setup time, thereby optimizing the circuit performance.

[0060] Therefore, based on this analysis, when performing layout legalization, according to the reference connection from the preceding node Pre to the succeeding node Next, the two logic units a and b on the same critical path for maintaining time can be moved relatively far away from each other on the basis of optimizing the establishment time requirement of the critical path for establishing time, and the initial layout state can be legalized as the optimization target. Including: on the basis of keeping the distance between logic unit a and logic unit b and the reference connection line not exceeding a predetermined threshold, the initial layout state is legalized as the optimization target for moving logic unit a and logic unit b relatively far away from each other. Thereby, logic unit a and logic unit b can be kept discrete near the reference connection line to achieve the effect of optimizing the establishment time while achieving discreteness. On the basis of this optimization principle:

[0061] On the basis of keeping the distance between the logic unit a and the reference line not exceeding the predetermined threshold, the logic unit a is taken as the optimization target along the direction close to the previous node Pre. This is also achieved by adjusting the selection probability of the layout position, including: setting the selection probability of the layout position with a smaller distance from the reference line and the previous node Pre within the exchange radius of the logic unit a to be higher, selecting the updated layout position according to the selection probability of each layout position within the exchange radius of the logic unit a, and optimizing the layout position of the logic unit a using the simulated annealing algorithm.

[0062] and / or,

[0063] On the basis of keeping the distance between the logic unit b and the reference line not exceeding a predetermined threshold, the logic unit b is moved in the direction close to the subsequent node Next as the optimization target. This is also achieved by adjusting the selection probability of the layout position, including: setting the selection probability of the layout position within the exchange radius of the logic unit b, the smaller the distance between the logic unit b and the reference line and the subsequent node Next, the higher the selection probability, selecting the updated layout position according to the selection probability of each layout position within the exchange radius of the logic unit b, and optimizing the layout position of the logic unit b using the simulated annealing algorithm.

Claims

1. A layout method for optimizing holding time, characterized in that: The layout method comprises: Obtaining a user input netlist corresponding to the FPGA chip, and laying out the FPGA chip according to the user input netlist to obtain an initial layout state, wherein the initial layout state indicates a layout position of each logic unit in the user input netlist; Determine that a path in the user input netlist, through which the number of levels of logic units is less than a predetermined threshold, is a hold time critical path, and determine the layout position of the logic units on each hold time critical path in the user input netlist, each hold time critical path is a path that has a risk of failing to meet the hold time requirement, and each hold time critical path passes through two levels of logic units; Taking the logic units on the same hold time critical path as the optimization goal to be moved in a relatively distant trend, the initial layout state is layout legalized to determine the updated layout position of each logic unit, and the layout legalization is completed to obtain a layout result in which all paths meet the setup time requirement and the hold time requirement; The layout legalization of the initial layout state includes: when two logic units a and logic units b on the same hold time critical path are also located on the same setup time critical path, and the preceding node Pre, the logic unit a, the logic unit b and the succeeding node Next are sequentially connected along the data transmission direction on the setup time critical path, the initial layout state is layout legalized according to a reference connection from the preceding node Pre to the succeeding node Next, with the two logic units a and b on the same hold time critical path being moved in a relatively distant trend as an optimization target on the basis of optimizing the setup time of the setup time critical path; wherein the setup time critical path is a path that has a risk of failing to meet the setup time requirement.

2. The layout method according to claim 1, characterized in that: Legalizing the initial layout state includes: For any logic unit on the hold time critical path, the farther the distance between the logic unit and other logic units on the same hold time critical path is within the exchange radius, the higher the selection probability of the layout position is, and the closer the distance between the logic unit and other logic units on the same hold time critical path is, the lower the selection probability of the layout position is. According to the selection probability of each layout position, the updated layout position is selected and the layout position is optimized using a simulated annealing algorithm.

3. The layout method according to claim 1, characterized in that: Legalizing the layout of the initial layout state according to the reference connection from the preceding node Pre to the succeeding node Next includes: The initial layout state is layout legalized with the optimization goal of moving the logic unit a and the logic unit b relatively away from each other while keeping the distances between the logic unit a and the logic unit b and the reference connection line not exceeding a predetermined threshold.

4. The layout method according to claim 3, characterized in that: Legalizing the layout of the initial layout state according to the reference connection from the preceding node Pre to the succeeding node Next also includes: On the basis of keeping the distance between the logic unit a and the reference line not exceeding a predetermined threshold, the logic unit a is taken as an optimization target in a direction close to the previous node Pre; And / or, on the basis of keeping the distance between the logic unit b and the reference line not exceeding a predetermined threshold, moving the logic unit b in a direction close to the subsequent node Next is taken as an optimization target.

5. The layout method according to claim 4, characterized in that: Optimizing the layout position of the logic unit a includes: The smaller the distance between the logic unit a and the reference connection line within the exchange radius and the smaller the distance between the logic unit a and the preceding node Pre, the higher the selection probability of the layout position is set. According to the selection probability of each layout position within the exchange radius of the logic unit a, the updated layout position is selected and the layout position of the logic unit a is optimized using the simulated annealing algorithm.

6. The layout method according to claim 4, characterized in that: Optimizing the layout position of the logic unit b includes: The smaller the distance between the logic unit b and the reference line within the exchange radius and the smaller the distance between the logic unit b and the subsequent node Next, the higher the selection probability of the layout position is set. According to the selection probability of each layout position within the exchange radius of the logic unit b, the updated layout position is selected and the layout position of the logic unit b is optimized using the simulated annealing algorithm.

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