FPGA clock glitch-free switching circuit

Abstract

The present invention provides an FPGA clock glitch-free switching circuit, which relates to the field of FPGA technology. The circuit comprises: a first clock circuit, which comprises a first AND gate, a first CDC processing circuit and a first D flip-flop; a second clock circuit, which comprises an inverter, a second AND gate, a second CDC processing circuit and a second D flip-flop; and a BUFGCTRL unit. By reasonably utilizing the basic primitive device BUFGCTRL of the existing FPGA and combining the design idea of ​​the free‑glitch circuit of the non-correlated clock switching that only ASIC proprietary chips have, the problems of skew, jitters, glitch, etc. existing in the existing gated clock technology can be effectively solved, thereby realizing FPGA clock glitch-free switching, and providing a strong design foundation for variable frequency FPGA low power consumption technology.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to an FPGA clock glitch-free switching circuit. Background Art

[0002] In the design of Application Specific Integrated Circuit (ASIC) chips, one of the low-power measures for the design is gated clock. Gated clock refers to the clock generated by combinational logic, where the input of the combinational logic can be all data signals or include the original clock signal. Since the basic units in the combinational logic are gate circuits such as AND, OR, and NOT gates, and AND gates and NOT gates have "switching properties", this type of clock is also called a gated clock.

[0003] However, in Field Programmable Gate Array (FPGA) design, since the problems of glitch (signal burr), skew (clock deviation), and jitters (clock jitter) cannot be solved, gated clocks are rarely used. For FPGA products with clock frequency switching, the clock switching requirements are solved at the system level at the expense of business continuity, for example: preparing multiple FPGA configuration files, each of which uses a different clock frequency. This method has great limitations. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides an FPGA clock glitch-free switching circuit.

[0005] In a first aspect, the present invention provides an FPGA clock glitch-free switching circuit, comprising:

[0006] A first clock circuit, the first clock circuit comprising a first AND gate, a first CDC processing circuit and a first D flip-flop;

[0007] a second clock circuit, the second clock circuit comprising an inverter, a second AND gate, a second CDC processing circuit and a second D flip-flop;

[0008] and BUFGCTRL unit;

[0009] Wherein, a clock selection signal is input to the first input terminal of the first AND gate, an inverting output terminal of the second D flip-flop is connected to the second input terminal of the first AND gate, an output signal of the first AND gate is input to the first CDC processing circuit, an output signal of the first CDC processing circuit is input to the data input terminal of the first D flip-flop, an output terminal of the first D flip-flop is connected to the first enable terminal of the BUFGCTRL unit, and a first clock signal is input to the first CDC processing circuit, the clock input terminal of the first D flip-flop, and the first input terminal of the BUFGCTRL unit;

[0010] The inverting output terminal of the first D flip-flop is connected to the first input terminal of the second AND gate, the clock selection signal is inverted by the inverter and input to the second input terminal of the second AND gate, the output signal of the second AND gate is input to the second CDC processing circuit, the output signal of the second CDC processing circuit is input to the data input terminal of the second D flip-flop, the output terminal of the second D flip-flop is connected to the second enable terminal of the BUFGCTRL unit, and the second clock signal is input to the second CDC processing circuit, the clock input terminal of the second D flip-flop, and the second input terminal of the BUFGCTRL unit;

[0011] The output of the BUFGCTRL unit is a gated clock signal.

[0012] In some embodiments, the first CDC processing circuit includes a third D flip-flop and a fourth D flip-flop;

[0013] Among them, the output signal of the first AND gate is input into the data input end of the third D flip-flop, the output end of the third D flip-flop is connected to the data input end of the fourth D flip-flop, the output end of the fourth D flip-flop is connected to the data input end of the first D flip-flop, and the first clock signal is input into the clock input end of the third D flip-flop and the clock input end of the fourth D flip-flop.

[0014] In some embodiments, the third D flip-flop and the fourth D flip-flop are both rising-edge triggered D flip-flops.

[0015] In some embodiments, the second CDC processing circuit includes a fifth D flip-flop and a sixth D flip-flop;

[0016] Among them, the output signal of the second AND gate is input into the data input terminal of the fifth D flip-flop, the output terminal of the fifth D flip-flop is connected to the data input terminal of the sixth D flip-flop, the output terminal of the sixth D flip-flop is connected to the data input terminal of the second D flip-flop, and the second clock signal is input into the clock input terminal of the fifth D flip-flop and the clock input terminal of the sixth D flip-flop.

[0017] In some embodiments, the fifth D flip-flop and the sixth D flip-flop are both rising-edge triggered D flip-flops.

[0018] In some embodiments, the first D flip-flop and / or the second D flip-flop is a falling edge triggered D flip-flop.

[0019] In some embodiments, a maximum delay between an output terminal of the fourth D flip-flop and a data input terminal of the first D flip-flop is less than or equal to a half period of the first clock signal.

[0020] In some embodiments, a maximum delay between an output terminal of the sixth D flip-flop and a data input terminal of the second D flip-flop is less than or equal to a half period of the second clock signal.

[0021] In some embodiments, a maximum delay between an output terminal of the first D flip-flop and a first enable terminal of the BUFGCTRL unit is less than or equal to a half period of the first clock signal.

[0022] In some embodiments, a maximum delay between an output terminal of the second D flip-flop and a second enable terminal of the BUFGCTRL unit is less than or equal to a half period of the second clock signal.

[0023] The FPGA clock glitch-free switching circuit provided by the present invention can effectively solve the problems of skew, jitters, glitch, etc. existing in the existing gated clock technology by reasonably utilizing the basic primitive device BUFGCTRL of the existing FPGA and combining the design concept of the free-glitch circuit for the non-correlated clock switching that is only available in ASIC proprietary chips, thereby realizing FPGA clock glitch-free switching and providing a strong design foundation for variable frequency FPGA low power consumption technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of the structure of the FPGA clock glitch-free switching circuit provided by the present invention;

[0026] Figure 2 This is an example diagram of the FPGA clock glitch-free switching circuit provided by the present invention. DETAILED DESCRIPTION

[0027] In the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0028] In the present invention, the term "plurality" refers to two or more than two, and other quantifiers are similar to them.

[0029] In the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In order to more clearly understand the technical solution of the present invention, some technical contents related to the present invention are first introduced.

[0032] In ASIC chip design, one of the low-power measures for the design is gating the clock. In ASIC, the clock tree (a set of networks and buffers) that distributes the clock to all clock elements is built specifically for each device. As a result, a clock tree with almost any logic in the tree can be used to gate a specific clock or clock group. The clock tree is used to handle all of this, including adapting to delays through gating elements. Generally, clock free-glitch switching circuits are used to switch clocks in ASICs.

[0033] However, in FPGA design, gated clocks are rarely used. Generally, they are used to generate low-frequency clocks. For example, when clock management devices such as digital clock managers (DCM) and phase-locked loops (PLL) cannot generate low-frequency clock signals, they are used to drive the trigger count with a high-frequency clock, thus generating a gated clock. However, the skew and jitters of the gated clock generated in this way cannot be guaranteed, and low-frequency clock signals (below 10MHz) can only be used if they are not sensitive to skew and jitters.

[0034] In the field of traditional gated clock switching, since the problems of glitch, skew, and jitters cannot be solved, the clock switching requirements for FPGA products with clock frequency switching are solved at the system level at the expense of business continuity. Generally, multiple FPGA configuration files are prepared, and each FPGA configuration file uses a different clock frequency. This method is acceptable in some scenarios, but for some special scenarios such as field single-soldier combat scenarios, storing one more FPGA configuration file will sacrifice a part of the precious system storage space and also increase the workload of version management (if a certain FPGA configuration file is broken, the system will crash). The technical solution provided by the present invention solves this problem, and the saved space can be used to store several more identical FPGA configuration files to increase the quality and reliability of the system (it is not a problem if one or several files are broken, as long as one is good), or it can be used to record field logs or store several more combat or survival instructions to increase the chances of winning or surviving a single soldier, etc.

[0035] In the field of gated clock switching technology, relevant FPGA design guidance documents clearly recommend that you try not to use gated clocks in your design. The reason is that in FPGAs, the clock trees are fixed (they are dedicated networks and buffers responsible for distributing clocks to all elements), and it is impossible to perform any possible gating in FPGAs.

[0036] At present, FPGA engineers in the industry will completely use the clock-free glitch circuit of ASIC, but this is very problematic because it still directly uses logic gate circuits to gate the clock. In this case, the clock routing is as follows: the clock that needs to be gated needs to leave the clock network, use general routing resources to route to the LUT (gate circuit), and then use general resources to route back to the clock network. It is difficult to ensure that the clock gating of the LUT is free-glitch, and more importantly, all additional routing traces (including additional global clock buffers (BUFG) / horizontal clock buffers (BUFH)) will make the clock arrive later than any clock that stays on the clock tree (delay caused by additional routing) (here we are talking about applying the free-glitch clock switching circuit of ASIC, and the final output is the two gated clocks after the gate signals are ANDed and then output by the OR gate). What is even more troublesome is that the extra delay is extremely difficult to ensure that it is fixed every time the FPGA is recompiled, because this is related to the FPGA layout and routing algorithm (not discussed in depth here). The LUT and general routing resources selected after each FPGA routing are inconsistent, which will cause the skew to be different every time. What is more troublesome is that the clock is routed on the general routing resources, and its ability to resist jitters is greatly reduced. It may even be disturbed on the general routing to form jitters and eventually be brought back to the clock tree, causing all the timing circuits driven by the clock tree to become unreliable. In serious cases, the entire FPGA function will become unreliable.

[0037] Even if the algorithm seed interface or position constraint LUT-PATH-BUFG path provided by the electronic design automation (EDA) tool is properly utilized to achieve temporary layout and routing success, this will lead to a very serious consequence: the configuration file generated by the FPGA is not reproducible or can be reproduced, but as long as the new logic function is added, the original method of fixing the seed and constraining the LUT-PATH-BUFG path becomes invalid, which actually makes it impossible to iterate the product series. This is unsustainable for all scientific research companies that are constantly iterating and improving based on technology and products.

[0038] In view of the above problems, the present invention proposes an applicable, reproducible, and escalable interference-free gated clock free-glitch switching technology to solve the problem of "being afraid of 'gated clock'" in the FPGA development field and trying to avoid or not touch it as much as possible.

[0039] Figure 1The schematic diagram of the structure of the FPGA clock glitch-free switching circuit provided by the present invention is as follows: Figure 1 As shown, the FPGA clock glitch-free switching circuit includes:

[0040] A first clock circuit 100, the first clock circuit comprising a first AND gate 101, a first CDC processing circuit 102 and a first D flip-flop 103;

[0041] A second clock circuit 110, the second clock circuit comprising an inverter 111, a second AND gate 112, a second CDC processing circuit 113 and a second D flip-flop 114;

[0042] and a BUFGCTRL unit 120;

[0043] Wherein, the clock selection signal (CLK_SELECT) is input to the first input terminal of the first AND gate 101, the inverting output terminal (Qn terminal) of the second D flip-flop 114 is connected to the second input terminal of the first AND gate 101, the output signal of the first AND gate 101 is input to the first CDC processing circuit 102, the output signal of the first CDC processing circuit 102 is input to the data input terminal (D terminal) of the first D flip-flop 103, the output terminal (Q terminal) of the first D flip-flop 103 is connected to the first enable terminal (CE0) of the BUFGCTRL unit 120, and the first clock signal (CLK0) is input to the first CDC processing circuit 102, the clock input terminal of the first D flip-flop 103, and the first input terminal (I0) of the BUFGCTRL unit 120;

[0044] The inverting output terminal (Qn terminal) of the first D flip-flop 103 is connected to the first input terminal of the second AND gate 112, the clock selection signal (CLK_SELECT) is inverted by the inverter 111 and input to the second input terminal of the second AND gate 112, the output signal of the second AND gate 112 is input to the second CDC processing circuit 113, the output signal of the second CDC processing circuit 113 is input to the data input terminal (D terminal) of the second D flip-flop 114, the output terminal (Q terminal) of the second D flip-flop 114 is connected to the second enable terminal (CE1) of the BUFGCTRL unit 120, the second clock signal (CLK1) is input to the second CDC processing circuit 113, the clock input terminal of the second D flip-flop 114, and the second input terminal (I1) of the BUFGCTRL unit 120;

[0045] The output of BUFGCTRL unit 120 is a gated clock signal (GATED_CLK).

[0046] Specifically, the FPGA clock glitch-free switching circuit designed by the present invention utilizes the basic primitive device BUFGCTRL (Global Clock Control Buffer) of the existing FPGA and combines the free-glitch irrelevant clock switching circuit design concept of ASIC to combine the two into one, without removing the clock to be gated from the clock tree, thereby avoiding a series of interference (glitch, skew, jitters) problems caused by it.

[0047] In an embodiment of the present invention, the CDC processing circuit refers to a clock domain crossing (Clock Domain Crossing, CDC) processing circuit, which is used to eliminate glitches and cross the gated signal into the gated clock domain. For example, the first CDC processing circuit is used to cross the output signal of the first AND gate into the clock domain of the first clock signal (CLK0), and the second CDC processing circuit is used to cross the output signal of the second AND gate into the clock domain of the second clock signal (CLK1).

[0048] In some embodiments, the first CDC processing circuit includes a third D flip-flop and a fourth D flip-flop;

[0049] Among them, the output signal of the first AND gate is input into the data input end of the third D flip-flop, the output end of the third D flip-flop is connected to the data input end of the fourth D flip-flop, the output end of the fourth D flip-flop is connected to the data input end of the first D flip-flop, and the first clock signal is input into the clock input end of the third D flip-flop and the clock input end of the fourth D flip-flop.

[0050] Figure 2 This is an example diagram of the FPGA clock glitch-free switching circuit provided by the present invention, such as Figure 2 As shown, the first CDC processing circuit can be implemented by two-stage flip-flops to eliminate glitches and bring the output signal of the first AND gate into the clock domain of CLK0. Figure 2 FF1 in is the third D flip-flop. Figure 2 FF2 in is the fourth trigger. Figure 2 In the figure, the output signal of AND1 (i.e. the first AND gate) is input into the D terminal of FF1, CLK0 is input into the clock input terminal of FF1, the signal output from the Q terminal of FF1 is input into the D terminal of FF2, and at the same time, CLK0 is input into the clock input terminal of FF2, and the signal output from the Q terminal of FF2 is input into the D terminal of FF3 (i.e. the first D flip-flop).

[0051] In some embodiments, the third D flip-flop and the fourth D flip-flop are both rising edge triggered D flip-flops, that is, rising edge effective D flip-flops, or positive edge driven D flip-flops. Figure 2 FF1 and FF2 in .

[0052] In some embodiments, the first D flip-flop is a falling edge triggered D flip-flop, that is, a falling edge effective D flip-flop, or a negative edge driven D flip-flop. Figure 2 FF3 in.

[0053] In some embodiments, the second CDC processing circuit includes a fifth D flip-flop and a sixth D flip-flop;

[0054] Among them, the output signal of the second AND gate is input into the data input terminal of the fifth D flip-flop, the output terminal of the fifth D flip-flop is connected to the data input terminal of the sixth D flip-flop, the output terminal of the sixth D flip-flop is connected to the data input terminal of the second D flip-flop, and the second clock signal is input into the clock input terminal of the fifth D flip-flop and the clock input terminal of the sixth D flip-flop.

[0055] like Figure 2 As shown, the second CDC processing circuit can be implemented by a two-stage flip-flop to eliminate glitches and bring the output signal of the second AND gate into the clock domain of CLK1. Figure 2 FF4 in is the fifth D flip-flop. Figure 2 FF5 in is the sixth trigger. Figure 2 In the figure, the output signal of AND2 (i.e., the second AND gate) is input into the D terminal of FF4, CLK1 is input into the clock input terminal of FF4, the signal output from the Q terminal of FF4 is input into the D terminal of FF5, and at the same time, CLK1 is input into the clock input terminal of FF5, and the signal output from the Q terminal of FF5 is input into the D terminal of FF6 (i.e., the second D flip-flop).

[0056] In some embodiments, the fifth D flip-flop and the sixth D flip-flop are both rising edge triggered D flip-flops, that is, rising edge effective D flip-flops, or positive edge driven D flip-flops. Figure 2 FF4 and FF5 in.

[0057] In some embodiments, the second D flip-flop is a falling edge triggered D flip-flop, that is, a falling edge effective D flip-flop, or a negative edge driven D flip-flop. Figure 2 FF6 in.

[0058] In some embodiments, a maximum delay between an output terminal of the fourth D flip-flop and a data input terminal of the first D flip-flop is less than or equal to a half period of the first clock signal.

[0059] Specifically, in order to ensure that the first D flip-flop can stably sample the value output by the fourth D flip-flop, in the embodiment of the present invention, the maximum delay (max_delay) between the output terminal of the fourth D flip-flop and the data input terminal of the first D flip-flop can be constrained to be less than or equal to half a period of the first clock signal. Figure 2As shown, the max_delay of FF3 and FF2 can be constrained to be half the clock of CLK0, ensuring that FF3 can stably sample the value output by FF2.

[0060] In some embodiments, a maximum delay between an output terminal of the sixth D flip-flop and a data input terminal of the second D flip-flop is less than or equal to a half period of the second clock signal.

[0061] Similarly, in order to ensure that the second D flip-flop can stably sample the value output by the sixth D flip-flop, in the embodiment of the present invention, the maximum delay (max_delay) between the output terminal of the sixth D flip-flop and the data input terminal of the second D flip-flop can be constrained to be less than or equal to half a period of the second clock signal. Figure 2 As shown, the max_delay of FF6 and FF5 can be constrained to be half the clock of CLK1, ensuring that FF6 can stably sample the value output by FF5.

[0062] In some embodiments, a maximum delay between an output terminal of the first D flip-flop and a first enable terminal of the BUFGCTRL unit is less than or equal to a half period of the first clock signal.

[0063] like Figure 2 As shown, the timing requirement can be made according to the delay of the path from the Q end of FF3 to BUFGCTRL being no greater than half of CLK0, thereby ensuring that the signal of CE0 reaches the pin corresponding to BUFGCTRL within half a cycle of CLK0.

[0064] In some embodiments, a maximum delay between an output terminal of the second D flip-flop and a second enable terminal of the BUFGCTRL unit is less than or equal to a half period of the second clock signal.

[0065] Similarly, in order to ensure that the CE1 signal reaches the pin corresponding to BUFGCTRL within half a cycle of CLK1, such as Figure 2 As shown, the timing requirement can be met based on the delay of the path from the Q-end output of FF6 to BUFGCTRL being no greater than half of CLK1.

[0066] The FPGA clock glitch-free switching circuit provided by the present invention can effectively solve the problems of skew, jitters, glitch, etc. existing in the existing gated clock technology by reasonably utilizing the basic primitive device BUFGCTRL of the existing FPGA and combining the design concept of the free-glitch circuit for the non-correlated clock switching that is only available in ASIC proprietary chips, thereby realizing FPGA clock glitch-free switching and providing a strong design foundation for variable frequency FPGA low power consumption technology.

[0067] The following combination Figure 2The work flow of the FPGA clock glitch-free switching circuit provided by the present invention is described. The generation processes of CE1 and CE0 are basically the same. Only the control circuit work flow of CE0 is illustrated below, and CE1 can be executed with reference, and no further description is given.

[0068] The control circuit workflow of CE0 mainly includes:

[0069] (1) After the FPGA is powered on and reset or GLOBAL_RESET (global reset), all trigger outputs are 0, so no CLK will be selected at this time.

[0070] (2) When CLK_SELECT is set, because the Qn outputs of all flip-flops are 1, the output is 1 after passing through the AND gate.

[0071] (3) Considering that the combinational logic has glitches, the glitches are eliminated through the CDC operation of the two-stage trigger, and the signal is transferred to the clock domain of CLK0.

[0072] (4) Then use the negative edge driven trigger to drive. Here, in the constraint file, it is necessary to constrain the max_delay of FF3 and FF2 to half the clock of CLK0 to ensure that FF3 can stably sample the value output by FF2.

[0073] (5) In this case, the Q value output by FF3 must be earlier than CLK0, and the period constraint is based on the timing requirement that the path from the Q end of FF3 to BUFGCTRL should not exceed the delay of half CLK0.

[0074] (6) In this way, the CLK0 output can be gated. When you want to gate CLK1, the process is similar.

[0075] In this example: a) CE 0 and CE1 are not valid at the same time; b) when CE0 and CE1 are both invalid, BUFGCTRL maintains the current state; c) the signals of CE0 and CE1 will be earlier than half a cycle of the clock they control, as long as the routing length of CE0 and CE1 reaches the pin corresponding to BUFGCTRL within half a cycle. By rationally utilizing the primitive devices provided by FPGA, combined with the mature free-glitch circuit of ASIC and basic FPGA constraints, the purpose of stable and reliable FPGA clock glitch-free switching circuit is achieved.

[0076] The device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0077] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An FPGA clock glitch-free switching circuit, characterized in that: include: A first clock circuit, the first clock circuit comprising a first AND gate, a first CDC processing circuit and a first D flip-flop; a second clock circuit, the second clock circuit comprising an inverter, a second AND gate, a second CDC processing circuit and a second D flip-flop; and BUFGCTRL unit; Wherein, a clock selection signal is input to the first input terminal of the first AND gate, an inverting output terminal of the second D flip-flop is connected to the second input terminal of the first AND gate, an output signal of the first AND gate is input to the first CDC processing circuit, an output signal of the first CDC processing circuit is input to the data input terminal of the first D flip-flop, an output terminal of the first D flip-flop is connected to the first enable terminal of the BUFGCTRL unit, and a first clock signal is input to the first CDC processing circuit, the clock input terminal of the first D flip-flop, and the first input terminal of the BUFGCTRL unit; The inverting output terminal of the first D flip-flop is connected to the first input terminal of the second AND gate, the clock selection signal is inverted by the inverter and input to the second input terminal of the second AND gate, the output signal of the second AND gate is input to the second CDC processing circuit, the output signal of the second CDC processing circuit is input to the data input terminal of the second D flip-flop, the output terminal of the second D flip-flop is connected to the second enable terminal of the BUFGCTRL unit, and the second clock signal is input to the second CDC processing circuit, the clock input terminal of the second D flip-flop, and the second input terminal of the BUFGCTRL unit; The output of the BUFGCTRL unit is a gated clock signal; The first CDC processing circuit includes a third D flip-flop and a fourth D flip-flop; Wherein, the output signal of the first AND gate is input to the data input terminal of the third D flip-flop, the output terminal of the third D flip-flop is connected to the data input terminal of the fourth D flip-flop, the output terminal of the fourth D flip-flop is connected to the data input terminal of the first D flip-flop, and the first clock signal is input to the clock input terminal of the third D flip-flop and the clock input terminal of the fourth D flip-flop; The second CDC processing circuit includes a fifth D flip-flop and a sixth D flip-flop; Wherein, the output signal of the second AND gate is input to the data input terminal of the fifth D flip-flop, the output terminal of the fifth D flip-flop is connected to the data input terminal of the sixth D flip-flop, the output terminal of the sixth D flip-flop is connected to the data input terminal of the second D flip-flop, and the second clock signal is input to the clock input terminal of the fifth D flip-flop and the clock input terminal of the sixth D flip-flop; The maximum delay between the output terminal of the fourth D flip-flop and the data input terminal of the first D flip-flop is less than or equal to a half period of the first clock signal; The maximum delay between the output terminal of the sixth D flip-flop and the data input terminal of the second D flip-flop is less than or equal to a half cycle of the second clock signal; The maximum delay between the output terminal of the first D flip-flop and the first enable terminal of the BUFGCTRL unit is less than or equal to a half period of the first clock signal; A maximum delay between an output terminal of the second D flip-flop and a second enable terminal of the BUFGCTRL unit is less than or equal to a half period of the second clock signal.

2. The FPGA clock glitch-free switching circuit according to claim 1, characterized in that: The third D flip-flop and the fourth D flip-flop are both rising-edge triggered D flip-flops.

3. The FPGA clock glitch-free switching circuit according to claim 1, characterized in that: The fifth D flip-flop and the sixth D flip-flop are both rising-edge triggered D flip-flops.

4. The FPGA clock glitch-free switching circuit according to claim 2 or 3, characterized in that: The first D flip-flop and / or the second D flip-flop is a falling edge triggered D flip-flop.

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