Chip tester clock synchronization method and device, electronic equipment and storage medium

Abstract

The application relates to the chip testing technical field, in particular to a chip tester clock synchronization method and device, electronic equipment and storage medium. The chip tester comprises a main backboard and a plurality of slave backboards, the main backboard comprises a high-precision clock chip and a first programmable logic chip, the method comprises the following steps: in response to an instruction for performing clock synchronization processing, a low-frequency detection clock signal with a preset frequency is configured and sent; when the low-frequency detection clock signal is detected, a high-precision clock signal with a target frequency is configured based on the high-precision clock chip, and the target frequency is higher than the preset frequency; when it is verified that the clock signals currently acquired by the first programmable logic chip and a second programmable logic chip satisfy preset state constraint conditions, the high-precision clock signal is sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip, so as to complete clock synchronization of all test board cards. The method can improve the precision and stability of clock synchronization processing.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing machine clock synchronization method, apparatus, electronic device, and storage medium. Background Technology

[0002] A digital chip tester is a specialized device used to test and verify the performance and functionality of digital chips (such as integrated circuits, processors, FPGAs, etc.). It typically consists of hardware and software and can perform various tests and measurements on the chip to ensure it functions correctly within its design specifications and expected performance range. Digital chip testers can perform electrical tests, timing tests, logic function tests, performance tests, reliability tests, and other functions. Digital chip testers play a crucial role in the chip design and manufacturing process, helping developers and manufacturers ensure chip quality and performance, and identify and resolve potential problems and defects.

[0003] To ensure chip reliability, digital chip testers typically utilize pattern (timing chip) testing to determine if the chip functions correctly, thereby enabling rapid testing during large-scale mass production of digital chips. Digital chip testers generally support hundreds of pattern test channels, such as 512, 768, or 1024 channels. The pattern digital waveform output from each channel needs to be simultaneously output to the pins of the digital chip under test (DUT), meaning the pattern digital waveforms need edge alignment to ensure correct timing between signals output to the DUT pins. To achieve this, ensuring edge alignment of the digital waveforms output from all pattern channels of all digital chip testers requires that the clocks of each digital measurement card be synchronized.

[0004] In related technologies, in order to synchronize the clock signals of multiple digital chip testers, it is usually necessary to connect multiple test backplanes according to their master-slave mode, and to make the pattern module use the first edge of the input clock to trigger the start of the clock. That is, it is necessary to ensure that the first edge of the clock used to control synchronization in the pattern module must be fully synchronized.

[0005] However, current clock synchronization methods for digital chip testing machines have the following technical problems:

[0006] Different chip testing machines may have different proprietary clock chips, which makes it difficult for the pattern module to detect the first edge of the latest clock according to a unified standard during clock switching, resulting in difficulties in clock synchronization processing. Summary of the Invention

[0007] Therefore, it is necessary to provide a chip tester clock synchronization method, device, electronic device, and computer-readable storage medium that can improve the accuracy and stability of clock synchronization processing of multiple chip testers in a multi-chip tester system, in order to address the above-mentioned technical problems.

[0008] In a first aspect, this application provides a clock synchronization method for a chip testing machine. The chip testing machine includes a main backplane and several slave backplanes, each of which is communicatively connected to multiple test boards. The main backplane includes a high-precision clock chip and a first programmable logic chip, and each slave backplane includes a second programmable logic chip. The method includes:

[0009] In response to the instruction to perform clock synchronization processing on the multiple test boards, a low-frequency detection clock signal of a preset frequency is configured and sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip configuration.

[0010] When the first programmable logic chip detects the low-frequency detection clock signal, it configures a high-precision clock signal with a target frequency based on the high-precision clock chip, wherein the target frequency is higher than the preset frequency.

[0011] When the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are verified to meet the preset state constraints, the high-precision clock signal is sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip to complete the clock synchronization of all the test boards.

[0012] In one embodiment, the step of detecting the low-frequency detection clock signal when the first programmable logic chip detects the following further includes:

[0013] The first programmable logic chip sends a trigger signal to the second programmable logic chip;

[0014] The trigger signal instructs the first programmable logic chip and the second programmable logic chip to perform synchronous timing.

[0015] In one embodiment, instructing the first programmable logic chip and the second programmable logic chip to perform synchronized timing based on the trigger signal includes:

[0016] When the timing of the first programmable logic chip reaches a first preset duration and the timing of the second programmable logic chip reaches a second preset duration, it is determined that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

[0017] In one embodiment, before instructing the first programmable logic chip and the second programmable logic chip to perform synchronized timing based on the trigger signal, the method further includes:

[0018] Disable the enable channel between the test board and the main backplane and the slave backplane associated with the test board.

[0019] In one embodiment, after configuring and sending a low-frequency detection clock signal of a preset frequency to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip, the method further includes:

[0020] In response to the detection of the main backplane and the slave backplane, the start flag is set and the timing is started;

[0021] When the second programmable logic chip reaches the second preset duration, it is determined that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip have been synchronized.

[0022] Enable the channel to send the high-precision clock signal to the target test board relative to the target backplane.

[0023] In one embodiment, the main backplane includes a first system clock chip, the slave backplane includes a second system clock chip, and prior to the instruction to perform clock synchronization processing on the plurality of test boards, the method further includes:

[0024] Configure the initial clock of the corresponding backplane based on the first system clock chip and the second system clock chip, so as to complete the system clock configuration of the main backplane and the slave backplane.

[0025] In one embodiment, the trigger signal is a synchronization start pulse signal generated by the first programmable logic chip at the rising edge of the low-frequency detection clock signal, using the system clock as a reference clock.

[0026] Secondly, this application also provides a clock synchronization device for a chip testing machine. The chip testing machine includes a main backplane and several slave backplanes. The main backplane and the slave backplanes are communicatively connected to multiple test boards. The main backplane includes a high-precision clock chip and a first programmable logic chip, and the slave backplanes include a second programmable logic chip. The method includes:

[0027] The low-frequency detection clock module is used to respond to the instruction to perform clock synchronization processing on multiple test boards, and to send a low-frequency detection clock signal of a preset frequency to the first programmable logic chip and the second programmable logic chip based on the configuration of the high-precision clock chip.

[0028] A high-precision clock configuration module is used to configure a high-precision clock signal with a target frequency based on the high-precision clock chip when the first programmable logic chip detects the low-frequency detection clock signal, wherein the target frequency is higher than the preset frequency.

[0029] The clock synchronization module is used to send the high-precision clock signal to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip when verifying that the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip meet the preset state constraints, so as to complete the clock synchronization of all the test boards.

[0030] In one embodiment, the high-precision clock configuration module further includes:

[0031] A trigger signal generation module is used to send a trigger signal to the second programmable logic chip based on the first programmable logic chip.

[0032] A synchronous timing module is used to instruct the first programmable logic chip and the second programmable logic chip to perform synchronous timing based on the trigger signal.

[0033] In one embodiment, the synchronization timing module includes:

[0034] The synchronization verification module is used to determine that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent when the timing of the first programmable logic chip reaches a first preset duration and the timing of the second programmable logic chip reaches a second preset duration. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

[0035] In one embodiment, prior to the synchronization timing module, the system further includes:

[0036] An enable channel limiting module is used to disable the enable channel between the test board and the main backplane and the slave backplane associated with the test board.

[0037] In one embodiment, after the low-frequency detection clock module, the system further includes:

[0038] A timing start module is used to set the start flag and start timing in response to the detection of the main backplane and the slave backplane;

[0039] The synchronization completion module is used to determine that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip are synchronized when the second programmable logic chip reaches the second preset time.

[0040] An enable channel opening module is used to open the enable channel to send the high-precision clock signal to the corresponding target test board based on the target backplane.

[0041] In one embodiment, the main backplane includes a first system clock chip, the slave backplane includes a second system clock chip, and before the low-frequency detection clock module, it further includes:

[0042] The system clock configuration module is used to configure the initial clock of the corresponding backplane based on the first system clock chip and the second system clock chip, so as to complete the system clock configuration of the main backplane and the slave backplane.

[0043] In one embodiment, the trigger signal is a synchronization start pulse signal generated by the first programmable logic chip at the rising edge of the low-frequency detection clock signal, using the system clock as a reference clock.

[0044] Thirdly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of a chip testing machine clock synchronization method as described in any embodiment of the first aspect.

[0045] Fourthly, this application also provides an electronic device. It includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the at least one processor implements a chip testing machine clock synchronization method as described in any one of the first aspects by executing the instructions stored in the memory.

[0046] The aforementioned chip testing machine clock synchronization method, apparatus, computer equipment, storage medium, and computer program product, derived through the technical features described in the patent, can achieve the following beneficial effects to address the technical problems in the background art:

[0047] In the clock synchronization processing of the chip testing machine, after receiving the instruction to synchronize the clocks of multiple test boards, a low-frequency detection clock signal with a preset frequency is first configured based on the high-precision clock chip and sent to the first and second programmable logic chips. Subsequently, when the first programmable logic chip detects the low-frequency detection clock signal, it can obtain a high-precision clock signal with a target frequency based on the high-precision clock chip. At this time, the target frequency of the high-precision clock signal is higher than the preset frequency. When it is verified that the clock signals currently acquired by the first and second programmable logic chips meet the preset state constraints, it can be determined that the stability of the communication clock state between the main backplane and the slave backplane can meet the clock synchronization requirements. At this time, the generated high-precision clock signal can be sent to the first and second programmable logic chips, so that the main backplane and the slave backplane can synchronously receive a high-precision clock signal with accurate signal frequency and stable state, ultimately realizing the clock synchronization processing between the test boards. In practice, the stability and accuracy of a signal can be determined by a relatively easy-to-generate low-frequency detection signal. After determining the signal status, the required high-precision clock signal is generated and configured and distributed, which can improve the efficiency and accuracy of clock synchronization of the chip tester in the system. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the system architecture of a chip tester clock in one embodiment;

[0049] Figure 2 This is a schematic diagram of the first process of a chip tester clock synchronization method in one embodiment;

[0050] Figure 3 This is a second flowchart illustrating a chip tester clock synchronization method in another embodiment;

[0051] Figure 4 This is a schematic diagram of the third process of a chip tester clock synchronization method in another embodiment;

[0052] Figure 5 This is a schematic diagram of the fourth process of a chip tester clock synchronization method in another embodiment;

[0053] Figure 6 This is a schematic diagram of the fifth step of a chip tester clock synchronization method in another embodiment;

[0054] Figure 7 This is a schematic diagram of the sixth process of a chip tester clock synchronization method in another embodiment;

[0055] Figure 8This is a technical schematic diagram of the system clock configuration in a chip tester clock synchronization method according to one embodiment;

[0056] Figure 9 This is a structural block diagram of a chip tester clock synchronization device in one embodiment;

[0057] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0059] In the chip testing process, to send digital signal waveforms to the pins of the chip under test (DUT) via the pattern module, different pattern modules within the same rack need to synchronously send synchronization signals to their respective DUTs. This requires the digital signals from the pattern modules to be frequency-synchronized. However, the frequency of the transmitted digital signals varies depending on the pin under test. To ensure synchronization of digital signal waveforms across all channels after a frequency change, the pattern module needs to detect the first clock edge after the frequency transition. Furthermore, to ensure that the pattern module can detect a clock edge, high-precision clocks across the backplane need to be synchronized.

[0060] In related technologies, in order to synchronize the clock signals of multiple digital chip testers, it is usually necessary to connect multiple test backplanes according to their master-slave mode, and to make the pattern module use the first edge of the input clock to trigger the start of the clock. That is, it is necessary to ensure that the first edge of the clock used to control synchronization in the pattern module must be fully synchronized.

[0061] However, current clock synchronization methods for digital chip testing machines have the following technical problems:

[0062] Different chip testing machines may have different proprietary clock chips, which makes it difficult for the pattern module to detect the first edge of the latest clock according to a unified standard during clock switching, resulting in difficulties in clock synchronization processing.

[0063] Based on this, the chip tester clock synchronization method provided in this application embodiment can be applied to, for example... Figure 1The chip testing machine shown includes a main backplane 101 and several slave backplanes 103. Both the main backplane 101 and the slave backplanes 103 are communicatively connected to multiple test boards 105. The main backplane 101 includes a high-precision clock chip 101-1 and a first programmable logic chip 101-2. The slave backplanes 103 include a second programmable logic chip 103-1.

[0064] In one embodiment, such as Figure 2 As shown, a chip tester clock synchronization method is provided, which is applied to... Figure 1 The following steps describe the main backplane of the chip testing machine:

[0065] Step 202: In response to the instruction to perform clock synchronization processing on the multiple test boards, a low-frequency detection clock signal of a preset frequency is sent to the first programmable logic chip and the second programmable logic chip based on the configuration of the high-precision clock chip.

[0066] The preset frequency refers to the set frequency of the low-frequency detection clock signal, which can be set by technicians according to actual testing needs and hardware performance. A programmable logic chip refers to a chip that can perform logical control and processing of input and output signals according to the program required by technicians.

[0067] For example, after the chip tester receives an instruction to perform clock synchronization processing on multiple test boards, when the reference clock of the second clock chip on the slave backplane is low, while the frequency of the first clock chip on the main backplane is high, it is difficult to use the reference clock to process a clock signal with a higher frequency than it. For example, when the reference clock of the slave backplane is 100MHz, and the frequency of the main backplane is 300MHz or higher. Therefore, before configuring the target high-precision clock, a low-frequency and fixed-frequency low-frequency detection clock signal needs to be configured first for synchronization processing. That is, the high-precision clock chip can be controlled to configure a low-frequency detection clock signal according to the parameters set by the preset frequency, and the low-frequency detection clock signal is sent to the first programmable logic chip and the second programmable logic chip.

[0068] Step 204: When the first programmable logic chip detects the low-frequency detection clock signal, it configures a high-precision clock signal with a target frequency based on the high-precision clock chip, wherein the target frequency is higher than the preset frequency.

[0069] The target frequency can refer to the set frequency of the high-precision clock signal, which is higher than the preset frequency of the low-frequency detection clock signal.

[0070] For example, when the first programmable logic chip detects a low-frequency detection clock signal, a high-precision clock signal of the target frequency can be configured based on a high-precision clock chip.

[0071] Step 206: When it is verified that the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip meet the preset state constraints, the high-precision clock signal is sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip to complete the clock synchronization of all the test boards.

[0072] Among them, state constraints can refer to constraints used to determine whether the signal performance, such as accuracy and stability, meets preset standards.

[0073] For example, the low-frequency detection clock signal sent to the first and second programmable logic chips in step 202 is actually intended to verify whether the first and second programmable logic chips can meet preset state constraints. When the state constraints are met, it can be determined that the parameters of the signals transmitted between the master and slave backplanes can meet the preset clock synchronization requirements. At this time, a high-precision clock signal generated by a high-precision clock chip can be sent to the first and second programmable logic chips. In this way, clock synchronization of all test boards can be achieved through a high-precision clock signal.

[0074] In the above-mentioned chip testing machine clock synchronization method, by reasonably deducing the technical features in the embodiments, the following beneficial effects can be achieved in solving the technical problems raised in the background art:

[0075] In the clock synchronization process of the chip testing machine, after receiving an instruction to synchronize the clocks of multiple test boards, a low-frequency detection clock signal with a preset frequency is first configured based on a high-precision clock chip and sent to the first and second programmable logic chips. Subsequently, when the first programmable logic chip detects the low-frequency detection clock signal, it can obtain a high-precision clock signal with a target frequency based on the high-precision clock chip. At this time, the target frequency of the high-precision clock signal is higher than the preset frequency. When it is verified that the clock signals currently acquired by the first and second programmable logic chips meet the preset state constraints, it can be determined that the stability of the communication clock state between the main backplane and the slave backplane can meet the clock synchronization requirements. At this time, the generated high-precision clock signal can be sent to the first and second programmable logic chips, so that the main backplane and the slave backplane can synchronously receive a high-precision clock signal with accurate signal frequency and stable state, ultimately realizing the clock synchronization process between the test boards. In practice, the stability and accuracy of a signal can be determined by a relatively easy-to-generate low-frequency detection signal. After determining the signal status, the required high-precision clock signal is generated and configured and distributed, which can improve the efficiency and accuracy of clock synchronization of the chip tester in the system.

[0076] In one embodiment, under the control of a high-precision clock chip, a high-precision clock signal is output to all slave backplanes. To ensure that all slave backplanes can start counting at the same time after receiving the high-precision clock signal, it can be done as follows: Figure 3 As shown, step 206 includes:

[0077] Step 302: Send a trigger signal to the second programmable logic chip based on the first programmable logic chip.

[0078] A trigger signal can refer to a signal emitted under specific conditions to trigger or initiate an action, operation, or event. Trigger signals can be electrical signals, digital signals, optical signals, etc., and their specific form depends on the application scenario and system design.

[0079] For example, after a high-precision clock signal is generated, a trigger signal can be generated through the main backplane and sent to other slave backplanes (FPGAs). At this time, the main backplane and the slave backplanes can synchronize their timing based on the trigger signal.

[0080] Step 304: Instruct the first programmable logic chip and the second programmable logic chip to perform synchronous timing based on the trigger signal.

[0081] For example, the main backplane can instruct the first programmable logic chip and the second programmable logic chip to perform synchronous timing based on the trigger signal.

[0082] In this embodiment, during the configuration of the synchronous clock signal, synchronous timing is performed by triggering a signal, which helps to verify the synchronization of the main backplane and the slave backplane through synchronous timing, thereby improving the stability of the test system.

[0083] In one embodiment, it can be as follows Figure 4 As shown, step 304 includes:

[0084] Step 402: When the timing of the first programmable logic chip reaches the first preset duration and the timing of the second programmable logic chip reaches the second preset duration, it is determined that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

[0085] The start flag is used to indicate the beginning of a data frame. When data is transmitted through a communication line, the receiving end needs to know when to start receiving data frames; this is the function of the start flag. The start flag is typically a specific sequence of bits used to indicate the beginning of a data frame.

[0086] For example, when the timing of the first programmable logic chip reaches the first preset duration and the timing of the second programmable logic chip reaches the second preset duration, it is determined that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

[0087] In this embodiment, the synchronization state between the main backplane and the slave backplane is determined by the timing relationship between the first programmable logic chip and the second programmable logic chip, which helps to improve the accuracy of clock synchronization processing between the main backplane and the slave backplane.

[0088] In one embodiment, such as Figure 5 As shown, step 304 includes:

[0089] Step 502: Disable the enable channel between the test board and the main backplane and the slave backplane associated with the test board.

[0090] The enable channel, in particular, has wide applications in digital circuits and communication systems. It can be used for scenarios such as data selection, signal routing, and channel switching to achieve signal selection and distribution.

[0091] For example, in response to a command to perform clock synchronization processing on the test board, the enable channel between the test board and the upper-level backplane can be turned off, thereby preventing the incomplete clock signal from interfering with the detection of the initial edge signal.

[0092] In this embodiment, the process of turning off the enable channel before clock synchronization can prevent signals from entering the test board in advance, which would cause the start signal reading to be out of sync and help improve the stability of clock synchronization.

[0093] In one embodiment, it can be as follows Figure 6 As shown, step 206 is followed by:

[0094] Step 602: In response to the detected main backplane and the slave backplane, set the start flag and start timing.

[0095] Step 604: When the second programmable logic chip reaches the second preset duration, it is determined that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip have been synchronized.

[0096] Step 606: Open the enable channel to send the high-precision clock signal to the corresponding target test board based on the target backplane.

[0097] In this embodiment, after determining that clock synchronization is completed between the main backplane and the slave backplane, the enable channel that was restricted in the preprocessing will be opened, thereby enabling the transmission of signals and instructions through the enable channel.

[0098] In one embodiment, it can be as follows Figure 7 As shown, the main backplane includes a first system clock chip, the slave backplane includes a second system clock chip, and before step 202, it further includes:

[0099] Step 702: Configure the initial clock of the corresponding backplane based on the first system clock chip and the second system clock chip, so that the main backplane and the slave backplane can complete the system clock configuration.

[0100] A clock chip typically contains one or more clock sources to generate clock signals. These clock sources can be crystal oscillators, external clock signals, PLLs (phase-locked loops), etc. When the chip powers on or resets, it uses one of these clock sources as the initial clock signal. The initial clock can refer to the parameters of the initial clock set during this clock synchronization process.

[0101] For example, the configuration principle of the system clock can be as follows: Figure 8 As shown.

[0102] In one embodiment, the trigger signal may be a synchronous start pulse signal generated by the first programmable logic chip at the rising edge of the low-frequency detection clock signal with the system clock as a reference clock.

[0103] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0104] Based on the same inventive concept, this application also provides a chip tester clock synchronization device for implementing the aforementioned chip tester clock synchronization method. The solution provided by this device is similar to the implementation described in the above method. Therefore, the specific limitations of one or more embodiments of the chip tester clock synchronization device provided below can be found in the limitations of the chip tester clock synchronization method described above, and will not be repeated here.

[0105] In one embodiment, such as Figure 9 As shown, a chip tester clock synchronization device is provided. The chip tester includes a main backplane and several slave backplanes. The main backplane and the slave backplanes are communicatively connected to multiple test boards. The main backplane includes a high-precision clock chip and a first programmable logic chip, and the slave backplanes include a second programmable logic chip. The device includes:

[0106] The low-frequency detection clock module is used to respond to the instruction to perform clock synchronization processing on multiple test boards, and to send a low-frequency detection clock signal of a preset frequency to the first programmable logic chip and the second programmable logic chip based on the configuration of the high-precision clock chip.

[0107] A high-precision clock configuration module is used to configure a high-precision clock signal with a target frequency based on the high-precision clock chip when the first programmable logic chip detects the low-frequency detection clock signal, wherein the target frequency is higher than the preset frequency.

[0108] The clock synchronization module is used to send the high-precision clock signal to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip when verifying that the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip meet the preset state constraints, so as to complete the clock synchronization of all the test boards.

[0109] In one embodiment, the high-precision clock configuration module further includes:

[0110] A trigger signal generation module is used to send a trigger signal to the second programmable logic chip based on the first programmable logic chip.

[0111] A synchronous timing module is used to instruct the first programmable logic chip and the second programmable logic chip to perform synchronous timing based on the trigger signal.

[0112] In one embodiment, the synchronization timing module includes:

[0113] The synchronization verification module is used to determine that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent when the timing of the first programmable logic chip reaches a first preset duration and the timing of the second programmable logic chip reaches a second preset duration. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

[0114] In one embodiment, prior to the synchronization timing module, the system further includes:

[0115] An enable channel limiting module is used to disable the enable channel between the test board and the main backplane and the slave backplane associated with the test board.

[0116] In one embodiment, after the low-frequency detection clock module, the system further includes:

[0117] A timing start module is used to set the start flag and start timing in response to the detection of the main backplane and the slave backplane;

[0118] The synchronization completion module is used to determine that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip are synchronized when the second programmable logic chip reaches the second preset time.

[0119] An enable channel opening module is used to open the enable channel to send the high-precision clock signal to the corresponding target test board based on the target backplane.

[0120] In one embodiment, the main backplane includes a first system clock chip, the slave backplane includes a second system clock chip, and before the low-frequency detection clock module, it further includes:

[0121] The system clock configuration module is used to configure the initial clock of the corresponding backplane based on the first system clock chip and the second system clock chip, so as to complete the system clock configuration of the main backplane and the slave backplane.

[0122] In one embodiment, the trigger signal is a synchronization start pulse signal generated by the first programmable logic chip at the rising edge of the low-frequency detection clock signal, using the system clock as a reference clock.

[0123] The various modules in the aforementioned chip testing machine clock synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0124] In one embodiment, a computer device is provided, which may include a chip tester clock synchronization system as described in a chip tester clock synchronization device. The computer device may also be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a chip testing machine clock synchronization method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0125] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0126] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0127] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0128] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0129] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with relevant laws, regulations and standards.

[0130] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for synchronizing a chip testing machine clock, characterized in that, The chip testing machine includes a main backplane and several slave backplanes. Both the main backplane and the slave backplanes are communicatively connected to multiple test boards. The main backplane includes a high-precision clock chip and a first programmable logic chip, and the slave backplanes include a second programmable logic chip. The method includes: In response to the instruction to perform clock synchronization processing on the multiple test boards, a low-frequency detection clock signal of a preset frequency is configured and sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip configuration. When the first programmable logic chip detects the low-frequency detection clock signal, it configures a high-precision clock signal with a target frequency based on the high-precision clock chip, wherein the target frequency is higher than the preset frequency. When the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are verified to meet the preset state constraints, the high-precision clock signal is sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip to complete the clock synchronization of all the test boards.

2. The method according to claim 1, characterized in that, When the first programmable logic chip detects the low-frequency detection clock signal, the method further includes: The first programmable logic chip sends a trigger signal to the second programmable logic chip; The trigger signal instructs the first programmable logic chip and the second programmable logic chip to perform synchronous timing.

3. The method according to claim 2, characterized in that, The step of instructing the first programmable logic chip and the second programmable logic chip to perform synchronized timing based on the trigger signal includes: When the timing of the first programmable logic chip reaches a first preset duration and the timing of the second programmable logic chip reaches a second preset duration, it is determined that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent. The first preset duration is the sum of the second preset duration and the period of the low-frequency detection clock signal.

4. The method according to claim 3, characterized in that, Before instructing the first programmable logic chip and the second programmable logic chip to synchronize timing based on the trigger signal, the method further includes: Disable the enable channel between the test board and the main backplane and the slave backplane associated with the test board.

5. The method according to claim 4, characterized in that, After configuring and sending a low-frequency detection clock signal of a preset frequency to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip, the method further includes: In response to the detection of the main backplane and the slave backplane, the start flag is set and the timing is started; When the second programmable logic chip reaches the second preset duration, it is determined that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip have been synchronized. Enable the channel to send the high-precision clock signal to the target test board relative to the target backplane.

6. The method according to claim 2, characterized in that, The main backplane includes a first system clock chip, the slave backplane includes a second system clock chip, and prior to the instruction to perform clock synchronization processing on the plurality of test boards, the method further includes: Configure the initial clock of the corresponding backplane based on the first system clock chip and the second system clock chip, so as to complete the system clock configuration of the main backplane and the slave backplane.

7. The method according to claim 6, characterized in that, The trigger signal is a synchronous start pulse signal generated by the first programmable logic chip at the rising edge of the low-frequency detection clock signal, using the system clock as a reference clock.

8. A clock synchronization device for a chip testing machine, characterized in that, The chip testing machine includes a main backplane and several slave backplanes. Each of the main backplane and slave backplanes is communicatively connected to multiple test boards. The main backplane includes a high-precision clock chip and a first programmable logic chip. The slave backplanes include a second programmable logic chip. The device includes: The low-frequency detection clock module is used to respond to the instruction to perform clock synchronization processing on multiple test boards, and to send a low-frequency detection clock signal of a preset frequency to the first programmable logic chip and the second programmable logic chip based on the configuration of the high-precision clock chip. A high-precision clock configuration module is used to configure a high-precision clock signal with a target frequency based on the high-precision clock chip when the first programmable logic chip detects the low-frequency detection clock signal, wherein the target frequency is higher than the preset frequency. The clock synchronization module is used to send the high-precision clock signal to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip when verifying that the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip meet the preset state constraints, so as to complete the clock synchronization of all the test boards.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that, The device includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the at least one processor implements a chip tester clock synchronization method as described in any one of claims 1-7 by executing the instructions stored in the memory.

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