A daisy chain structure and signal transmission method thereof

Abstract

The present invention discloses a daisy chain structure and a signal transmission method thereof, and belongs to the field of communication technology. A daisy chain structure and a signal transmission method thereof of the present invention sets multiple input interfaces for each chip in the daisy chain structure, and uses multiple input interfaces to simultaneously connect with multiple previous chips, so that each chip can receive data on multiple chips, and before transmitting downward, the chip judges all received data and distinguishes erroneous data, and while transmitting correct data downward, distinguishes erroneous data and the chip that transmits erroneous data and reports it to a host computer, so that the correct transmission of data can be ensured, and the erroneous chip can be reported in time, so that the staff can repair or replace the erroneous chip uniformly after a certain period of time, thereby reducing the number of maintenance times, and ensuring the long-term stable and correct operation of the signal transmission system.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more specifically, to a daisy chain structure and a signal transmission method thereof. Background Art

[0002] Daisy Chain is a method of transmitting signals along a bus, where devices on the signal transmission line of the daisy chain are connected in series, and signals are transmitted from one device to the next. The daisy chain connection method can assign priorities to devices according to their electrical status on the bus. In the daisy chain cascade circuit structure, the output of the previous device is coupled to the input of the subsequent device to provide information (such as data, address and command information) and control signals (such as enable signals) from the previous device to the subsequent device.

[0003] The daisy chain structure has fewer connections, which can reduce jumpers and automatically assign addresses. Compared with the traditional parallel structure, which has cumbersome connections and requires physical confirmation of addresses, it has many advantages. However, since the daisy chain is a series structure, all devices are connected in series downward in sequence, and its disadvantages are also obvious: once a chip (IC) in the series structure of the daisy chain has a problem, such as chip damage, cold soldering, etc., all chips in the chain after the damaged chip will receive wrong data, or even fail to receive data normally, resulting in a large number of chips working incorrectly or even not working. Summary of the invention

[0004] 1. Technical problem to be solved by the invention

[0005] In view of the problem that once a problem occurs in one device of the existing daisy chain connection, subsequent devices will receive error signals or fail to work, the present invention provides a daisy chain structure and a signal transmission method thereof to solve the problems mentioned in the background technology.

[0006] 2. Technical solution

[0007] In order to achieve the above object, the technical solution provided by the present invention is:

[0008] A daisy chain structure of the present invention comprises a plurality of chips, wherein the chips are connected in series in sequence, the chips comprise at least one data output port and m data input ports, the m data input ports are respectively connected to the preceding m chips, and m≥2.

[0009] Furthermore, the data input ports of m chips that are continuous or discontinuous and adjacent to the host computer are connected to the data output port of the host computer.

[0010] Furthermore, the data output port of each chip is connected to the data input ports of m consecutive or discontinuous chips following the chip.

[0011] A daisy chain signal transmission method of the present invention utilizes the above-mentioned daisy chain structure for signal transmission, and is characterized in that the host computer outputs a signal through Data OUT and transmits it along the chip connection sequence; the Nth chip in the chip receives m chip signals and compares the received signals. If the data are consistent, a group of data is selected to continue to be transmitted downward; if the data are inconsistent, the correct data is selected to be transmitted downward.

[0012] Furthermore, the m consecutive or discontinuous chips directly adjacent to the host computer obtain signals from the previous chip while also directly obtaining signals from the host computer.

[0013] Furthermore, when the host computer transmits data, a check bit is added to the data; after each chip receives the signal, the check bits of all the data are compared, and the data with a correct check bit is determined as correct data, and the data with an incorrect check bit is determined as incorrect data.

[0014] Furthermore, each chip performs resistance state identification and determination on each input pin on the chip. If the resistance state of any input pin is found to be high resistance, the signal received by the pin is defined as an invalid signal, and the signal received by another input pin is selected for processing.

[0015] Furthermore, the host computer is connected to each chip via a CLK interface to transmit a clock signal.

[0016] Furthermore, the method is run when the device is turned on, and the correct input port is recorded before running normally.

[0017] Furthermore, after each chip detects an error signal, it transmits an error report to a host computer.

[0018] 3. Beneficial effects

[0019] Compared with the existing known technologies, the technical solution provided by the present invention has the following significant effects:

[0020] In view of the fact that once a problem occurs in one of the devices in the existing daisy chain connection form, subsequent devices will receive error signals or fail to work. A daisy chain structure and a signal transmission method thereof of the present invention are provided, in which multiple input interfaces are set for each chip in the daisy chain structure, and multiple input interfaces are used to connect to multiple previous chips at the same time, so that each chip can receive data on multiple chips. Before transmitting downward, the chip judges all received data and distinguishes erroneous data. While transmitting correct data downward, the erroneous data and the chip that transmits the erroneous data are distinguished and reported to the host computer. This can not only ensure the correct transmission of data, but also report the erroneous chip in time, making it convenient for staff to uniformly repair or replace the erroneous chip after a certain period of time, thereby reducing the number of maintenance times and ensuring the long-term stable and correct operation of the signal transmission system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the daisy chain connection circuit structure of the present invention. DETAILED DESCRIPTION

[0022] In order to further understand the content of the present invention, the present invention is described in detail in conjunction with the accompanying drawings and embodiments.

[0023] Example

[0024] Combination Figure 1, a daisy chain structure of the present invention includes a host computer and several chips, and all the chips are connected in series in sequence. All chips include at least one output port and m input ports, and the m input ports are respectively connected to the previous m chips, and the m≥2. Specifically in this embodiment, the host computer includes a DataIN port and a DataOUT port, and each chip has the same structure, including a DataOUT port and two DataIN ports, namely a DataIN1 port and a DataIN2 port. When connecting, the DataOUT port of the host computer connects the DataIN1 port of the first chip and the DataIN2 port of the second chip. The DataIN2 port of the first chip is selected to be vacant or connected to the host for simulation (after connecting to the host, the delay of the IC can be simulated, and then virtual data can be sent to the DataIN2 port to make the chip function more complete); the DataOUT port is connected to the DataIN1 port of the second chip. Starting from the third chip, the DataIN1 port of the Nth chip is connected to the DataOUT port of the N-1th chip, the DataIN2 port of the Nth chip is connected to the DataOUT port of the N-2th chip, and the DataOUT port of the Nth chip is connected to the DataIN1 port of the N+1th chip and the DataIN2 port of the N+2th chip. This embodiment only describes the case where the chip has two DataIN ports. If there are multiple ports, the connection method is similar to this embodiment, that is, the m DataIN ports of each chip are respectively connected to the DataOUT ports of the m chips before the chip, and the DataOUT port of the chip is respectively connected to the DataIN ports of the m chips after the chip. The DataOUT port of the last chip can be connected to the DataIN port of the host computer, or it can be left vacant, so as to choose to report the error information to the host computer or not.

[0025] Considering that this embodiment may be used in micro LED driving, this embodiment introduces a structure similar to a single wire (single-wire communication), and other similar communications are also set up in the same way. If it is a two-wire communication similar to I2C, a CLK port is added, and a CLK port is added to the host computer and each chip. The host computer and all chips are connected together through the CLK port, and the rest is the same as single-wire communication. Since this embodiment is in a daisy chain form and the data is transmitted serially, the delay period of the DataOUT data of two adjacent chips can be inferred. This delay period can be agreed upon by the protocol or defined in the transmission parameters.

[0026] A daisy chain signal transmission method of the present invention utilizes the above-mentioned daisy chain structure for signal transmission, and the host computer outputs the signal through DataOUT and transmits it along the chip connection sequence; the Nth chip in the chip receives m chip signals at the same time, and compares the part of the data belonging to itself (the Nth chip) among the m chip signals, and ignores other signals (all signals will be compared in a few cases). If all the data are consistent, a group of data is selected to continue to be transmitted downward, and if all the data are inconsistent, the correct data is selected to be transmitted downward, and the position of the chip where the error occurs is reported to the host computer. This embodiment can transmit error reports by bidirectional data transmission or by connecting the DataOUT interface of the last chip back to the host computer.

[0027] In this embodiment, the m consecutive or discontinuous chips directly adjacent to the host computer simultaneously obtain signals from the previous chip and also directly obtain signals from the host computer.

[0028] This embodiment also performs high impedance detection on each entry of the chip. First, the high impedance state is defined (i.e., the resistance is set to be higher than a certain value), and then the impedance state of each input pin of the chip is identified and determined. If the impedance state of any input pin is found to be high impedance, the signal received by the pin is defined as an invalid signal, and the signal received by another input pin is selected for processing. One method for identifying a high impedance state is to set a pull-down resistor R. If it is a communication without a start instruction such as a single-line protocol, each bit of data can be defined as a high level start and a low level end. The duty cycle is set to 1 for data with a duty cycle > 50%, and 0 for data with a duty cycle < 50%. If no high level or rising edge is found at the beginning of the data, the data is considered to be wrong. On the contrary, the duty cycle is set to 0 for data with a duty cycle > 50%, and 1 for data with a duty cycle < 50%. If no low level or falling edge is found at the beginning of the data, the data is considered to be wrong.

[0029] 3. When the host computer transmits data, a check bit is added before the data. After each chip receives the signal, it compares the check bits of all the data, determines the correct data as the correct data, and the wrong data as the wrong data, and selects the correct data for transmission downward.

[0030] The daisy chain signal transmission method of this embodiment has two usage modes. One is to first run one or more sets of complex verification data on the daisy chain structure to determine whether the multiple DataIN ports on each chip are correct. After the correct port is determined, the system operation is started, and no further verification is required. The second is to determine in real time during the system operation which chip port has a problem, and promptly feedback to the host computer, and uniformly repair or replace after a period of time.

[0031] In this embodiment, each chip in the daisy chain structure is provided with multiple input interfaces, and multiple input interfaces are used to simultaneously connect with the previous multiple chips, so that each chip can receive data from multiple chips. Before transmitting downward, the chip judges the correctness of the received data, selects the data related to the chip itself for judgment, and distinguishes the erroneous data. While transmitting the correct data downward, the erroneous data and the chip that transmits the erroneous data are distinguished and reported to the host computer. This can not only ensure the correct transmission of data, but also report the erroneous chip in time, making it convenient for the staff to uniformly repair or replace the erroneous chip after a certain period of time, thereby reducing the number of maintenance times and ensuring the long-term stable and correct operation of the signal transmission system.

[0032] The present invention and its embodiments are described schematically above, and the description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired by it and designs a structural method and an embodiment similar to the technical solution without creativity without departing from the purpose of the invention, they shall all fall within the protection scope of the present invention.

Claims

1. A daisy chain signal transmission method, characterized in that: A daisy chain structure is used for signal transmission. The daisy chain structure includes a plurality of chips, which are connected in series in sequence. The chip includes at least one data output port and m data input ports, and the m data input ports are respectively connected to the preceding m chips, where m≥2; the data output port of each chip is connected to the data input ports of the consecutive or discontinuous m chips following the chip; the DataOUT port of the last chip is connected to the DataIN port of the host computer, and the data input ports of the consecutive or discontinuous m chips adjacent to the host computer are connected to the data output port of the host computer; The host computer outputs signals through Data OUT and transmits them in the chip connection sequence; the Nth chip in the chip receives signals from m chips and compares the received signals. If the data are consistent, a group of data is selected to be transmitted downward; if the data are inconsistent, the correct data is selected to be transmitted downward; after each chip detects an error signal, it transmits an error report to the host computer.

2. A daisy chain signal transmission method according to claim 1, characterized in that: The m consecutive or discontinuous chips directly adjacent to the host computer obtain signals from the previous chip and also directly obtain signals from the host computer.

3. A daisy chain signal transmission method according to claim 1 or 2, characterized in that: When the host computer transmits data, a check bit is added to the data; after each chip receives the signal, it compares the check bits of all the data, and determines the data with a correct check bit as correct data, and the data with an incorrect check bit as incorrect data.

4. A daisy chain signal transmission method according to claim 1 or 2, characterized in that: Each chip identifies and determines the resistance state of each input pin on the chip. If the resistance state of any input pin is found to be high resistance, the signal received by the pin is defined as an invalid signal, and the signal received by another input pin is selected for processing.

5. The daisy chain signal transmission method according to claim 1, characterized in that: The host computer is connected to each chip via a CLK interface to transmit a clock signal.

6. The daisy chain signal transmission method according to claim 3, characterized in that: When the device is turned on, run the method described above once and record the correct input port of each chip.

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