A TVS chip production process

Abstract

The present invention relates to a TVS chip production process, including: diffusion / immersion separation, primary phase, platform etching, time compensation, photoresist removal, grid etching, insulation oxidation, glass passivation, secondary phase, window opening, photoresist removal, sand blasting and cleaning after sand blasting, oxidation, nickel alloy calcination, nickel plating, spot testing, cutting and splitting, and cleaning. A TVS chip production process of the present invention performs performance testing on silicon wafers after the diffusion process, and ensures the yield rate after each subsequent process.

Description

Technical Field

[0001] The present invention relates to the technical field of diode production, and in particular to a TVS chip production process. Background Art

[0002] TVS diode is a special type of diode. TVS is the abbreviation of Transient Voltage Suppressor, also known as overvoltage suppression diode or breakdown diode. The main function of TVS diode is to protect other devices in the circuit from damage by overvoltage. When the circuit is subjected to overvoltage shock, TVS diode can respond quickly and provide a low impedance path to divert the overvoltage to the ground or other safe places, thereby limiting the amplitude of the overvoltage and protecting other devices from damage. The working principle of TVS diode is based on the breakdown effect, that is, when the voltage across the device exceeds the breakdown voltage value, the diode will break down, forming a low impedance path to divert the overvoltage.

[0003] At present, the conventional production process of TVS diodes is: material preparation, pretreatment, diffusion treatment, primary processing, etching treatment, secondary processing, and packaging treatment.

[0004] However, in the conventional production process, there are still the following deficiencies:

[0005] In the production process of diffusion treatment, multiple sand blasting and cleaning are required, and the silicon wafer is easily damaged, resulting in a decrease in electrical performance. After the subsequent production process, the damaged areas on the silicon wafer are all defective products. Summary of the invention

[0006] In order to solve the technical problems existing in the background technology, the present invention provides a TVS chip production process, which performs performance testing on silicon wafers after the diffusion process and ensures the yield rate after each subsequent processing step.

[0007] The technical solution adopted by the present invention is:

[0008] A TVS chip production process, comprising:

[0009] Diffusion, used to form a PN junction and increase the surface carrier concentration;

[0010] Immersion separation is used to separate the whole chip board that is glued together after phosphorus / boron diffusion;

[0011] The primary phase uses the negative photoresist property of the photoresist to leave a groove etching area after exposure and development;

[0012] Terrace etching, etching trenches to expose the PN junction to generate electrical properties;

[0013] Compensation time, based on the measurement results, deepen the PN interface depth and increase the breakdown voltage;

[0014] Remove the photoresist layer, remove the photoresist layer on the entire chip board;

[0015] Grid etching to remove the oxide layer in the area where trenching is required;

[0016] Insulation oxidation, using the oxide layer to isolate the PN junction from the outside air;

[0017] Glass passivation, PN junction insulation;

[0018] The secondary phase uses the negative photoresist property of the photoresist to leave a metallized area after exposure and development;

[0019] Open windows and remove glass and oxide layers from areas that need metallization;

[0020] Photoresist removal: removing the photoresist layer on the glass passivation area;

[0021] Sand blasting and post-sand blasting cleaning, sand blasting on the back of the chip to prevent staggering, sand blasting on both sides of the chip to atomize the chip surface to facilitate nickel plating;

[0022] Oxidation, using high temperatures to form silicon dioxide on the chip surface;

[0023] Nickel alloy calcination, using an alloying furnace to bond the metal to silicon;

[0024] Nickel plating: plating metal nickel on the electrode to facilitate welding;

[0025] Point testing, using contacts to test performance;

[0026] Cutting and splitting, after the spot test is qualified, the whole chip board will be cut;

[0027] Cleaning: Clean the cut single chips.

[0028] Furthermore, the silicon wafer after the diffusion process is subjected to performance tests, including:

[0029] A. Contacts electrically connected to the silicon wafer, the contacts are arranged in a rectangular array, and a plane rectangular coordinate system is constructed. The coordinates of the contacts in the plane rectangular coordinate system are (X n , Y n );

[0030] B. The silicon circle area M placed in the contact matrix is:

[0031] ,

[0032] in:

[0033] R is the radius of the silicon circle, the coordinates of the silicon circle area M in the plane rectangular coordinate system are (x, y), and the coordinates of the center of the silicon circle in the plane rectangular coordinate system are (a, b);

[0034] C. The electrical contact area N of the contact structure is:

[0035] ,

[0036] in:

[0037] r is the contact surface radius of the contact, the coordinates of the electrical contact area N in the plane rectangular coordinate system are (x0, y0), and the electrical contact area N is separated from and inscribed in the silicon circle area M;

[0038] D. The contact provides test power and obtains test data Z n , and construct a spatial rectangular coordinate system, and calculate the distribution probability based on the test data:

[0039] ,

[0040] in:

[0041] K is the coordinate dimension,

[0042] Σ is the covariance matrix of the coordinate points,

[0043] |Σ| is the value of the covariance matrix of the coordinate point,

[0044] Σ （-1） is the inverse matrix of Σ,

[0045] T is the matrix transpose,

[0046] μ is the mean vector of coordinate points;

[0047] E、f(Z n ) is discrete data, which is used to judge the discrete performance of the silicon wafer after the diffusion process;

[0048] F、f(Z n ) is calculated as continuous data, which is used to judge the overall performance of the silicon wafer after the diffusion process.

[0049] Furthermore, a pair of contacts are arranged in the up-down direction, the upper contact is electrically connected to the upper end surface of the silicon circle, and the lower contact is electrically connected to the lower end surface of the silicon circle;

[0050] The plane rectangular coordinate system is located at the upper end surface or the lower end surface of the silicon circle;

[0051] Based on the coordinates (a, b) of the center of the silicon circle in the plane rectangular coordinate system and the radius R of the silicon circle, the silicon circle area M is located in the first quadrant of the plane rectangular coordinate system.

[0052] Furthermore, the test data Z n The expression is:

[0053] ,

[0054] The expression of the coordinate point mean vector μ is:

[0055] .

[0056] Furthermore, a positive test voltage is provided to the upper and lower contacts electrically connected to the upper and lower end surfaces of the silicon wafer, and the voltage drop data A x and contact coordinates (X n , Y n ), we can know the voltage drop matrix A at the contact point n for:

[0057] ,

[0058] It can be seen that the voltage drop matrix A at the contact point n The distribution probability is:

[0059] .

[0060] Furthermore, the voltage drop matrix A at the contact point n In the spatial rectangular coordinate system, the coordinate dimension K=3.

[0061] Furthermore, the voltage drop matrix A at the contact point n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for:

[0062] ,

[0063] Among them, Y0 is in the range of M∩N;

[0064] Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ, according to foXZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (A n ) Continuous data of curvature, which determines the overall performance of the silicon wafer after the diffusion process;

[0065] Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for:

[0066] ,

[0067] Among them, X0 is in the range of M∩N;

[0068] Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ, according to foYZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (A n ) curvature, which is used to determine the overall performance of the silicon wafer after the diffusion process.

[0069] Furthermore, a reverse test voltage is provided to the upper and lower contacts electrically connected to the upper and lower end surfaces of the silicon wafer, and the breakdown current data B x and contact coordinates (X n , Y n ), we can know the voltage drop matrix B at the contact point n for:

[0070] ,

[0071] It can be seen that the voltage drop matrix B at the contact point n The distribution probability is:

[0072] .

[0073] Furthermore, the voltage drop matrix B at the contact point n In the spatial rectangular coordinate system, the coordinate dimension K=3.

[0074] Furthermore, the voltage drop matrix B at the contact point n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for:

[0075] ,

[0076] Among them, Y0 is in the range of M∩N;

[0077] Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ, according to foXZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (B n ) Continuous data of curvature, which determines the overall performance of the silicon wafer after the diffusion process;

[0078] Voltage drop matrix at contact point B n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for:

[0079] ,

[0080] Among them, X0 is in the range of M∩N;

[0081] Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ, according to foYZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (B n ) curvature, which is used to determine the overall performance of the silicon wafer after the diffusion process.

[0082] The advantages of a TVS chip production process of the present invention are:

[0083] 1. Ensure that the contact is within the silicon circle by constructing the silicon circle area M and the electrical contact area N of the contact;

[0084] 2. Through the pressure drop data A x , Breakdown current data B x , and test them respectively;

[0085] 3. Ensure the integrity of the data structure through multi-dimensional data. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] In order to more clearly illustrate the specific implementation of the present invention, the drawings required in the specific implementation are briefly introduced below. The drawings in the following description are implementations of the present invention.

[0087] Figure 1 The present invention provides an example of a TVS chip production process, providing a schematic diagram of the first quadrant of a plane rectangular coordinate system of a silicon circle area M and an electrical contact area N of a contact;

[0088] Figure 2 The present invention provides a test data schematic diagram of a spatial rectangular coordinate system in a TVS chip production process;

[0089] Figure 3 The present invention provides a schematic diagram of plane rectangular coordinate system data based on spatial rectangular coordinate system test data in a TVS chip production process. Figure 1 ;

[0090] Figure 4 The present invention provides a schematic diagram of plane rectangular coordinate system data based on spatial rectangular coordinate system test data in a TVS chip production process. Figure 2 . DETAILED DESCRIPTION

[0091] In order to more clearly and specifically explain the specific implementation purpose and implementation mode of the present invention, the technical solution of the present invention will be fully described below. The described embodiments are part of the embodiments of the present invention, but not all of them. Without making creative work, all other embodiments based on the embodiments described in the present invention belong to the protection scope of the present invention.

[0092] The present invention provides a TVS chip production process, comprising:

[0093] Diffusion is used to form a PN junction and increase the surface carrier concentration. After the diffusion process, the silicon wafer is subjected to performance testing, including:

[0094] A. Contacts electrically connected to the silicon circle, the contacts are arranged in a rectangular array, and a plane rectangular coordinate system is constructed, such as Figure 1 As shown, the coordinates of the contact in the plane rectangular coordinate system are (X n , Y n ), a pair of contacts are arranged in the up and down direction, the upper contact is electrically connected to the upper end surface of the silicon circle, and the lower contact is electrically connected to the lower end surface of the silicon circle; the plane rectangular coordinate system is located at the upper end surface or the lower end surface of the silicon circle.

[0095] B. The silicon circle area M placed in the contact matrix is:

[0096] ,

[0097] like Figure 1 As shown, where:

[0098] R is the radius of the silicon circle, the coordinates of the silicon circle area M in the plane rectangular coordinate system are (x, y), and the coordinates of the center of the silicon circle in the plane rectangular coordinate system are (a, b);

[0099] Based on the coordinates (a, b) of the center of the silicon circle in the plane rectangular coordinate system and the radius R of the silicon circle, the silicon circle area M is located in the first quadrant of the plane rectangular coordinate system.

[0100] C. The electrical contact area N of the contact structure is:

[0101] ,

[0102] like Figure 1 As shown, where:

[0103] r is the contact surface radius of the contact, the coordinates of the electrical contact area N in the plane rectangular coordinate system are (x0, y0), and the electrical contact area N is separated and inscribed with the silicon circle area M.

[0104] D. The contact provides test power and obtains test data Z n , and construct a spatial rectangular coordinate system, and calculate the distribution probability based on the test data:

[0105] ,

[0106] in:

[0107] K is the coordinate dimension,

[0108] Σ is the covariance matrix of the coordinate points,

[0109] |Σ| is the value of the covariance matrix of the coordinate point,

[0110] Σ （-1） is the inverse matrix of Σ,

[0111] T is the matrix transpose,

[0112] μ is the mean vector of coordinate points;

[0113] Z n is the test data, Z n The expression is:

[0114] ,

[0115] in:

[0116] The expression of the coordinate point mean vector μ is:

[0117] .

[0118] E、f(Z n ) is a discrete data, which is used to judge the discrete performance of the silicon wafer after the diffusion process, where:

[0119] ①, provide a positive test voltage to the upper and lower contacts electrically connected to the upper and lower ends of the silicon circle, and the voltage drop data A x and contact coordinates (X n , Y n ), we can know the voltage drop matrix A at the contact point n for:

[0120] ,

[0121] It can be seen that the voltage drop matrix A at the contact point n The distribution probability is:

[0122] ;

[0123] Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, Figure 2 As shown, the coordinate dimension K=3.

[0124] Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for:

[0125] ,

[0126] Among them, Y0 is in the range of M∩N;

[0127] Coordinate dimension K = 2, such as Figure 3 As shown, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ. According to foXZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (A n ) Continuous data of curvature, which determines the overall performance of the silicon wafer after the diffusion process;

[0128] Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for:

[0129] ,

[0130] Among them, X0 is in the range of M∩N;

[0131] Coordinate dimension K = 2, such as Figure 4 As shown, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ. According to foYZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (A n ) curvature, which is used to determine the overall performance of the silicon wafer after the diffusion process.

[0132] ② Provide reverse test voltage to the upper and lower contacts electrically connected to the upper and lower ends of the silicon circle, and the breakdown current data B x and contact coordinates (X n , Y n ), we can know the voltage drop matrix B at the contact point n for:

[0133] ,

[0134] It can be seen that the voltage drop matrix B at the contact point n The distribution probability is:

[0135] .

[0136] Voltage drop matrix at contact point B n In the rectangular coordinate system of space, Figure 2 As shown, the coordinate dimension K=3.

[0137] Voltage drop matrix at contact point B n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for:

[0138] ,

[0139] Among them, Y0 is in the range of M∩N;

[0140] Coordinate dimension K = 2, such as Figure 3 As shown, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ. According to foXZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (B n ) Continuous data of curvature, which determines the overall performance of the silicon wafer after the diffusion process;

[0141] Voltage drop matrix at contact point B n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for:

[0142] ,

[0143] Among them, X0 is in the range of M∩N;

[0144] Coordinate dimension K = 2, such as Figure 4 As shown, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ. According to foYZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (B n ) curvature, which is used to determine the overall performance of the silicon wafer after the diffusion process.

[0145] F、f(Z n ) is calculated as continuous data, which is used to judge the overall performance of the silicon wafer after the diffusion process.

[0146] G. After the above overall performance judgment, the silicon elements with unqualified overall performance are returned for diffusion and diffused again.

[0147] Immersion separation is used to separate the whole chip board that is stacked together after phosphorus / boron diffusion; the immersion separation includes:

[0148] The chip is soaked in acid. The whole chip is moved from the silicon carbide boat to a special tank for soaking and separation. The special tank for soaking and separation is placed in an acid soaking tank, which is filled with hydrofluoric acid. The hydrofluoric acid is replaced every 3 days, and the phosphorus-attached chip and the boron-attached chip are respectively in separate special acid soaking tanks. The acid-resistant tank cover is sealed on the special tank for soaking and separation, and the soaking is carried out for 4 hours.

[0149] Chip separation, fill the pure water tank in the chemical tank with pure water and keep it flowing; open the acid-resistant tank cover and place the acid tank in the pure water tank to flush the acid, and the flushing time should be at least 5 minutes; put the separated chip whole board into a 25pcs Teflon basket, install a handle on the basket, and keep flushing for at least 5 minutes; take the flushing basket, soak it in isopropyl alcohol for 3 seconds, replace the isopropyl alcohol once a week, remove the handle, and put the basket in the oven to bake until completely dry.

[0150] The primary phase utilizes the negative photoresist property of the photoresist to leave a groove etching area after exposure and development; the primary phase includes:

[0151] Before applying the photoresist layer, place the rotating head on the rotating axis and fix it securely, confirm the phosphorus / boron surface of the entire unidirectional chip board, and collect it with the phosphorus side facing up.

[0152] Photoresist coating: apply the photoresist material to the center of the whole chip board, start the driving motor of the rotating head, the driving motor speed is 2000 rpm, and the rotation time is 10 seconds; after the driving motor stops, remove the whole chip board and place it on the chip placement rack to dry in the shade; arrange the whole chip board into a Teflon basket with a specification of 40 pcs, send it to a high-temperature oven for soft baking at 110°C for 10 minutes; take out the Teflon basket and place it on the workbench to cool down for 5 minutes; turn the whole chip board over, apply the photoresist material to the center of the second side of the whole chip board, start the driving motor of the rotating head, the driving motor speed is 2000 rpm, and the rotation time is 10 seconds; after the driving motor stops, remove the whole chip board and place it on the chip placement rack to dry in the shade, arrange the whole chip board into a Teflon basket with a specification of 40 pcs, send it to a high-temperature oven for hard baking at 110°C for 50 minutes; take out the Teflon basket and place it on the workbench to cool down for 5 minutes. For the cases where the coated part is uniform, uncoated, or the surface is uneven due to foreign matter, the photoresist layer material is removed by xylene, and the photoresist layer is re-coated. After completion, the suction cup head and the glue spinning pot are immersed in xylene to remove the photoresist layer material.

[0153] Exposure, turn on the light source of the exposure machine; select the masks in sequence according to the process flow, and stack them and fix them on the fixed seat of the double-sided exposure machine; check the alignment of the multi-layer masks, set the exposure time, place the entire chip board at the mask marked position, and start exposure after determining the alignment position; after the exposure is completed, clamp the entire chip board and arrange it in a basket with a specification of 40pcs.

[0154] Development, according to the process flow, place the basket in the chemical tank in turn, and immerse it in the developer and shake it for 1 minute; put the basket in the fixer and let it stand for 30 seconds; after fixing, place the basket in the tray for 30 seconds, and then send it into the oven for baking at 110℃ for 10 minutes; after baking, take it out for random inspection, check the left, middle and right line widths of the chip: line widths greater than 5.5 mil are qualified, less than 5.5 mil or asymmetric line widths are unqualified, and record the line width; after the random inspection is correct, carry out the final baking at 130℃ for 45 minutes; after the final baking is completed, take out the basket and cool it for 10 minutes.

[0155] Terrace etching, etching a groove to expose the PN junction to generate electrical properties; the terrace etching includes:

[0156] Pour the mixed acid into the mixed acid tank; turn on the power and lighting of the mixed acid tank through the control panel, and turn on the refrigeration and circulation to 5℃ and the target depth. Put the whole chip basket to be etched into the mixed acid tank, and start automatic etching through the control panel. The mixed acid is replaced every 650 pieces of etching; after completing the automatic etching, place the basket in the pure water tank to rinse.

[0157] Measuring the groove depth is used to perform random inspections on the groove depth of the chip board after automatic etching, including:

[0158] Spray isopropyl alcohol on the whole chip board after flushing, use dust-free paper to gently press and absorb the moisture of the whole chip board, and then place it on the microscope stage; by adjusting the focal length of the microscope, the groove bottom is clearly displayed as the benchmark, and the groove bottom scale value is measured as A. By adjusting the focal length of the microscope, the groove surface is clearly displayed as the benchmark, and the groove surface scale value is measured as B. The groove depth value = BA.

[0159] When the trench depth value does not reach the target depth, the platform etching step is repeated.

[0160] The compensation time is to deepen the PN interface depth and increase the breakdown voltage according to the measurement results; the compensation time includes:

[0161] Chip preparation: open the diffusion furnace, place the silicon carbide boat on the quartz tray and sprinkle aluminum powder on it, place a baffle at the front end of the quartz boat; place the entire chip board on the silicon carbide boat and record the discharge sequence sheet.

[0162] When the chip enters the furnace, the silicon carbide boat with the whole chip plate is moved to the furnace mouth of the diffusion furnace by using a quartz tray, and the silicon carbide boat is pushed into the tube mouth of the diffusion furnace by using a short quartz push rod; the silicon carbide boat is pushed to the marked position by using a long quartz push rod, and the replenishment time is set according to the process flow to start the process.

[0163] After the chip is taken out of the furnace and the temperature of the diffusion high-temperature furnace drops to 600°C, a long quartz pull rod is used to pull the silicon carbide boat in the diffusion furnace out to the furnace mouth; the quartz tray is taken out, and the silicon carbide boat is lifted out using a short pull rod and placed on a heat-resistant plate on the workbench for cooling.

[0164] Removing the photoresist layer A, removing the photoresist layer on the entire chip board; the photoresist layer removal includes:

[0165] The mixed acid is prepared by mixing the photoresist removal mixed acid with sulfuric acid / nitric acid = 9 / 1 and heating it to 65°C.

[0166] To remove the photoresist layer on the chip board, drain the chip basket and soak it in nitric acid for 5 seconds; slowly place the chip basket in hot mixed acid until the photoresist is completely removed; drain the chip basket and soak it in nitric acid for 5 seconds; move the chip basket to the hot water overflow tank and rinse it for at least 1 minute. The mixed acid for removing photoresist is replaced once a day, and the nitric acid is replaced once a week.

[0167] Repeat the steps of removing the photoresist layer until the photoresist layer on the entire board of the sampled chip is completely removed.

[0168] Grid line etching is to remove the oxide layer in the area where trenching is required; the grid line etching includes:

[0169] Place the basket in an isopropanol tank and soak for 3 seconds, take out the basket and place it in a buffered oxide etching solution tank for 4 minutes, take out the basket from the acid tank, drain it and place it in a pure water tank for at least 3 minutes; repeat the above steps, take out the basket and check the dehydration status of the chip board. If the dehydration is not complete, place it in a buffered oxide etching solution tank and soak it for 30 seconds. The buffered oxide etching solution and isopropanol should be replaced once a week.

[0170] Insulation oxidation, using an oxide layer to isolate the PN junction from the outside air; the insulation oxidation includes:

[0171] Place the chip, start the oxidation furnace, place the quartz boat on the quartz tray; start the heating pack to 90°C, and place the entire chip board on the oxidized quartz boat.

[0172] When the chip is put into the furnace, the quartz boat with the whole chip plate is moved to the mouth of the oxidation high-temperature furnace with a tray, and the quartz boat is pushed to the mouth of the oxidation furnace tube using a short quartz push rod; the quartz boat is pushed in sections to the marked line using a long push rod, and the quartz cover is sealed on the quartz boat, and the door of the oxidation high-temperature furnace is closed; the process parameters of the insulation oxidation are set according to the process flow, and the process is started.

[0173] After the chip is taken out of the furnace, the heating pack is turned off after the process is running, and the quartz cover is removed; the quartz boat is pulled to the furnace mouth in sections using a long quartz pull rod, and the quartz tray is taken out; the quartz boat is lifted out using a short pull rod, and placed on the workbench to cool, and the cooled chip plate is arranged in a Teflon basket.

[0174] Glass passivation, PN junction insulation; the glass passivation includes:

[0175] The binding liquid is prepared by injecting 1000ml of ethylene glycol butyl ether acetate into a 2000CC glass measuring cup, and then pouring 60g of ethyl cellulose into the measuring cup, and mixing evenly with a stirring rod; after mixing, pour it into a glass bottle, and roll it on a bottle roller until the liquid becomes light yellow and viscous, and there is no undissolved binding powder in the liquid.

[0176] The glass liquid is prefabricated, 800cc of the binding liquid is mixed with 1000g of glass powder, poured into a glass bottle, and then placed on a bottle roller for rolling.

[0177] Scrape the glass, place the chip board on the glass scraping work table suction cup, turn on the vacuum; pour a little glass liquid on the baffle, use a scraper to evenly scrape the glass liquid into the groove, the scraper and the chip are perpendicular to each other, and the scraper moves at a 45-degree angle to the groove. The scraper is replaced every 25 chips. The scraped chip board is placed flat on the platform to dry; after drying, the chip board is collected in a 40pcs basket and inverted for 15 minutes; the basket is upright, the glass side of the chip board is facing down, and it is placed in the oven for baking at 110℃ for 15 minutes. Repeat the above steps on the other side of the bidirectional material.

[0178] Glass sintering,

[0179] Start the glass sintering furnace, set the sintering temperature of the glass sintering according to the process flow, arrange the scraped chips on the quartz boat, and record the chip batch number; when the furnace temperature of the glass sintering furnace reaches 550℃, introduce 5NL nitrogen and 5NL oxygen into the glass sintering furnace; send the quartz boat into the glass sintering furnace, set the process parameters of the glass sintering according to the process flow, and start the process; after the sintering process is completed, wait for the furnace temperature to drop below 550℃, pull the quartz boat out of the furnace, cool it for 10 minutes after it is out of the furnace, and clamp the chip back into the basket.

[0180] The secondary phase utilizes the negative photoresist property of the photoresist to leave a metallized area after exposure and development; the secondary phase includes:

[0181] Scrape the photoresist layer, place the chip board with the surface to be scraped facing up on the chip suction cup, drop the photoresist material on the upper surface of the chip board, use a scraper to fill the photoresist material into the etched groove, keep the scraper moving at a 45-degree angle with the groove, scrape off the photoresist material on the back of the chip, and move the excess photoresist material to another chip board; remove the chip board and place it on the chip rack on the workbench to dry, arrange the chip board in a Teflon basket with a specification of 40 pcs, put the chip basket in a hot air oven for baking, and bake at 110℃ for 10 minutes. Repeat the above steps on the other side of the bidirectional material.

[0182] For one exposure, turn on the light source of the exposure machine, select the mask in sequence according to the process flow, and stack and fix it on the fixed seat of the single-sided exposure machine, set the exposure time, place the whole chip on the suction cup of the exposure machine, and adjust it so that the middle of the chip coincides with the alignment position of the light. Measure the illumination every day according to the light source standard of the degree detection table. After the middle of the chip and the mask are aligned, start the exposure. After the exposure is completed, clamp the whole chip board and arrange it in a basket with a specification of 40pcs. Repeat the above steps on the other side of the two-way material.

[0183] For the second layer of photoresist coating, place the rotating head on the rotating axis and fix it securely, apply the photoresist material to the center of the chip board, start the driving motor of the rotating head, the driving motor speed is 1000 rpm, and the rotation time is 13 seconds; after the driving motor stops, remove the chip board and place it on the chip placement stand to dry in the shade, arrange the chip board into a 40pcs Teflon basket; send it to a high-temperature oven for soft baking at 110℃ for 10 minutes; arrange the chip board into a 40pcs Teflon basket, send it to a high-temperature oven for hard baking at 110℃ for 60 minutes; take out the Teflon basket and put it on the workbench to cool down for 10 minutes. After the first side of the two-way material is soft-baked at 110℃ for 10 minutes, the second side is coated with a photoresist layer for the second time. In the case where the coating part is uniform, uncoated, or there are foreign objects and unevenness on the surface, remove the photoresist material with xylene and re-coat the photoresist layer. After completion, the suction cup head and the glue spinning pot are immersed in xylene to remove the photoresist layer material.

[0184] Secondary exposure: turn on the light source of the exposure machine, select the masks in sequence according to the process flow, and stack and fix them on the fixed seat of the single-sided exposure machine; set the exposure time, place the whole chip on the suction cup of the exposure machine and adjust it so that the middle of the chip coincides with the alignment position of the light; start the exposure after the middle of the chip and the mask are aligned, and after the exposure is completed, clamp the whole chip and arrange it in a basket with a specification of 40 pcs. Repeat the above steps on the other side of the bidirectional material.

[0185] Secondary development: according to the process flow, place the basket in the chemical tank in turn, and immerse it in the developer and shake it for 120 seconds; place the basket in the fixer and let it stand for 60 seconds; after fixing, place the basket in the tray for 30 seconds, and then put it into the oven for baking at 110℃ for 10 minutes; after baking, take it out for random inspection, and after the random inspection is correct, perform the final baking at 130℃ for 45 minutes; after the final baking is completed, take out the basket and cool it for 10 minutes. Check the chip and display the unclear areas for 30 seconds, then put it into the oven for baking at 100℃ for 10 minutes, and then inspect it again.

[0186] Opening the window, removing the glass and oxide layer in the area that needs metallization; the opening of the window includes:

[0187] Place the basket in an isopropanol tank and soak for 3 seconds, take out the basket and place it in a buffered oxide etching solution tank for 3 minutes, take out the basket from the acid tank, drain it and place it in a hot water overflow tank for mechanical flushing for at least 3 minutes; repeat the above steps, take out the basket and check the dehydration status of the chip board. If the dehydration is not complete, place it in a buffered oxide etching solution tank and soak it for 30 seconds. The buffered oxide etching solution should be replaced once a week.

[0188] Removing the photoresist layer B, removing the photoresist layer on the glass passivation area; the photoresist layer removal includes:

[0189] The mixed acid is prepared by mixing the photoresist removal mixed acid with sulfuric acid / nitric acid = 9 / 1 and heating it to 65°C.

[0190] To remove the photoresist layer on the glass passivation area, drain the chip basket and soak it in nitric acid for 5 seconds; slowly place the chip basket in hot mixed acid until the photoresist is completely removed; drain the chip basket and soak it in nitric acid for 5 seconds; move the chip basket to the hot water overflow tank and rinse it for at least 1 minute. The mixed acid for removing photoresist is replaced once a day, and the nitric acid is replaced once a week.

[0191] Repeat the step of removing the photoresist layer until the photoresist layer on the passivation area of ​​the sample glass is completely removed.

[0192] Sand blasting and cleaning after sand blasting, sand blasting on the back of the chip to prevent staggering, sand blasting on both sides of the chip to atomize the chip surface to facilitate nickel plating; the sand blasting and cleaning after sand blasting include:

[0193] To bake the sand, pour the sand into a baking pan and place it on the induction cooker. Turn the induction cooker to medium temperature and stir with a spoon.

[0194] Sandblasting, checking the sand position, setting the sandblasting pressure according to the process flow, and collecting the whole chip board after sandblasting.

[0195] Ultrasonic cleaning, place the whole chip board into a 25pcs Teflon basket and install a handle; place the basket in an isopropyl alcohol tank for 3 seconds, the isopropyl alcohol is replaced once a day, take out the basket and place it in an ultrasonic vibration tank for 10 minutes; repeat the above steps; take out the basket and place it in an acid soaking tank for 30 seconds, the acid soaking tank is filled with hydrofluoric acid, the hydrofluoric acid is replaced every 3 days, take out the basket and place it in the overflow tank for flushing for at least 3 minutes.

[0196] Oxidation, using high temperature to form silicon dioxide on the surface of the chip; the oxidation includes:

[0197] Place the chip, start the oxidation furnace, place the quartz boat on the quartz tray; start the heating pack to 90°C, and place the entire chip board on the oxidized quartz boat.

[0198] When the chip is put into the furnace, the quartz boat with the whole chip plate is moved to the mouth of the oxidation high-temperature furnace with a tray, and the quartz boat is pushed to the mouth of the oxidation furnace tube using a short quartz push rod; the quartz boat is pushed in sections to the marked line using a long push rod, and the quartz cover is sealed on the quartz boat, and the door of the oxidation high-temperature furnace is closed; the process parameters of the insulation oxidation are set according to the process flow, and the process is started.

[0199] The chip is taken out of the furnace. After the process is running, the heating pack is turned off. After the furnace temperature drops to 850℃, the quartz cover is removed. The quartz boat is pulled to the furnace mouth in sections using a long quartz segmented pull rod, and the quartz tray is taken out. The quartz boat is lifted out using a short pull rod, and placed on a workbench to cool. The cooled chip plate is arranged in a Teflon basket.

[0200] Nickel alloy calcination, using an alloy furnace to bond metal to silicon; the nickel alloy calcination includes:

[0201] No-load operation, open the nitrogen valve, increase the opening of the nitrogen valve until the furnace door is opened, start the mechanical pump and count for 2 minutes, close the nitrogen valve and count for 2 minutes when the time is up, open the nitrogen valve and count for 2 minutes when the time is up, enter the car and count for 2 minutes, open the hydrogen cylinder, open the hydrogen valve and count for 40 minutes, close the hydrogen valve and count for 2 minutes when the time is up, exit the car, start the fan and count for 2 minutes, close the nitrogen valve and count for 5 minutes when the time is up, and close the mechanical pump and fan when the time is up. No-load operation is performed once a day.

[0202] Place the chips, arrange the whole chip plate on the quartz boat, start the alloy furnace and vacuum pump, and set the parameters of the alloy process according to the process flow.

[0203] Put the chip into the furnace, open the nitrogen valve, increase the opening of the nitrogen valve until the furnace door opens, and use the long pull rod to push the quartz boat to the mark of the pull rod;

[0204] Start the mechanical pump and start counting for 2 minutes. When the time is up, close the nitrogen valve and start counting for 2 minutes. When the time is up, open the nitrogen valve and start counting for 2 minutes. When the time is up, get into the vehicle and start counting for 2 minutes. Open the hydrogen cylinder. When the time is up, open the hydrogen valve and start counting for 40 minutes.

[0205] After the chip is taken out of the furnace, close the hydrogen valve and start counting for 2 minutes. When the time is up, retreat the machine, start the fan and start counting for 2 minutes. When the time is up, turn off the mechanical pump until the furnace door is opened, and close the nitrogen valve; use the long pull rod to pull the quartz boat to the furnace mouth, use the short pull rod to pull the quartz boat out to the tray, start the mechanical pump and start counting for 5 minutes. When the time is up, turn off the mechanical pump and fan.

[0206] Nickel plating, plating metal nickel on the electrode to facilitate welding; the nickel plating includes:

[0207] Chemicals are prepared, the solution in the pickling tank is: hydrofluoric acid / pure water = 1 / 25; the gold chloride dilution in the gold chloride tank is = 2000cc pure water + 38cc hydrochloric acid + 20cc hydrofluoric acid + 10g gold chloride; the solution in the nickel liquid tank is = 2600g ammonium citrate + 2000g ammonium chloride + 1200g nickel chloride + 500g sodium hypophosphite + 30000cc pure water + 2000cc ammonia water. The water temperature of the nickel liquid tank is 90℃±2℃, and the pH value of the nickel liquid must be within 8.6±0.2.

[0208] Ni plating, place the whole chip in the chip basket, place the chip basket in the pickling tank and swing for 15 seconds; take out the chip basket and drain it and place it in the pure water overflow tank for flushing for at least 15 seconds; take out the chip basket and drain it and place it in the gold chloride tank for 1 second; take out the chip basket and place it in the nickel liquid tank for nickel plating and shake it regularly for 4 minutes, and the whole chip is below the surface during shaking; take out the chip basket and place it in the pure water tank for flushing for at least 1 minute; take out the chip basket and drain it and place it in the isopropanol tank for 30 seconds; take out the chip basket and drain it, place it in the oven for baking, bake it at 130℃ for 10 minutes; take out the chip basket and place it on the workbench for cooling. The configuration liquid in the pickling tank is replaced once a day; the nickel liquid in the nickel liquid tank is replaced every 800pcs.

[0209] Point testing, using contacts to test performance;

[0210] Cutting and splitting, after the spot test is qualified, the whole chip board will be cut;

[0211] Cleaning: Clean the cut single chips.

[0212] Based on the above, the embodiment of the TVS chip production process of the present invention is inspired. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A TVS chip production process, characterized in that: include: Diffusion, used to form a PN junction and increase the surface carrier concentration; Immersion separation is used to separate the whole chip board that is glued together after phosphorus / boron diffusion; The primary phase uses the negative photoresist property of the photoresist to leave a groove etching area after exposure and development; Terrace etching, etching trenches to expose the PN junction to generate electrical properties; Compensation time, according to the measurement results, deepen the PN junction depth and increase the breakdown voltage; Remove the photoresist layer, remove the photoresist layer on the entire chip board; Grid etching to remove the oxide layer in the area where trenching is required; Insulation oxidation, using the oxide layer to isolate the PN junction from the outside air; Glass passivation, PN junction insulation; The secondary phase uses the negative photoresist property of the photoresist to leave a metallized area after exposure and development; Open windows and remove glass and oxide layers from areas that need metallization; Photoresist removal: removing the photoresist layer on the glass passivation area; Sand blasting and post-sand blasting cleaning, sand blasting on the back of the chip to prevent staggering, sand blasting on both sides of the chip to atomize the chip surface to facilitate nickel plating; Oxidation, using high temperatures to form silicon dioxide on the chip surface; Nickel alloy calcination, using an alloying furnace to bond the metal to silicon; Nickel plating: plating metal nickel on the electrode to facilitate welding; Point testing, using contacts to test performance; Cutting and splitting, after the spot test is qualified, the whole chip board will be cut; Cleaning: cleaning the cut single chip; Among them, the performance test of the silicon wafer after the diffusion process includes: A. Contacts electrically connected to the silicon wafer, the contacts are arranged in a rectangular array, and a plane rectangular coordinate system is constructed. The coordinates of the contacts in the plane rectangular coordinate system are (X n , Y n ); B. The silicon circle area M placed in the contact matrix is: ， in: R is the radius of the silicon circle, the coordinates of the silicon circle area M in the plane rectangular coordinate system are (x, y), and the coordinates of the center of the silicon circle in the plane rectangular coordinate system are (a, b); A pair of contacts are arranged in the up-down direction, the upper contact is electrically connected to the upper end surface of the silicon circle, and the lower contact is electrically connected to the lower end surface of the silicon circle; The plane rectangular coordinate system is located at the upper end surface or the lower end surface of the silicon circle; According to the coordinates (a, b) of the center of the silicon circle in the plane rectangular coordinate system and the radius R of the silicon circle, the silicon circle area M is located in the first quadrant of the plane rectangular coordinate system; C. The electrical contact area N of the contact structure is: ， in: r is the contact surface radius of the contact, the coordinates of the electrical contact area N in the plane rectangular coordinate system are (x0, y0), and the electrical contact area N is separated from and inscribed in the silicon circle area M; D. Provide a positive test voltage to the upper and lower contacts electrically connected to the upper and lower ends of the silicon circle. x and contact coordinates (X n , Y n ), we can know the voltage drop matrix A at the contact point n for: ， It can be seen that the voltage drop matrix A at the contact point n The distribution probability is: ， in: K is the coordinate dimension, Σ is the covariance matrix of the coordinate points, |Σ| is the value of the covariance matrix of the coordinate point, Σ （-1） is the inverse matrix of Σ, T is the matrix transpose, μ is the mean vector of coordinate points; Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for: ， Among them, Y0 is in the range of M∩N; Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ, according to foXZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (A n ) Continuous data of curvature to determine the overall performance of the silicon wafer after the diffusion process; Voltage drop matrix at the contact point A n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix A at the contact point is n for: ， Among them, X0 is in the range of M∩N; Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ, according to foYZ (A n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (A n ) Continuous data of curvature to determine the overall performance of the silicon wafer after the diffusion process; or A reverse test voltage is provided to the upper and lower contacts electrically connected to the upper and lower ends of the silicon wafer, and the breakdown current data B x and contact coordinates (X n , Y n ), we can know the voltage drop matrix B at the contact point n for: ， It can be seen that the voltage drop matrix B at the contact point n The distribution probability is: ， in: K is the coordinate dimension, Σ is the covariance matrix of the coordinate points, |Σ| is the value of the covariance matrix of the coordinate point, Σ （-1） is the inverse matrix of Σ, T is the matrix transpose, μ is the mean vector of coordinate points; Voltage drop matrix at contact point B n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for: ， Among them, Y0 is in the range of M∩N; Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oXZ, according to foXZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foXZ (B n ) Continuous data of curvature to determine the overall performance of the silicon wafer after the diffusion process; Voltage drop matrix at contact point B n In the rectangular coordinate system of space, it can be seen that the voltage drop matrix B at the contact point is n for: ， Among them, X0 is in the range of M∩N; Coordinate dimension K = 2, the spatial rectangular coordinate system is simplified to the plane rectangular coordinate system oYZ, according to foYZ (B n ) to determine the discrete performance of the silicon wafer after the diffusion process; according to foYZ (B n ) curvature to determine the overall performance of the silicon wafer after the diffusion process.

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