Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a method for preparing the same, comprising a first N-type epitaxial layer located on one side of a substrate; a P-well region and a source N-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on the side of the gate away from the substrate; a source located on the side of the interlayer dielectric layer away from the substrate; and a drain located on the side of the substrate away from the source. The longitudinal arrangement of the N-type current extension region is relatively matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In recent years, silicon carbide (SiC) and gallium nitride (GaN), as third-generation semiconductor materials, have received widespread attention from the industry due to their excellent material properties. Compared with traditional silicon (Si) materials, they have more advantages in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. The power devices prepared, such as diodes and transistors, have better electrical properties and can be used for high power, high voltage, high frequency, and high temperature applications that silicon-based devices cannot meet. They are also one of the breakthrough paths beyond Moore's Law. Therefore, they are widely used in the field of new energy (photovoltaics, energy storage, charging piles, and electric vehicles, etc.), promoting the development of the "new energy revolution".

[0003] At the same time, the ultra-wide bandgap semiconductor materials with a bandgap width greater than that of SiC and GaN mainly include gallium oxide (Ga2O3), diamond (C) and aluminum nitride (AlN), which have superior optical and electrical properties. The larger bandgap width allows the device to be used in many extremely harsh environments: in the context of geothermal energy production and oil and gas extraction, higher drilling speeds and lower failure rates can be achieved, and in high temperature conditions, the operating temperature of aluminum plants, steel mills, and coal-fired and gas-fired power plants controlled by electronic sensors can be higher, thereby improving the energy efficiency of these industrial processes.

[0004] There are still several problems in the actual process manufacturing and application of wide bandgap semiconductor devices: (1) The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the groove corner, causing the gate dielectric layer to quickly break down under high drain voltage; the device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; 2) The gate capacitance of traditional devices is large and the device switching speed is slow; 3) The body diode turn-on voltage of traditional devices is as high as about 3V, so the loss of the body diode during reverse conduction is large, and the body diode is very likely to cause bipolar degradation when working for a long time, which leads to the degradation of the electrical performance of the wide bandgap semiconductor device.

[0005] Therefore, how to improve the reliability of wide bandgap semiconductor devices and improve their electrical performance is a technical problem that needs to be solved in this field. Summary of the invention

[0006] In view of this, this summary of the invention is provided to introduce the concepts in a brief form, which will be described in detail in the detailed description section below. This summary of the invention is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to be used to limit the scope of the technical solution claimed for protection.

[0007] The purpose of the present application is to provide a semiconductor device and a method for preparing the same, which can improve the reliability of wide bandgap semiconductor devices and improve electrical performance.

[0008] To achieve the above purpose, this application has the following technical solutions:

[0009] In a first aspect, an embodiment of the present application provides a semiconductor device, including:

[0010] substrate;

[0011] a first N-type epitaxial layer located on one side of the substrate;

[0012] a P-well region and a source N-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on a side of the first N-type epitaxial layer away from the substrate;

[0013] A gate trench penetrating the P-well region and the source N-type contact region;

[0014] An N-type channel in the P-well region and located on the sidewall of the gate trench; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel;

[0015] A gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the substrate; a source located on a side of the interlayer dielectric layer away from the substrate; and a drain located on a side of the substrate away from the source.

[0016] In a possible implementation manner, the N-type current extension region is in a cup shape.

[0017] In a possible implementation, the method further includes:

[0018] a first P-type buried layer and a second N-type epitaxial layer located between the P-well region and the first N-type epitaxial layer; the N-type current extension region penetrates the first P-type buried layer and the second N-type epitaxial layer;

[0019] The gate trench is located in the second N-type epitaxial layer; and a P-type shielding layer is located between the gate trench and the second N-type epitaxial layer.

[0020] In a possible implementation manner, the gate includes two gate structures separated by a preset distance.

[0021] In a possible implementation, the method further includes:

[0022] An N-type connection layer located in the P-type shielding layer; a Schottky metal located on a side of the N-type connection layer away from the substrate;

[0023] A P-type connecting layer penetrates the P-type shielding layer and the second N-type epitaxial layer and is connected to the first P-type buried layer.

[0024] In a possible implementation, the method further includes:

[0025] A source trench; a source dielectric layer and a source structure located in the source trench; the source P-type contact region is located around the outer wall of the source trench and wraps the source trench;

[0026] An ohmic contact metal is located between the source P-type contact region and the source.

[0027] In a possible implementation, the method further includes:

[0028] A third N-type semiconductor layer and a second P-type buried layer are sequentially stacked and located between the first P-type buried layer and the second N-type epitaxial layer.

[0029] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0030] providing a substrate;

[0031] epitaxially growing a first N-type epitaxial layer on one side of the substrate;

[0032] Forming a P-well region on a side of the first N-type epitaxial layer away from the substrate by ion implantation or epitaxial growth; forming a source N-type contact region on a side of the P-well region away from the substrate by ion implantation; forming a source P-type contact region on a side of the first N-type epitaxial layer away from the substrate by ion implantation;

[0033] Etching the P-well region and the source N-type contact region to form a gate trench;

[0034] An N-type current extension region is formed between the gate trench and the first N-type epitaxial layer by N-type ion implantation; an N-type channel is formed in the P-well region by lateral diffusion on the sidewall of the gate trench; and the N-type current extension region is connected to the N-type channel;

[0035] A gate dielectric layer and a gate are grown in the gate trench; an interlayer dielectric layer is grown on the side of the gate away from the substrate; a source electrode is grown on the side of the interlayer dielectric layer away from the substrate; and a drain electrode is grown on the side of the substrate away from the source electrode.

[0036] In a possible implementation manner, growing a gate dielectric layer and a gate in the gate trench includes:

[0037] growing an initial gate dielectric layer and an initial gate in the gate trench;

[0038] The initial gate dielectric layer and the initial gate are etched to form two gate dielectric structures and two gate structures separated by a preset distance.

[0039] In a possible implementation manner, the N-type current extension region is in a cup shape.

[0040] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0041] The embodiment of the present application provides a semiconductor device and a preparation method thereof, the device comprising: a substrate; a first N-type epitaxial layer located on one side of the substrate; a P-well region and a source N-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the substrate; a source located on a side of the interlayer dielectric layer away from the substrate; and a drain located on a side of the substrate away from the source. The present application sets an N-type current extension region between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel and further connected to the source N-type contact region. The longitudinal setting of the N-type current extension region is more matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0044] Figure 1 A schematic diagram of a semiconductor device provided by an embodiment of the present application is shown;

[0045] Figure 2 The semiconductor device provided by the embodiment of the present application is shown along Figure 1 Schematic diagram of the cross section of the middle section A;

[0046] Figure 3 The semiconductor device provided by the embodiment of the present application is shown along Figure 1 Schematic diagram of the cross section of the middle section B;

[0047] Figure 4 The embodiment of the present invention provides another semiconductor device. Figure 1 Schematic diagram of the cross section of the middle section A;

[0048] Figure 5 Another semiconductor device provided by the embodiment of the present application is shown along the Figure 1 Schematic diagram of the cross section of the middle section A;

[0049] Figure 6 A schematic diagram showing that the semiconductor device provided by the embodiment of the present application includes only one cross section;

[0050] Figure 7-Figure 21 A schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present application is shown;

[0051] Fig. 22 A top view of a device gate provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0052] It should be noted that the semiconductor device and the method for manufacturing the same provided by the present invention can be applied to the field of semiconductor technology. The above is only an example and does not limit the application field of the semiconductor device and the method for manufacturing the same provided by the present invention.

[0053] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0054] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0055] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0056] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0057] As described in the background technology, the applicant has found that in recent years, silicon carbide (SiC) and gallium nitride (GaN), as third-generation semiconductor materials, have received widespread attention from the industry due to their excellent material properties. Compared with traditional silicon (Si) materials, they have more advantages in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. The prepared power devices such as diodes and transistors have better electrical properties and can be applied to high power, high voltage, high frequency, high temperature and other application requirements that silicon-based devices cannot meet. It is also one of the breakthrough paths beyond Moore's Law. Therefore, they are widely used in the field of new energy (photovoltaic, energy storage, charging piles and electric vehicles, etc.), promoting the development of the "new energy revolution".

[0058] At the same time, the ultra-wide bandgap semiconductor materials with a bandgap width greater than that of SiC and GaN mainly include gallium oxide (Ga2O3), diamond (C) and aluminum nitride (AlN), which have superior optical and electrical properties. The larger bandgap width allows the device to be used in many extremely harsh environments: in the context of geothermal energy production and oil and gas extraction, higher drilling speeds and lower failure rates can be achieved, and in high temperature conditions, the operating temperature of aluminum plants, steel mills, and coal-fired and gas-fired power plants controlled by electronic sensors can be higher, thereby improving the energy efficiency of these industrial processes.

[0059] There are still several problems in the actual process manufacturing and application of wide bandgap semiconductor devices: (1) The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the groove corner, causing the gate dielectric layer to quickly break down under high drain voltage; the device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; 2) The gate capacitance of traditional devices is large and the device switching speed is slow; 3) The body diode turn-on voltage of traditional devices is as high as about 3V, so the loss of the body diode during reverse conduction is large, and the body diode is very likely to cause bipolar degradation when working for a long time, which leads to the degradation of the electrical performance of the wide bandgap semiconductor device.

[0060] Therefore, how to improve the reliability of wide bandgap semiconductor devices and improve their electrical performance is a technical problem that needs to be solved in this field.

[0061] In order to solve the above technical problems, an embodiment of the present application provides a semiconductor device, including: a substrate; a first N-type epitaxial layer located on one side of the substrate; a P-well region and a source N-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the substrate; a source located on a side of the interlayer dielectric layer away from the substrate; and a drain located on a side of the substrate away from the source. The present application sets an N-type current extension region between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel and further connected to the source N-type contact region. The longitudinal setting of the N-type current extension region is more matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

[0062] Exemplary Devices

[0063] See also Figure 1 FIG. 1 is a schematic diagram of a semiconductor device provided in an embodiment of the present application, see Figure 2 As shown, the semiconductor device provided by the embodiment of the present application is Figure 1 Schematic diagram of the cross section of the middle section A. Figure 3 As shown, the semiconductor device provided by the embodiment of the present application is Figure 1 Schematic diagram of the cross section of the middle section B.

[0064] The semiconductor device provided in the embodiment of the present application may include:

[0065] A substrate 1; a first N-type epitaxial layer 2 located on one side of the substrate 1; a P-well region 3 and a source N-type contact region 4 located on a side of the first N-type epitaxial layer 2 away from the substrate 1; and a source P-type contact region 5 located on a side of the first N-type epitaxial layer 2 away from the substrate 1.

[0066] A gate trench penetrating the P-well region 3 and the source N-type contact region 4; an N-type channel 6 located in the P-well region 3 on the sidewall of the gate trench; an N-type current extension region 7 located between the gate trench and the first N-type epitaxial layer 2; and the N-type current extension region 7 and the N-type channel 6 are connected.

[0067] A gate dielectric layer 8 and a gate 9 are located in the gate trench; an interlayer dielectric layer 10 is located on a side of the gate 9 away from the substrate 1; a source 11 is located on a side of the interlayer dielectric layer 10 away from the substrate 1; and a drain 12 is located on a side of the substrate 1 away from the source 11.

[0068] In the embodiment of the present application, the material of the substrate 1 may include SiC, GaN, Ga2O3, C or AlN.

[0069] Specifically, in power switch applications, Baliga's figure-of-merit (BFOM) is an indicator used to indicate the applicability of semiconductor materials in power electronics. It is expressed as: BFOM = εμE3, where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly proportional to the bandgap width E. g The sixth power is positively correlated.

[0070] Therefore, a larger bandgap width means that wide bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thereby achieving more excellent and ideal power electronics applications. Among wide bandgap semiconductor materials, Ga2O3 has a bandgap width of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a BFOM value of up to 3400, which is about 4 times that of GaN and 10 times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have more significant research significance and broader market application prospects.

[0071] The N-type current extension region 7 provided in the embodiment of the present application is connected to the N-type channel 6, and further connected to the source N-type contact region 4. The longitudinal setting of the N-type current extension region 7 is more matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

[0072] Optionally, the shape of the N-type current extension region can be set to be lamp-shaped to better match the current path and better conduct the device current.

[0073] Specifically, the wider width of the upper part of the N-type current expansion region 7 can reduce the on-resistance and improve the on-characteristics of the device, and the narrower width of the lower part can make the structure on both sides of the N-type current expansion region 7 wider, better protect the gate groove angle, and reduce the gate groove angle electric field.

[0074] In one possible implementation, see Figure 1 As shown, the device provided in the embodiment of the present application may also include:

[0075] The first P-type buried layer 13 and the second N-type epitaxial layer 14 are located between the P-well region 3 and the first N-type epitaxial layer 2 ; the N-type current extension region 7 penetrates the first P-type buried layer 13 and the second N-type epitaxial layer 14 .

[0076] Since the N-type current expansion region 7 runs through the first P-type buried layer 13, the wider width of the upper part of the N-type current expansion region 7 can reduce the on-resistance and improve the on-characteristics of the device, and the narrower width of the lower part can make the remaining first P-type buried layer 13 on both sides of the N-type current expansion region 7 wider, so as to better protect the gate groove angle and reduce the gate groove angle electric field.

[0077] The gate trench is located in the second N-type epitaxial layer 14 ; and the P-type shielding layer 15 is located between the gate trench and the second N-type epitaxial layer 14 .

[0078] Specifically, in the embodiment of the present application, the deep masking structure formed by the P-type masking layer 15 and the first P-type buried layer 13 can better protect the gate groove corner and improve the gate oxide reliability of the device.

[0079] In one possible implementation, the gate 9 includes two gate structures separated by a preset distance, namely a split gate. The split gate structure can reduce the capacitance of the gate 9 and improve the switching speed of the device. At the same time, the complete gate structure in section B can maintain the split gate in section A at the same potential through the connection of gate polysilicon.

[0080] In a possible implementation, the device provided in the embodiment of the present application may further include:

[0081] An N-type connection layer 16 located in the P-type shielding layer 15 ; a Schottky metal 17 located on a side of the N-type connection layer 16 away from the substrate 1 ; and a P-type connection layer 18 penetrating the P-type shielding layer 15 and the second N-type epitaxial layer 14 and connected to the first P-type buried layer 13 .

[0082] That is, in the embodiment of the present application, an N-type connection layer 16 is constructed in the middle of the split gate of section A, and a Schottky metal 17 is formed on the surface of the N-type connection layer 16, that is, a Schottky diode (SBD, Schottky barrier diode) is integrated here. The turn-on voltage of the Schottky diode is lower than that of the body diode, so the turn-on voltage and conduction loss of the device when working in the third quadrant can be reduced, thereby improving the overall characteristics of the device.

[0083] In one possible implementation, see Figure 4 As shown, another semiconductor device provided by the embodiment of the present application is provided along Figure 1 Schematic diagram of the cross section of section A.

[0084] The device provided in the embodiment of the present application may also include: a source trench; a source dielectric layer 19 and a source structure 20 located in the source trench; a source P-type contact region 5 located around the outer wall of the source trench, wrapping the source trench; and an ohmic contact metal 21 located between the source P-type contact region 5 and the source 11.

[0085] That is, in the embodiment of the present application, a source trench structure may also be used, and a single-level trench or a multi-level trench structure may be used, and the number of trench levels is N, where N ≥ 0; to provide a deeper ion implantation depth and improve the electrical performance of the device.

[0086] In one possible implementation, see Figure 5 As shown, another semiconductor device provided by the embodiment of the present application is provided along Figure 1 Schematic diagram of the cross section of section A.

[0087] The device provided in the embodiment of the present application may further include: a third N-type semiconductor layer 22 and a second P-type buried layer 23 stacked in sequence and located between the first P-type buried layer 13 and the second N-type epitaxial layer 14 .

[0088] That is, in the embodiment of the present application, after the first P-type buried layer 13 is epitaxially grown, the third N-type semiconductor layer 22 can be implanted between the first P-type buried layer 13 and the second N-type epitaxial layer 14, or the third N-type semiconductor layer 22 is formed by epitaxially growing to form a PNP structure in the middle. The multi-layer P+ buried layer has a better effect on electric field modulation, which can improve the breakdown characteristics of the device.

[0089] In one possible implementation, see Figure 6 As shown, the semiconductor device provided by the embodiment of the present application only includes a schematic diagram of a cross section. When the device has only one cross section and there is no N-type connection layer 16 and Schottky metal 17, the split gate can make the P-type shielding layer 15 better grounded to ensure the dynamic reliability of the device; at the same time, it can reduce the gate capacitance and improve the switching speed of the device.

[0090] The embodiment of the present application provides a semiconductor device, including: a substrate; a first N-type epitaxial layer located on one side of the substrate; a P-well region and a source N-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on the side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on the side of the gate away from the substrate; a source located on the side of the interlayer dielectric layer away from the substrate; and a drain located on the side of the substrate away from the source. The present application sets an N-type current extension region between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel and then connected to the source N-type contact region. The longitudinal setting of the N-type current extension region is relatively matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

[0091] Exemplary Methods

[0092] S101: providing a substrate.

[0093] S102: epitaxially growing a first N-type epitaxial layer on one side of the substrate.

[0094] S103: forming a P-well region on a side of the first N-type epitaxial layer away from the substrate by ion implantation or epitaxial growth; forming a source N-type contact region on a side of the P-well region away from the substrate by ion implantation; forming a source P-type contact region on a side of the first N-type epitaxial layer away from the substrate by ion implantation.

[0095] S104: etching the P-well region and the source N-type contact region to form a gate trench.

[0096] S105: forming an N-type current extension region between the gate trench and the first N-type epitaxial layer by N-type ion implantation; forming an N-type channel in the P-well region on the sidewall of the gate trench by lateral diffusion; and connecting the N-type current extension region and the N-type channel.

[0097] S106: growing a gate dielectric layer and a gate in the gate trench; growing an interlayer dielectric layer on a side of the gate away from the substrate; growing a source electrode on a side of the interlayer dielectric layer away from the substrate; and growing a drain electrode on a side of the substrate away from the source electrode.

[0098] In a possible implementation manner, growing a gate dielectric layer and a gate in the gate trench includes:

[0099] growing an initial gate dielectric layer and an initial gate in the gate trench;

[0100] The initial gate dielectric layer and the initial gate are etched to form two gate dielectric structures and two gate structures separated by a preset distance.

[0101] In a possible implementation manner, the N-type current extension region is in a cup shape.

[0102] See also Figure 7-Figure 21 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present application. Figure 7 , a first N-type epitaxial layer 2 may be epitaxially grown on the substrate 1. The first N-type epitaxial layer 2 may be made of materials such as SiC doped with N-type elements (such as P, etc.).

[0103] See also Figure 8 Then, a first P-type buried layer 13 is grown on the first N-type epitaxial layer 2. The material of the first P-type buried layer 13 can be SiC or other materials doped with P-type elements (such as B). Fig. 9 , and then grow a second N-type epitaxial layer 14 on the first P-type buried layer 13 .

[0104] See also Fig.10 , a P-well region 3 is formed by ion implantation, secondary epitaxy, growth of a P-type oxide, etc.; a source N-type contact region 4 is formed by ion implantation. Fig.11 , a source P-type contact region 5 is formed by ion implantation; see Fig.12 , dry etching is used to form a gate trench.

[0105] See also Fig.13 At the bottom of the gate trench, a P-type masking layer 15 is formed in the second N-type epitaxial layer 14 by P-type ion implantation; see Fig.14 , an N-type current channel 7 is formed by N-type ion implantation, and an N-type channel 6 and an N-type current extension region 7 are naturally formed by lateral diffusion effect. In the embodiment of the present application, the N-type current extension region 7 in the first P-type buried layer 13 serves as the N-type current channel 7.

[0106] During the ion implantation process of the N-type current channel 7, the energy and dosage of the ion implantation can be controlled to further control the width of the N-type current channel 7. The wider width of the upper part of the N-type current channel 7 can reduce the on-resistance and improve the on-characteristics of the device. The narrower width of the lower part of the N-type current channel 7 can better protect the gate groove angle and reduce the electric field at the gate groove angle.

[0107] See also Fig.15 , an N-type connection layer 16 is formed by N-type ion implantation in section A; and a P-type connection layer 18 is formed by P-type ion implantation in section 9. Fig.16 , there is a P-type connecting layer 18 in the cross section B, which can keep the P-type shielding layer 15 in a grounded state and improve the dynamic reliability of the device.

[0108] See also Fig.16 (Section A) and Fig.17 (Cross-section B), an initial gate dielectric layer 8 and an initial gate 9 are grown in the gate trench; see Fig.19 , the initial gate dielectric layer 8 and the initial gate electrode 9 are etched in the cross section A to form two gate dielectric structures and two gate structures separated by a preset distance, and an interlayer dielectric layer 10 is deposited and etched; see Fig. 20 , depositing an interlayer dielectric layer and etching in section B.

[0109] See also Fig.21 , etching the gate dielectric layer 8, depositing the Schottky metal 17 and etching; see Figure 2 and Figure 3 The ohmic contact metal 21 is deposited and etched; the source metal 11 is deposited and etched, and the drain metal 12 is deposited.

[0110] See also Fig. 22 , which is a schematic diagram of a cross section corresponding to the device provided in an embodiment of the present application, respectively corresponding to the gate 9 at different positions.

[0111] Silicon carbide (SiC) devices can achieve P-type doping through ion implantation or epitaxial growth. However, it is difficult to achieve P-type doping through ion implantation for materials with a wider bandgap than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). P-type can be achieved through special processes such as epitaxial growth or oxide growth.

[0112] The embodiment of the present application provides a method for preparing a semiconductor device, and the device prepared by the method includes: a substrate; a first N-type epitaxial layer located on one side of the substrate; a P-well region and a source N-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a source P-type contact region located on a side of the first N-type epitaxial layer away from the substrate; a gate trench penetrating the P-well region and the source N-type contact region; an N-type channel located on the sidewall of the gate trench and in the P-well region; an N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region and the N-type channel are connected; a gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the substrate; a source located on a side of the interlayer dielectric layer away from the substrate; and a drain located on a side of the substrate away from the source. The present application sets an N-type current extension region between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel and further connected to the source N-type contact region. The longitudinal setting of the N-type current extension region is more matched with the current path, which can reduce the on-resistance, improve the on-characteristics of the device, and improve the electrical performance of the device.

[0113] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0114] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a first N-type epitaxial layer located on one side of the substrate; A P-well region and a source N-type contact region located on a side of the first N-type epitaxial layer away from the substrate; A source P-type contact region located on a side of the first N-type epitaxial layer away from the substrate; A gate trench penetrating the P-well region and the source N-type contact region; An N-type channel in the P-well region located on the sidewall of the gate trench; An N-type current extension region located between the gate trench and the first N-type epitaxial layer; the N-type current extension region is connected to the N-type channel; A gate dielectric layer and a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the substrate; A source electrode located at a side of the interlayer dielectric layer away from the substrate; a drain electrode located at a side of the substrate away from the source electrode; a first P-type buried layer and a second N-type epitaxial layer located between the P-well region and the first N-type epitaxial layer; the N-type current extension region penetrates the first P-type buried layer and the second N-type epitaxial layer; The gate trench is located in the second N-type epitaxial layer; a P-type masking layer is located between the gate trench and the second N-type epitaxial layer; A third N-type semiconductor layer and a second P-type buried layer are sequentially stacked and located between the first P-type buried layer and the second N-type epitaxial layer.

2. The device according to claim 1, characterized in that The N-type current extension region is in a cup shape.

3. The device according to claim 1, characterized in that The gate includes two gate structures separated by a preset distance.

4. The device according to claim 1, characterized in that Also includes: An N-type connection layer located in the P-type shielding layer; A Schottky metal located on a side of the N-type connection layer away from the substrate; A P-type connecting layer penetrates the P-type shielding layer and the second N-type epitaxial layer and is connected to the first P-type buried layer.

5. The device according to claim 1, characterized in that Also includes: source trench; A source dielectric layer and a source structure are located in the source trench; the source P-type contact region is located around the outer wall of the source trench and wraps the source trench; An ohmic contact metal is located between the source P-type contact region and the source.

6. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; epitaxially growing a first N-type epitaxial layer on one side of the substrate; Growing a first P-type buried layer on the first N-type epitaxial layer, and growing a second N-type epitaxial layer on the first P-type buried layer; forming a third N-type semiconductor layer and a second P-type buried layer stacked in sequence between the first P-type buried layer and the second N-type epitaxial layer; Forming a P-well region on a side of the first N-type epitaxial layer away from the substrate by ion implantation or epitaxial growth; forming a source N-type contact region on a side of the P-well region away from the substrate by ion implantation; forming a source P-type contact region on a side of the first N-type epitaxial layer away from the substrate by ion implantation; Etching the P-well region and the source N-type contact region to form a gate trench; the gate trench is located in the second N-type epitaxial layer; A P-type masking layer is formed in the second N-type epitaxial layer at the bottom of the gate trench; Forming an N-type current extension region between the gate trench and the first N-type epitaxial layer by N-type ion implantation; forming an N-type channel in the P-well region by lateral diffusion on the sidewall of the gate trench; The N-type current extension region is connected to the N-type channel; the N-type current extension region penetrates the first P-type buried layer and the second N-type epitaxial layer; Growing a gate dielectric layer and a gate in the gate trench; and growing an interlayer dielectric layer on a side of the gate away from the substrate; A source electrode is grown on a side of the interlayer dielectric layer away from the substrate; and a drain electrode is grown on a side of the substrate away from the source electrode.

7. The method according to claim 6, characterized in that Growing a gate dielectric layer and a gate in the gate trench, comprising: growing an initial gate dielectric layer and an initial gate in the gate trench; The initial gate dielectric layer and the initial gate are etched to form two gate dielectric structures and two gate structures separated by a preset distance.

8. The method according to claim 6, characterized in that The N-type current extension region is in a cup shape.

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