SiC MOSFET device with dual-gate trench

Abstract

The utility model relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a double-gate groove, belonging to the technical field of semiconductors. The device comprises an active region and a terminal region. A first gate trench and a second gate trench are arranged in the active region, a P-type base region is arranged below the first gate trench, the side wall and the bottom of the first gate trench are covered with a gate oxide layer, and the first gate trench is filled with a polycrystalline silicon electrode and an interlayer medium; and a P-type protection region is arranged below the second gate trench, and the side wall and the bottom of the P-type protection region are covered with the gate oxide layer and filled with the polycrystalline silicon electrode. An N + type source region and a P + type source region penetrating through the N + type source region are arranged between the first gate trench and the second gate trench, and a source ohmic contact electrode is formed on the surface of the source region. Through the optimization of the double-gate trench structure and the doping design, the high reliability of the gate oxide layer, the uniformity of electric field distribution and the excellent conduction performance are realized, and the semiconductor device is suitable for high-power density occasions.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, and in particular to a SiCMOSFET device with double gate trenches. Background Art

[0002] In trench SiC MOSFET, the bottom of the gate trench is prone to electric field concentration, which may lead to reduced reliability of the gate oxide layer, thus affecting the long-term performance of the device. By increasing the junction depth of the P+ region to make it significantly greater than the depth of the gate trench, the coverage of the space charge region under the gate trench can be expanded, thereby effectively shielding high voltage and protecting the gate oxide layer.

[0003] However, in practical applications, increasing the P+ junction depth also brings certain challenges. For the active area of ​​the device, the large difference between the P+ junction depth and the gate trench depth will cause the current channel to be compressed, thereby increasing the specific on-resistance; for the terminal area, the larger P+ junction depth will cause the main junction electric field peak position to shift downward, making it difficult to transfer the electric field peak through the conventional JTE structure. In addition, increasing the P+ junction depth requires increasing the injection energy, which puts higher requirements on the mask process, which also limits the minimum spacing between adjacent P+ injection areas, thereby affecting the application of the traditional field limiting ring structure.

[0004] Therefore, although the introduction of deep P+ regions in trench SiC MOSFETs can significantly improve the reliability of the gate oxide layer, it may also lead to a decrease in the conduction capability and reduce the breakdown voltage of the device due to the mismatch with the conventional terminal design. Therefore, the design of the active area and the terminal area needs to be further optimized to achieve a balance between performance and reliability. Utility Model Content

[0005] The utility model aims to provide a SiC MOSFET device with dual gate trenches to solve the deficiencies in the prior art. The technical problem to be solved by the utility model is achieved through the following technical solutions.

[0006] The utility model proposes a SiC MOSFET device with a double gate trench, comprising an active region and a terminal region, wherein the active region and the terminal region have a SiC substrate and a drift layer located on the SiC substrate, and the active region comprises a plurality of cell structures.

[0007] The cell structure has a first gate trench A and a second gate trench B; a P-type base region is provided below the first gate trench A, and a gate oxide layer is provided on the sidewall and the two end regions of the bottom, and polysilicon electrodes are provided on the gate oxide layer in the two end regions of the bottom, and an interlayer dielectric is filled in the first gate trench A between the polysilicon electrodes;

[0008] A P-type protection layer is provided below the second gate trench B, a gate oxide layer is provided on the sidewall and bottom of the second gate trench B, and a polysilicon electrode is provided inside the second gate trench B;

[0009] A P-type base region, an N+-type source region and a P+-type source region are provided between the first gate trench A and the second gate trench B, the N+-type source region is located above the P-type base region, the P+-type source region penetrates the P-type base region and the N+-type source region and extends into the drift layer; the surface of the P+-type source region is flush with the N+-type source region, and a source ohmic contact electrode is provided on the P+-type source region; the P-type base region wraps the bottom corner of the first gate trench A;

[0010] The terminal region has a residual P+ type source region and an etched region formed by etching simultaneously with the first gate trench A. The depth of the residual P+ type source region is the injection junction depth of the P+ type source region minus the depth of the first gate trench A. There is a P-type base region inside the etched region.

[0011] A drain ohmic contact electrode is provided on the back side of the SiC substrate, and a layer of front metal is further provided on the cell structure.

[0012] Furthermore, the first gate trench A has a greater depth and a greater width than the second gate trench B.

[0013] Furthermore, the width of the first gate trench A is not less than 3 μm.

[0014] Furthermore, the depth of the first gate trench A is not less than 1.2 μm.

[0015] Furthermore, the angle of the sidewall of the first gate trench A is not less than 70°.

[0016] Furthermore, the implantation junction depth of the P+ type source region is not less than 1.5 μm.

[0017] Furthermore, the width and depth of the second gate trench B are both less than 1 μm.

[0018] Furthermore, the doping concentration of the P-type protection zone is not more than 1×10 18 cm -3 .

[0019] Furthermore, the width of the P-type base region directly below the first gate trench A of the active region does not exceed 2 μm.

[0020] The utility model includes the following advantages: the depth and width of the second gate groove used in the device of the present application are smaller than the first gate groove, the conduction of the second gate groove under low voltage ensures the opening of the device, and the conduction of the first gate groove after the voltage is increased improves the performance of the device under large current, and the use of double gate grooves can optimize the overall conduction characteristics of the device. In addition, the P-type base region of the terminal area of ​​the present application is implanted inside the etching area, which can increase the effective injection depth, play the role of JTE or Rings outside the main junction, alleviate the electric field peak and improve the breakdown voltage of the device, and the device structure does not need to introduce an additional terminal area injection process to optimize the blocking characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of a SiC MOSFET device with dual gate trenches of the utility model; DETAILED DESCRIPTION

[0022] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] like Figure 1 As shown, the utility model provides a SiC MOSFET device with a dual-gate trench structure, including an active region and a terminal region, wherein the active region and the terminal region have a SiC substrate 1 and a drift layer 2 located on the SiC substrate 1. The active region includes a plurality of cellular structures, and the cellular structure has a first gate trench A and a second gate trench B. A P-type base region 5 is provided below the first gate trench A, and its sidewalls and the bottom end regions are covered with a gate oxide layer 6, and a polysilicon electrode 7 is filled on the gate oxide layer. The first gate trench A is filled with an interlayer dielectric 8 to provide electrical isolation and mechanical support.

[0024] There is a P-type protection layer 10 below the second gate trench B. The doping concentration of the P-type protection layer 10 is controlled to be no more than 1×10¹ 8 cm -³ to prevent compression of the current path. The sidewalls and bottom of the second gate trench B are also covered with a gate oxide layer 6, and a polysilicon electrode 7 is filled inside. A P-type base region 5, an N+ type source region 3 and a P+ type source region 4 are provided between the first gate trench A and the second gate trench B. The N+ type source region 3 is located above the P-type base region, and the P+ type source region 4 penetrates the P-type base region and the N+ type source region 3 and extends into the drift layer 2. The injection junction depth of the P+ type source region 4 is designed to be no less than 1.5μm to ensure that the P+ injection can protect the gate oxide layer, and its surface is flush with the surface of the N+ type source region 3. The edge of the P-type base region 5 and the edge of the first gate trench A need to overlap by at least 0.2μm, so that the P-type base region 5 can wrap the bottom corner of the first gate trench A for protection, and at the same time, when the alignment of the two layers of photolithography is deviated during the process manufacturing process, it can ensure that the conductive channel can be normally formed on both sides of the first gate trench A.

[0025] There is a source ohmic contact electrode 9 on the P+ source region 4 and the N+ source region 3 to ensure good current conduction performance. In addition, a layer of front metal 12 is further formed on the surface of the cell structure to facilitate external wiring.

[0026] The structure of the terminal region has been optimized, and its P+ type source region has been etched, and the final depth is the depth of the P+ type source region injection junction minus the depth of the first gate trench A, thereby effectively alleviating the problem of uneven electric field distribution in the terminal region. The terminal region has an etched region formed by etching simultaneously with the first gate trench A, and a P-type base region is formed by injection inside the etched region, which can increase the effective injection depth, play the role of JTE or Rings outside the main junction, alleviate the electric field peak and increase the device breakdown voltage. The device structure does not need to introduce additional terminal region injection processes to optimize the blocking characteristics. The optimized terminal region design meets the compatibility with conventional junction end extension structures and can significantly improve the breakdown voltage performance of the device. A drain ohmic contact electrode 11 is set on the back side of the SiC substrate 1 to form a low-resistance connection with the external circuit.

[0027] In the dual-gate trench design of the utility model, the depth and width of the first gate trench A are greater than the second gate trench B. To be compatible with the large-scale etching process of the terminal area, the width of the first gate trench is not less than 3μm. To ensure that the electric field distribution in the terminal area can be optimized while reducing the specific on-resistance of the active area, the depth of the first gate trench is not less than 1.2μm. In order to optimize the electric field distribution in the terminal area, the sidewall of the first gate trench A can be designed to have a certain angle (not less than 70°), and this design will not affect the normal performance of the active area trench. The width and depth of the second gate trench B are both controlled within 1μm to compress the cell size. In addition, the width of the P-type base region 5 directly below the first gate trench A is controlled to be no more than 2μm to avoid excessive compression of the current path.

[0028] The key manufacturing methods of the above-mentioned devices are further described below. First, a SiC epitaxial wafer with a SiC substrate and a drift layer is prepared, wherein the thickness and doping concentration of the drift layer are designed according to the target withstand voltage requirements of the device. Next, an N+ region is formed in the active area using an ion implantation process, and the parameters of the implantation energy and dose are optimized to ensure that the N+ region has an appropriate depth and doping concentration to provide good conductivity for the device. At the same time, a P+ region is formed in the active area and the terminal area at the same time, and its junction depth and doping concentration are designed to ensure the protection effect of the gate oxide layer.

[0029] Through the etching process, the first gate trench is etched in the active area and the terminal area at the same time. The etching process needs to control the depth and sidewall angle of the trench. The sidewall of the first gate trench can have a certain angle, which is not less than 70°, to optimize the electric field distribution in the terminal area and ensure the normal performance of the active area trench. Subsequently, an ion implantation process is used to form a P-type base region in the active area and the terminal area. The implantation dose and energy are adjusted according to the design requirements to optimize the threshold voltage of the device and provide the necessary shielding function under the first gate trench without adversely affecting the performance of other areas.

[0030] The second gate trench is formed by etching again. The width and depth of the trench are controlled within 1μm to compress the cell size. After etching, ion implantation is performed using the same mask to form a P-type protection zone under the second gate trench.

[0031] After the trench structure is completed, the entire wafer is thermally oxidized to form a gate oxide layer on the sidewalls and bottom of the first gate trench and the second gate trench. Subsequently, a polysilicon layer is deposited on the wafer and patterned by an etching process so that the polysilicon fills the trench and forms a gate electrode.

[0032] For electrical isolation and mechanical support, an interlayer dielectric (ILD) is further deposited on the entire chip, and then holes are opened in the ILD layer through an etching process to expose the P+ and N+ regions, providing a channel for the formation of the source ohmic contact electrode. In the hole area, the source ohmic contact electrode is formed through a metallization process. The metal material is usually nickel or titanium, and the contact performance is optimized through a rapid thermal annealing process. The drain ohmic contact electrode is formed on the SiC substrate.

[0033] Finally, a layer of metal is formed on the front of the device. The front metal is prepared by a deposition process, and a low-resistance metal material such as aluminum is selected to facilitate external wiring. The entire device is completed with a passivation process to improve its environmental adaptability and long-term stability.

[0034] By introducing a dual-gate trench structure and optimizing the doping and geometric design of the P-type base region and the P-type protection zone, the utility model significantly improves the gate oxide layer reliability and high-voltage breakdown performance of the SiC MOSFET device, while achieving uniform distribution of the electric field in the terminal region. The entire design achieves excellent conduction performance while maintaining high reliability, providing an efficient solution for high-power density and long-life power electronic devices.

[0035] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.

[0036] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0038] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0039] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0040] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A SiC MOSFET device with dual gate trenches, comprising an active region and a terminal region, wherein the active region and the terminal region have a SiC substrate (1) and a drift layer (2) located on the SiC substrate (1), wherein the active region comprises a plurality of cell structures, and wherein: The cell structure comprises a first gate trench A and a second gate trench B; a P-type base region (5) is provided below the first gate trench A, a gate oxide layer (6) is provided on the sidewall and the two end regions of the bottom, polysilicon electrodes (7) are provided on the gate oxide layer (6) in the two end regions of the bottom, and an interlayer dielectric (8) is filled in the first gate trench A between the polysilicon electrodes (7); A P-type protection layer (10) is provided below the second gate trench B, a gate oxide layer (6) is provided on the sidewall and bottom of the second gate trench B, and a polysilicon electrode (7) is provided inside the second gate trench B; A P-type base region (5), an N+ type source region (3) and a P+ type source region (4) are provided between the first gate trench A and the second gate trench B, the N+ type source region (3) being located above the P-type base region (5), the P+ type source region (4) penetrating the P-type base region (5) and the N+ type source region (3) and extending into the drift layer (2); the surface of the P+ type source region (4) is flush with the N+ type source region (3), and a source ohmic contact electrode (9) is provided on the P+ type source region (4); the P-type base region (5) wraps around the bottom corner of the first gate trench A; The terminal region has a residual P+ type source region and an etched region formed by etching simultaneously with the first gate trench A, the depth of the residual P+ type source region is the injection junction depth of the P+ type source region minus the depth of the first gate trench A, and there is a P-type base region inside the etched region; A drain ohmic contact electrode (11) is provided on the back side of the SiC substrate (1), and a layer of front metal (12) is further provided on the cell structure.

2. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The first gate trench A has a greater depth and a greater width than the second gate trench B.

3. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The width of the first gate trench A is not less than 3 μm.

4. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The depth of the first gate trench A is not less than 1.2 μm.

5. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The angle of the side wall of the first gate trench A is not less than 70°.

6. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The injection junction depth of the P+ type source region (4) is not less than 1.5 μm.

7. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The width and depth of the second gate trench B are both less than 1 μm.

8. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The doping concentration of the P-type protection zone (10) does not exceed 1×10 18 cm -3 .

9. The SiC MOSFET device with dual gate trenches according to claim 1, characterized in that: The width of the P-type base region (5) directly below the first gate trench A of the active region does not exceed 2 μm.

Images