A method and device for managing RDMA data transmission queue based on hardware multithreading

Abstract

The present invention provides a method and device for managing an RDMA data transmission queue based on hardware multithreading. In a general execution scheme of an RDMA network card, multiple thread slots are set for query reading of contexts by a queue and query reading of memory translation table entries. When a read miss occurs, the corresponding task thread is re-added to an available thread slot for re-execution, thereby omitting the process of re-retrieval of corresponding query task information from a dynamic random access memory, and will not affect the execution of subsequent tasks in the queue and other active queues, thereby avoiding waste of logic resources and delay in handling all tasks.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for managing an RDMA data sending queue based on hardware multithreading. Background Art

[0002] When a typical RDMA Network Interface Card (RNIC) performs data transmission, all queue pair context information (QPC) and memory translation entry (MTE) are stored in a large-capacity dynamic random access memory (DRAM). DRAM has a long access delay. In order to reduce processing delay, the existing technology usually uses a static random access memory (SRAM) with a faster access speed to cache part of the QPC and MTE. Due to cost and manufacturing process constraints, the capacity of the SRAM on the chip is limited, and QPC and MTE cache misses are difficult to avoid. Every time a miss occurs, the RNIC needs to retrieve the corresponding information from the DRAM.

[0003] Typical RDMA applications usually have multiple active send queues. When a send queue misses in the query of QPC or MTE status information cache, causing the send queue processor (SQP) pipeline to be blocked, this blocking will result in the inability to process subsequent tasks of the same queue or affect other active queues, resulting in a waste of send queue processor pipeline logic resources and increased delays in processing all tasks. Therefore, a new data send queue management solution is urgently needed. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a method and device for managing an RDMA data sending queue based on hardware multithreading to eliminate or improve one or more defects in the prior art and solve the problem of blocking and delay of the RDMA data sending queue in the prior art due to the query queue not hitting the context information and memory translation table entries.

[0005] On the one hand, the present invention provides a method for managing an RDMA data transmission queue based on hardware multithreading, the method being executed based on an RDMA network card, and the method comprising the following steps:

[0006] In the idle state, arbitrate and obtain the send queue element at the head of the queue and the corresponding queue pair number from the non-empty send queue;

[0007] querying queue pair context information according to the sending queue element and the queue pair number, and generating a data packet header according to the queue pair context information;

[0008] Reading the scatter-gather list nested in the sending queue element, and querying the memory translation table entry according to the scatter-gather list to obtain the load physical memory address;

[0009] Generate a data packet descriptor according to the header and the load physical memory address, and deliver it to the direct memory access module for sending;

[0010] Among them, multiple first-class thread slots are set for querying the context information of the queue, and multiple second-class thread slots are set for querying the memory translation table entries; when the queue context information query thread is blocked due to a cache miss, the first-class thread slots are coordinated to rewrite the blocked query thread for re-execution; when the memory translation table entry query thread is blocked due to a cache miss, the second-class thread slots are coordinated to re-write the blocked query thread for re-execution.

[0011] In some embodiments, when the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution includes:

[0012] When the thread slot of the first type is not full, the context information query thread is directly written into the queue where the block occurs.

[0013] In some embodiments, when the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution includes:

[0014] When the task status of reading the queue pair context information is idle and the thread slot of the first type is not empty, first read out one or more available queue pair context information query threads, and write the blocked queue pair context information query thread to re-execute.

[0015] In some embodiments, when the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution includes:

[0016] When the task status of reading the queue pair context information is non-idle and the thread slot of the type has no available slots, querying the queue pair context information blocking prompt information is generated and displayed.

[0017] In some embodiments, when the memory translation table entry query thread is blocked due to a miss, the second type of thread slot is coordinated to rewrite the blocked query thread for re-execution, including: when the second type of thread slot is not full, directly write the blocked memory translation table entry query thread.

[0018] In some embodiments, when the memory translation table entry query thread is blocked due to a miss, coordinating the second type of thread slot to rewrite the blocked query thread for re-execution includes:

[0019] When the task status of reading the memory translation table entry is idle and the second type of thread slot is not empty, first read out one or more available memory translation table entry query threads, and write the blocked memory translation table entry query thread to re-execute.

[0020] In some embodiments, when the memory translation table entry query thread is blocked due to a miss, coordinating the second type of thread slot to rewrite the blocked query thread for re-execution includes:

[0021] When the task status of reading the memory translation table entry is non-idle and there is no available slot for the second type of thread slot, a query memory translation table entry blocking prompt information is generated and displayed.

[0022] In some embodiments, the first type of thread slot and the second type of thread slot indicate whether each thread is empty and the task status by setting a valid bit and a status bit mark.

[0023] On the other hand, the present invention also provides an RDMA data sending queue management device based on hardware multi-threading, including a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the device implements the steps of the above method.

[0024] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0025] The beneficial effects of the present invention are at least:

[0026] The RDMA data transmission queue management method and device based on hardware multithreading described in the present invention, in the general execution scheme of the RDMA network card, multiple thread slots are set for the query reading of the queue to the context and the query reading of the memory translation table item. When a read miss occurs, the corresponding task thread is re-added to the available thread slot for re-execution, omitting the process of re-retrieval of the corresponding query task information from the dynamic random access memory, and will not affect the execution of subsequent tasks in the queue and other active queues, thereby avoiding the waste of logic resources and the delay of the disposal of all tasks.

[0027] Additional advantages, purposes, and features of the present invention will be described in part in the following description, and will become apparent to those skilled in the art after studying the following, or may be learned from the practice of the present invention. The purposes and other advantages of the present invention may be achieved and obtained by the structures specifically indicated in the specification and the accompanying drawings.

[0028] Those skilled in the art will appreciate that the objectives and advantages that can be achieved with the present invention are not limited to the above specific description, and the above and other objectives that can be achieved by the present invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of the present application, and do not constitute a limitation of the present invention. In the drawings:

[0030] Figure 1 The figure is a schematic diagram of a data transmission mechanism of an RDMA network card according to an embodiment of the present invention.

[0031] Figure 2 The figure is a schematic diagram of an RDMA sending queue processing mechanism based on hardware multithreading according to an embodiment of the present invention.

[0032] Figure 3 (a) is a schematic diagram of a thread maintenance mechanism for reading queue context information in the RDMA transport layer sending queue processing thread state maintenance mechanism described in an embodiment of the present invention.

[0033] Figure 3 (b) is a schematic diagram of a thread maintenance mechanism for reading memory translation table entries in the RDMA transport layer send queue processing thread state maintenance mechanism described in an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of a thread maintenance mechanism for reading queue pair context information in the RDMA transport layer sending queue processing thread state maintenance mechanism according to another embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0036] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0037] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0038] It should also be noted that, unless otherwise specified, the term “connection” herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0040] In the prior art, in the data transmission mechanism of the RDMA Network Interface Card (RNIC), the Send Queue Processor (SQP) is the main user of the cache. Figure 1 , its use of cache includes the following two aspects:

[0041] (1) For connection-oriented reliable transmission (Reliable Connection, RC), the sending queue processor reads the queue pair context information according to the queue pair (QP) number to be processed, obtains the peer QP ID, the send packet sequence number (Send Packet Sequence Number, Send PSN), the IP and MAC address of the peer QP and other connection information, and thus generates the header of the data packet to be sent.

[0042] (2) The send queue element (SQE) uses a virtual address to represent the address of the data to be sent. The send queue processor needs to query the memory translation table entry (MTE), translate the corresponding physical address, and then use the physical address to perform direct memory access (Dynamic Memory Access, DMA) to read the data to be sent.

[0043] In a typical implementation, when a queue misses the context information and the memory translation table entry cache, the send queue processor processing pipeline needs to be blocked until the corresponding information is retrieved from the dynamic random access memory (DRAM) to the cache.

[0044] In the InfiniBand RDMA protocol, there is a processing order requirement for different send queue elements (SQEs) in a send queue, but there is no requirement for the processing order between different send queues. In order to cover up the overhead of queue context information and memory translation table cache misses, the present invention first defines the thread context model of the RDMA transport layer send processing pipeline from the hardware implementation level, and correspondingly provides a fast thread switching mechanism in the case of blocking of the send queue processor processing pipeline.

[0045] Specifically, the present invention provides a method for managing an RDMA data transmission queue based on hardware multithreading. The method is executed based on an RDMA network card. The method includes the following steps S101 to S104:

[0046] Step S101: in an idle state, arbitrating and obtaining a sending queue element at the head of a queue and a corresponding queue pair number from a non-empty sending queue.

[0047] Step S102: querying queue pair context information according to the sending queue element and the queue pair number, and generating a data packet header according to the queue pair context information.

[0048] Step S103: read the scatter-gather list nested in the sending queue element, and query the memory translation table entry according to the scatter-gather list to obtain the load physical memory address.

[0049] Step S104: Generate a data packet descriptor according to the header and the load physical memory address, and deliver it to the direct memory access module for transmission.

[0050] Among them, multiple first-class thread slots are set for querying the context information of the queue, and multiple second-class thread slots are set for querying the memory translation table entries; when the queue query thread for context information is blocked due to a cache miss, the first-class thread slots are coordinated to rewrite the blocked query thread for re-execution; when the memory translation table entry query thread is blocked due to a cache miss, the second-class thread slots are coordinated to re-write the blocked query thread for re-execution.

[0051] In steps S101 to S104, the send queue processor (SQP) of the RDMA network card performs data forwarding. The processing pipeline can be abstracted into four stages. The first step is to query the send queue element and queue pair number at the queue head, the second step is to query the queue pair context information and generate the data packet header, the third step is to obtain the load data, and the fourth step is to generate the data packet and forward it.

[0052] In RDMA (Remote Direct Memory Access), RDMA communication usually uses SendQueue and ReceiveQueue to coordinate data transmission. Send Queue (SQ) is a queue maintained by the RDMA adapter, which contains relevant information about the message to be sent. SQE (Send Queue Element) is an element in this queue, representing a send operation. Each SQE contains information such as the description of the data to be sent and the target address.

[0053] Queue Pair (QP), a queue pair contains queues in two directions: send queue (SQ) and receive queue (RQ). Each queue contains multiple elements used to describe and control data transmission in the corresponding direction. QP is a combination of SQ and RQ, representing a pair of mutually related queues. A QP can be used to establish an RDMA connection between two nodes. Queue Pair Context (QPC) is a context data structure associated with a queue pair (QP). QPC contains some important information about RDMA communication so that the adapter can perform data transmission correctly; for example, local and remote memory address information, send and receive queue information, queue size and status information, etc.

[0054] The data payload to be sent is obtained from the host memory through the Scatter Gather List (SGL). The data payload is stored in multiple parts of the host memory in a scattered manner instead of being stored continuously. In order to efficiently read these scattered data, the network card uses the data structure of the Scatter Gather List. This SGL list lists in detail all the locations and lengths of the data payload in the host memory. When it is necessary to read these data, the network card uses DMA (direct memory access) technology to read the data from the corresponding locations of the host memory one by one in the order listed through the SGL list until all the data has been read. This method not only improves the efficiency of data transmission, but also reduces the burden on the CPU.

[0055] The memory translation table entry (MET) is a data structure used to establish a mapping between virtual addresses and physical addresses between the RDMA adapter and the host memory. MET is responsible for managing how the RDMA adapter accesses the host memory to achieve direct memory access and obtain data payloads without the intervention of the host CPU.

[0056] The RDMA adapter can use MET to directly map virtual addresses to physical addresses, and then use SGL to describe the non-contiguous memory blocks that need to be transferred. MET ensures that the RDMA adapter can access these memory blocks correctly, while SGL provides a mechanism to organize and describe these non-contiguous memory blocks.

[0057] Finally, a data packet descriptor is generated and handed over to the direct memory access module (MDA module) for forwarding.

[0058] During this process, the queue context information and memory translation table entries are usually stored in the cache, and misses may occur to prevent affecting subsequent tasks in the queue.

[0059] The present application sets up multi-threading on the hardware, sets multiple first-class thread slots for querying the queue for context information, and sets multiple second-class thread slots for querying the memory translation table entries; exemplarily, 4 first-class thread slots and 4 second-class thread slots can be set respectively, indicating that the maximum number of waiting threads supported in the stage of querying the reading queue for context information and memory translation table entries is 4.

[0060] During operation, when the read queue is blocked for context information or memory translation table entries due to a cache miss, the blocked task can be rewritten into an available thread slot and the query read can be re-executed.

[0061] In some embodiments, when a queue-to-context information query thread is blocked due to a cache miss, a class of thread slots is coordinated to rewrite the blocked query thread for re-execution, including step S201: when a class of thread slots is not full, directly write the blocked queue-to-context information query thread.

[0062] In some embodiments, when a queue pair context information query thread is blocked due to a cache miss, a class of thread slots is coordinated to rewrite the blocked query thread for re-execution, including step S202: when the task status of reading the queue pair context information is idle and a class of thread slots is non-empty, first read one or more available queue pair context information query threads, and write the blocked queue pair context information query thread for re-execution.

[0063] In some embodiments, when a queue pair context information query thread is blocked due to a cache miss, a class of thread slots is coordinated to rewrite the blocked query thread for re-execution, including step S203: when the task status of reading the queue pair context information is non-idle and a class of thread slots has no available slots, query queue pair context information blocking prompt information is generated and displayed.

[0064] In some embodiments, when a memory translation table entry query thread is blocked due to a miss, the second type of thread slot is coordinated to rewrite the blocked query thread for re-execution, including step S301: when the second type of thread slot is not full, directly write the blocked memory translation table entry query thread.

[0065] In some embodiments, when a memory translation table entry query thread is blocked due to a miss, the second type of thread slot is coordinated to rewrite the blocked query thread for re-execution, including step S302: when the task status of reading the memory translation table entry is idle and the second type of thread slot is non-empty, first read one or more available memory translation table entry query threads, and write the blocked memory translation table entry query thread for re-execution.

[0066] In some embodiments, when a memory translation table entry query thread is blocked due to a miss, the second-class thread slot is coordinated to rewrite the blocked query thread for re-execution, including step S303: when the task status of reading the memory translation table entry is non-idle and there is no available slot in the second-class thread slot, a query memory translation table entry blocking prompt information is generated and displayed.

[0067] In some embodiments, the first type thread slot and the second type thread slot indicate whether each thread is empty and the task status by setting the valid bit (Valid) and the status bit (Ready) mark. The valid bit is 1 for valid, and 0 for invalid. The status bit is 1 for available, and 0 for unavailable.

[0068] On the other hand, the present invention also provides an RDMA data sending queue management device based on hardware multi-threading, including a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the device implements the steps of the above method.

[0069] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0070] The present invention is described below in conjunction with a specific embodiment:

[0071] This embodiment first provides an RDMA send queue processing mechanism based on hardware multithreading, abstracting the processing pipeline of the send queue processor SQP into the following five stages: Figure 2 As shown:

[0072] 1. Read the send queue element SQE (Read SQE): In the idle state, request the upper-level module to read the send queue element SQE. The upper-level module first arbitrates from the non-empty send queue (Send Queue, SQ), and takes the send queue element at the head of the queue from the arbitrated SQ, and finally inputs the arbitrated SQ number and send queue element SQE into the ReadSQE module; the Read SQE module parses the send queue element SQE according to the specification.

[0073] 2. Read queue pair context information (Read QPC): Read the queue pair context information QPC from the cache according to the send queue element number SQE QP. The queue pair context information includes all the information used to generate the RDMA data packet header corresponding to the send queue element SQE to be processed. The main content includes the peer QP ID for establishing binding, the MAC address and IP address of the peer QP, and the send data packet sequence number PSN.

[0074] 3. Header Generation: Generate the header of the transport layer data packet based on the send queue element SQE and the queue pair context information QPC.

[0075] 4. Read Memory Translation Table Entries (Read MTE): For sending and RDMA write operations, the NIC needs to read the data payload to be sent from the host memory in DMA mode based on the Scatter Gather List (SGL). SGL is nested in the send queue element SQE. Each SGL item includes the local virtual address (Local Address) of the data to be sent, the local key (Local Key), and the data length (Length). The NIC needs to use the physical address to perform DMA operations. In a typical implementation, SGL needs to be used to query the memory translation table entry MTE.

[0076] 5. Packet Descriptor Generation: Generate a packet descriptor based on the header (Header) obtained in the header generation phase and the load (Payload) physical memory address obtained in the read memory translation table entry (Read MTE) phase, and deliver it to the downstream direct memory access module (DMA module) for sending.

[0077] In the processing pipeline of the send queue processor, there are QPC cache misses and MTE cache misses in the execution of reading queue context information (Read QPC) and reading memory translation table entries (Read MTE), respectively, with a long uncertain delay.

[0078] This embodiment provides a RDMA transport layer send queue processing thread state maintenance mechanism, which is as follows:

[0079] This embodiment first defines the content of the Read QPC and Read MTE threads, where the Read QPC thread includes the QP ID and the SQE content parsed in the Read SQE stage, and the Read MTE thread includes the Local Key and the Header Template generated in the Header Generation stage. Due to the limitation of the Path Maximum Transmission Unit (PMTU), a send queue element SQE corresponding to a send or RDMA write message includes multiple RDMA packets, each of which requires a Header and Payload Descriptor. The Header Template is used to generate the header of all packets of a Message.

[0080] like Figure 3 (a) and Figure 4 As shown, the queue pair context information thread waiting queue (QPC Thread Wait Queue) is taken as an example, which includes 4 QPC thread slots, each of which also includes a valid bit and a ready bit. The 4 QPC thread slots indicate that the maximum number of waiting threads supported in the Read QPC stage is 4. In the Read QPC stage, when the QPC Thread WaitQueue is not full, the blocked queue pair context information query thread (QPC Thread) can be written; when the ReadQPC is idle and the QPC Thread Wait Queue is not empty (the available slots are counted), the available QPCThread can be read out for processing. The QPC Thread Wait Queue listens to the fill QP ID (QPC Fill ID) from the QPC cache, and compares it with the QP ID in all valid slots (Valid bit is 1) in the QPC Thread Wait Queue. If they are equal, the Ready bit of the corresponding slot is set.

[0081] Specifically, take the queue pair context information query thread (QPC Thread) as an example:

[0082] (1) The Read QPC stage is idle (Ready is 1), and the Read SQE outputs the parsed SQE and the corresponding QP ID, and sets Valid.

[0083] (2) Read QPC accesses the QPC cache based on the QP ID to read the QPC. If it hits, it continues to execute at the next level; if it misses, it writes the blocked QPC Thread to the QPC Wait Thread Queue, sets Ready again, and receives the next SQE. If a miss occurs, the QPC Wait Thread Queue is full and Empty (no available slot), then the Read QPC stage is blocked; if it is not Empty, it reads an executable QPC Thread and then writes the blocked QPCThread to the QPC Wait Thread Queue.

[0084] (3) If the Read QPC is idle and the Read SQE has no new input, and the QPC Wait Thread Queue is not empty, the Read QPC reads an available slot from the QPC Wait Thread Queue.

[0085] Further, such as Figure 3 (b) The handling solution for the Read MTE thread can refer to the handling solution for the Read QPC thread.

[0086] In order to explain the superiority of this embodiment over the traditional blocking execution method in principle, the following assumptions are made: only considering the case where the queue misses the cache of context information, each level of the pipeline in this embodiment can process a transaction once in one cycle, the probability of the queue missing the cache of context information is P, the overhead is A cycles, and there are enough active queues to be processed.

[0087] Based on the blocking execution mode, the number of clock cycles required to process N send queue elements SQE is N+4+P(A+1); based on the non-blocking mode proposed in this implementation, the thread switching overhead is fixed at 2 cycles, and the number of clock cycles required to execute N send queue elements SQE is N+4+P(2+1). In a typical case, A is greater than 2, so this embodiment can save P(A-2) cycles compared to the blocking execution mode.

[0088] An embodiment of the present invention further provides a computer device, which may include a processor and a memory, wherein the processor and the memory may be connected via a bus or in other ways.

[0089] The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0090] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the key shielding method of the vehicle-mounted display device in the embodiment of the present invention. The processor executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory.

[0091] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0092] The one or more modules are stored in the memory, and when executed by the processor, the method described in this embodiment is performed.

[0093] The embodiment of the present invention also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned edge computing server deployment method are implemented. The computer-readable storage medium can be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0094] In summary, the RDMA data sending queue management method and device based on hardware multithreading described in the present invention, in the general execution scheme of the RDMA network card, sets multiple thread slots for the query reading of the queue to the context and the query reading of the memory translation table item. When a read miss occurs, the corresponding task thread is re-added to the available thread slot for re-execution, omitting the process of re-retrieval of the corresponding query task information from the dynamic random access memory, and will not affect the execution of subsequent tasks in the queue and other active queues, thereby avoiding the waste of logical resources and the delay of the handling of all tasks.

[0095] It should be understood by those skilled in the art that the exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0096] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention.

[0097] In the present invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with features of other embodiments or replace features of other embodiments.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for managing RDMA data transmission queues based on hardware multithreading, characterized in that: The method is performed based on an RDMA network card, and the method comprises the following steps: In the idle state, arbitrate and obtain the send queue element at the head of the queue and the corresponding queue pair number from the non-empty send queue; querying queue pair context information according to the sending queue element and the queue pair number, and generating a data packet header according to the queue pair context information; Reading the scatter-gather list nested in the sending queue element, and querying the memory translation table entry according to the scatter-gather list to obtain the load physical memory address; Generate a data packet descriptor according to the header and the load physical memory address, and deliver it to the direct memory access module for sending; Among them, multiple first-class thread slots are set for querying the context information of the queue, and multiple second-class thread slots are set for querying the memory translation table entries; when the queue context information query thread is blocked due to a cache miss, the first-class thread slots are coordinated to rewrite the blocked query thread for re-execution; when the memory translation table entry query thread is blocked due to a cache miss, the second-class thread slots are coordinated to re-write the blocked query thread for re-execution.

2. The RDMA data sending queue management method based on hardware multithreading according to claim 1 is characterized in that: When the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution, including: When the thread slot of the first type is not full, the context information query thread is directly written into the queue where the block occurs.

3. The RDMA data transmission queue management method based on hardware multithreading according to claim 2 is characterized in that: When the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution, including: When the task status of reading the queue pair context information is idle and the thread slot of the first type is not empty, first read out one or more available queue pair context information query threads, and write the blocked queue pair context information query thread to re-execute.

4. The RDMA data transmission queue management method based on hardware multithreading according to claim 3 is characterized in that: When the queue blocks the context information query thread due to a cache miss, coordinating the first type of thread slot to rewrite the blocked query thread for re-execution, including: When the task status of reading the queue pair context information is non-idle and the thread slot of the type has no available slots, querying the queue pair context information blocking prompt information is generated and displayed.

5. The RDMA data sending queue management method based on hardware multithreading according to claim 1, characterized in that: When the memory translation table entry query thread is blocked due to a miss, coordinating the second type of thread slot to rewrite the blocked query thread for re-execution, including: When the second-class thread slot is not full, the blocked memory translation table entry query thread is directly written.

6. The RDMA data sending queue management method based on hardware multithreading according to claim 5 is characterized in that: When the memory translation table entry query thread is blocked due to a miss, coordinating the second type of thread slot to rewrite the blocked query thread for re-execution, including: When the task status of reading the memory translation table entry is idle and the second type of thread slot is not empty, first read out one or more available memory translation table entry query threads, and write the blocked memory translation table entry query thread to re-execute.

7. The RDMA data transmission queue management method based on hardware multithreading according to claim 6 is characterized in that: When the memory translation table entry query thread is blocked due to a miss, coordinating the second type of thread slot to rewrite the blocked query thread for re-execution, including: When the task status of reading the memory translation table entry is non-idle and there is no available slot for the second type of thread slot, a query memory translation table entry blocking prompt information is generated and displayed.

8. The RDMA data sending queue management method based on hardware multithreading according to claim 1, characterized in that: The first type of thread slot and the second type of thread slot indicate whether each thread is empty and the task status by setting a valid bit and a status bit mark.

9. A RDMA data transmission queue management device based on hardware multithreading, comprising a processor and a memory, characterized in that: The memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the device implements the steps of the method as claimed in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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