Semiconductor devices, RF chips and electronic devices

Abstract

The present application discloses a semiconductor device, a radio frequency chip and an electronic device, belonging to the field of semiconductor technology. The semiconductor device includes a silicon-on-insulator substrate having a top silicon layer, a gate wiring located on the upper surface of the top silicon layer, a plurality of first contact holes, a plurality of second contact holes, a first metal part and a second metal part; wherein the spacing between adjacent first contact holes and second contact holes is greater than a target distance, the target distance being the spacing when the first contact hole and the second contact hole are respectively located in the middle of the region in which they are located and facing each other along a second direction, the second direction being perpendicular to the first direction; and / or the two opposite sides of the first metal part and the second metal part are parallel, and at least one contact hole is flush with one of the two opposite sides. By increasing the spacing between adjacent contact holes, the parasitic capacitance between the contact holes and between the contact holes and the gate wiring can be reduced, thereby improving device performance.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device, a radio frequency chip and an electronic device. Background Art

[0002] In the design of SOI (Silicon-On-Insulator) devices, parasitic capacitance has an important impact on device performance. The silicon-on-insulator substrate leads to the source and drain terminals through the contact structure, and a gate wiring is arranged between the two contact structures. Therefore, parasitic capacitance will be generated between the source, drain and gate wiring, affecting the performance of SOI devices. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a semiconductor device, a radio frequency chip and an electronic device, which reduce the parasitic capacitance between contact holes and between contact holes and gate wirings, and improve device performance.

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] A silicon-on-insulator substrate having a top silicon layer;

[0006] A gate wiring is formed on the upper surface of the top silicon layer, and defines a separated first region and a second region on the upper surface of the top silicon layer;

[0007] A plurality of first contact holes are formed in a first region of the upper surface of the top silicon layer and arranged along a first direction;

[0008] A plurality of second contact holes are formed in a second region of the upper surface of the top silicon layer and arranged along the first direction;

[0009] A first metal member connected to the plurality of first contact holes;

[0010] A second metal member connected to the plurality of second contact holes;

[0011] The distance between adjacent first contact holes and second contact holes is greater than a target distance, the target distance being the distance between the first contact hole and the second contact hole when they are respectively located in the middle of the region and facing each other along a second direction, the second direction being perpendicular to the first direction; and / or

[0012] The two opposite sides of the first metal member and the second metal member are parallel, and at least one contact hole is flush with one of the two opposite sides.

[0013] According to the semiconductor device of the present application, a first contact hole and a second contact hole are provided on the silicon-on-insulator substrate, the first contact hole is used to lead out a source terminal (or a drain terminal), and the second contact hole is used to lead out a drain terminal (or a source terminal), and by increasing the spacing between adjacent first contact holes and second contact holes, the parasitic capacitance between the contact holes and between the contact holes and the gate wiring can be reduced, thereby improving device performance.

[0014] According to an embodiment of the present application, along the first direction, the first contact holes and the second contact holes are arranged alternately.

[0015] According to an embodiment of the present application, along the second direction, a distance between the contact hole and a side of the region in which the contact hole is located is smaller than a distance between the contact hole and the gate wiring.

[0016] According to an embodiment of the present application, along the second direction, the first contact hole and the second contact hole are arranged opposite to each other, and a first spacing between the contact hole and the side of the region in which the contact hole is located is smaller than a second spacing between the contact hole and the gate wiring.

[0017] According to an embodiment of the present application, the two opposite sides are arranged along the first direction, and each contact hole is flush with one of the corresponding two sides.

[0018] According to an embodiment of the present application, the first metal member and the second metal member are both members of unequal width, and two opposite sides form a first angle with the first direction, and the first angle is greater than 0.

[0019] In a second aspect, the present application also provides a radio frequency chip, comprising the semiconductor device according to the foregoing.

[0020] In a third aspect, the present application also provides an electronic device, comprising the aforementioned radio frequency chip.

[0021] According to the radio frequency chip and electronic device of the present application, the semiconductor devices used are less interfered by parasitic capacitance, and the performance of the chip and the device is higher.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a cross-sectional view of a semiconductor device;

[0025] Figure 2 It is a schematic diagram of a contact structure of a semiconductor device in the related art;

[0026] Figure 3 This is one of the contact structure schematic diagrams of a semiconductor device provided in an embodiment of the present application;

[0027] Figure 4 This is the second schematic diagram of a contact structure of a semiconductor device provided in an embodiment of the present application;

[0028] Figure 5 This is a third schematic diagram of a contact structure of a semiconductor device provided in an embodiment of the present application;

[0029] Figure 6 This is a fourth schematic diagram of a contact structure of a semiconductor device provided in an embodiment of the present application;

[0030] Figure 7 This is a fifth schematic diagram of a contact structure of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 8 This is the sixth schematic diagram of a contact structure of a semiconductor device provided in an embodiment of the present application;

[0032] Fig. 9 This is the seventh contact structure schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0033] Reference numerals:

[0034] Silicon-on-insulator substrate 10 , insulating substrate 11 , trapping layer 12 , buried oxide layer 13 and top silicon 14 , gate wiring 20 , gate dielectric layer 21 , gate metal 22 , first contact hole 30 , second contact hole 40 , first metal member 50 , second metal member 60 . DETAILED DESCRIPTION

[0035] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0037] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0038] Reference Figure 1 and Figure 2 , Figure 1 shows a cross-sectional view of a semiconductor device, Figure 2 A schematic diagram of a contact structure of a semiconductor device is shown. The present application provides a semiconductor device.

[0039] The semiconductor device may be an SOI device, such as RF-SOI (radio frequency silicon on insulator). The semiconductor device includes a silicon-on-insulator substrate 10, a gate wiring 20, a first contact hole 30, a second contact hole 40, a first metal member 50, and a second metal member 60. The silicon-on-insulator substrate 10 includes an insulating substrate 11, a trapping layer 12, a buried oxide layer 13, and a top silicon layer 14 stacked sequentially from bottom to top. In some types of SOI devices, the silicon-on-insulator substrate 10 may not include the trapping layer 12.

[0040] The gate wiring 20 includes a gate dielectric layer 21 and a gate metal 22. The gate dielectric layer 21 is coated on the top silicon 14, and the gate metal 22 can be attached to the gate dielectric layer 21. Figure 2 As shown, as an example, the gate wiring 20 may be T-shaped.

[0041] A source contact and a drain contact may be formed in the top silicon 14, the first metal member 50 forms a conductive connection with the source contact (or drain contact) through the first contact hole 30 to lead out the source terminal (or drain terminal), and the second metal member 60 forms a conductive connection with the drain contact (or source contact) through the second contact hole 40 to lead out the drain terminal (or source terminal). There are mature technologies for the structure and materials of each layer in the silicon-on-insulator substrate 10, and this embodiment will not be repeated here.

[0042] Usually, there are multiple first contact holes 30, and each of them is connected to a first metal member 50; there are multiple second contact holes 40, and each of them is connected to a second metal member 60. Parasitic capacitance will be generated between the first contact hole 30 and the second contact hole 40, between the first metal member 50 and the second metal member 60, and between the gate wiring 20 and each contact hole or each metal member, thereby affecting the performance of the SOI device.

[0043] The semiconductor device proposed in the present application can reduce the parasitic capacitance between contact holes and between the contact holes and the gate wiring by increasing the spacing between adjacent first contact holes and second contact holes, thereby improving device performance.

[0044] Reference Figure 3 , Figure 4 and Figure 5 , Figure 3 , Figure 4 and Figure 5 A schematic diagram of a contact structure of a semiconductor device is shown. An embodiment of the present application provides a semiconductor device. In this embodiment, a silicon-on-insulator substrate 10 has a top silicon layer 14; a gate wiring 20 is formed on the upper surface of the top silicon layer 14, and a first region A and a second region B separated from each other are defined on the upper surface of the top silicon layer 14; a plurality of first contact holes 30 are formed in the first region A on the upper surface of the top silicon layer 14, and are arranged along a first direction; a plurality of second contact holes 40 are formed in the second region B on the upper surface of the top silicon layer 14, and are arranged along a first direction; wherein the spacing d1 between adjacent first contact holes 30 and second contact holes 40 is greater than a target distance d2, and the target distance is the spacing when the first contact hole 30 and the second contact hole 40 are respectively located in the middle of the region and face each other along the second direction, and the second direction is perpendicular to the first direction.

[0045] As an example, the gate wiring 20 is T-shaped, wherein the vertical portion divides the upper surface of the top silicon layer 14 into a first region A and a second region B. The vertical portion is arranged in the middle of the upper surface, that is, the length and width of the first region A and the second region B may be the same.

[0046] by Figure 3 Taking the plane shown as an example, the first direction may be the up-down direction, the second direction may be the left-right direction, and the vertical part may be arranged along the up-down direction. In the first region A, each first contact hole 30 may be arranged in an aligned manner along the up-down direction. In the second region B, each second contact hole 40 may be arranged in an aligned manner along the up-down direction. Figure 3 The square contact hole shown in the figure is only an example, and may also be a circle, etc., which is not limited in this embodiment.

[0047] The second contact hole 40 adjacent to the first contact hole 30 refers to the second contact hole 40 closest to the first contact hole 30 , and the first contact hole 30 adjacent to the second contact hole 40 refers to the first contact hole 30 closest to the second contact hole 40 .

[0048] by Figure 2 As an example of the contact structure schematic diagram shown in FIG. 1 , adjacent first contact holes 30 and second contact holes 40 refer to first contact holes 30 and second contact holes 40 aligned in the left-right direction. Figure 3 Taking the contact structure schematic diagram shown in FIG. 1 as an example, the adjacent first contact hole 30 and the second contact hole 40 refer to the first contact hole 30 and the second contact hole 40 which are diagonally opposite to each other.

[0049] The target distance d2 refers to the distance between the first contact hole 30 located in the middle of the first area A and the second contact hole 40 located in the middle of the second area B aligned in the left-right direction. Figure 2 The distance between the first contact hole 30 and the second contact hole 40 in the contact structure schematic diagram shown. The middle of the region means that the distance between the contact hole and the edges on the left and right sides of the region is equal.

[0050] In some embodiments, the distance between the first contact hole 30 and the gate wiring 20 may be equal to the distance between the second contact hole 40 and the gate wiring 20. Thus, the arrangement track of the first contact holes 30 and the arrangement track of the second contact holes 40 are symmetrical along the gate wiring 20.

[0051] Since the interval d1 between the adjacent first contact holes 30 and the second contact holes 40 is greater than the target distance d2, the parasitic capacitance generated between the first contact holes 30 and the second contact holes 40 is smaller, and the influence on the SOI device is smaller.

[0052] According to the semiconductor device of the present application, a first contact hole 30 and a second contact hole 40 are provided on the silicon-on-insulator substrate 10. The first contact hole 30 is used to lead out the source terminal (or drain terminal), and the second contact hole 40 is used to lead out the drain terminal (or source terminal). By increasing the spacing between adjacent first contact holes 30 and second contact holes 40, the parasitic capacitance between the contact holes and between the contact holes and the gate wiring 20 can be reduced, thereby improving the device performance.

[0053] Continue to refer to Figure 3 In some embodiments, along the first direction, the first contact holes 30 and the second contact holes 40 are alternately arranged.

[0054] In this embodiment, the projections of the first contact holes 30 and the second contact holes 40 in the first direction do not overlap, so the first contact holes 30 and the second contact holes 40 are alternately arranged in the first direction. Thus, the adjacent first contact holes 30 and the second contact holes 40 are arranged obliquely, thereby increasing the spacing between the adjacent first contact holes 30 and the second contact holes 40 in a limited space.

[0055] As an example, the spacing between the second contact hole 40 and the first contact hole 30 opposite obliquely above is the same as the spacing between the first contact holes 30 opposite obliquely below. Thus, in the first direction, the first contact holes 30 and the second contact holes 40 are alternately arranged at a uniform spacing.

[0056] Continue to refer to Figure 4 , along the second direction, the distance between the contact hole and the side of the region in which it is located is smaller than the distance between the contact hole and the gate wiring.

[0057] In this embodiment, the first region A is located on the left side of the gate wiring 20, and the second region B is located on the right side of the gate wiring 20. The spacing between the first contact hole 30 and the left side of the first region A is smaller than the spacing between the first contact hole 30 and the gate wiring 20. The spacing between the second contact hole 40 and the right side of the second region B is smaller than the spacing between the second contact hole 40 and the gate wiring 20.

[0058] The first contact hole 30 and the second contact hole 40 can be arranged close to the edges of their respective regions, so as to further increase the distance d1 between the first contact hole 30 and the second contact hole 40 and reduce the parasitic capacitance; in addition, the parasitic capacitance between the first contact hole 30 and the gate wiring 20 and the parasitic capacitance between the second contact hole 40 and the gate wiring 20 can also be reduced.

[0059] In other embodiments, the projections of the first contact hole 30 and the second contact hole 40 in the first direction may also partially overlap, and the first contact hole 30 and the second contact hole 40 may be arranged close to the edges of the respective regions. Thus, more first contact holes 30 and second contact holes 40 may be arranged in the first direction, so that the number of contact holes may be increased while reducing the parasitic capacitance between the contact holes and between the contact holes and the gate wiring 20, thereby reducing the contact resistance between the source terminal and the drain terminal and the metal member.

[0060] Continue to refer to Figure 5 Along the second direction, the first contact hole 30 and the second contact hole 40 are arranged opposite to each other, and a first spacing between the contact hole and the side of the region in which the contact hole is located is smaller than a second spacing between the contact hole and the gate wiring.

[0061] In this embodiment, the first contact hole 30 and the second contact hole 40 are aligned in the left-right direction. The spacing between the first contact hole 30 and the left side of the first region A is smaller than the spacing between the first contact hole 30 and the gate wiring 20. The spacing between the second contact hole 40 and the right side of the second region B is smaller than the spacing between the second contact hole 40 and the gate wiring 20.

[0062] Since the first contact hole 30 and the second contact hole 40 can be arranged close to the edge of the respective region, more first contact holes 30 and second contact holes 40 can be arranged in the first direction while reducing the parasitic capacitance between the contact holes and between the contact holes and the gate wiring 20, thereby increasing the number of contact holes and reducing the contact resistance between the source terminal and the drain terminal and the metal member.

[0063] In some embodiments, multiple first contact holes 30 are connected to the first metal member 50, multiple second contact holes 40 are connected to the second metal member 60, the opposite sides of the first metal member 50 and the second metal member 60 are parallel, and at least one contact hole is flush with one of the opposite sides.

[0064] In this embodiment, at least one first contact hole 30 is flush with the side of the first metal member 50 facing the second metal member 60, or at least one second contact hole 40 is flush with the side of the second metal member 60 facing the first metal member 50. The side of the first metal member 50 facing the second metal member 60 is parallel to the side of the second metal member 60 facing the first metal member 50, and the spacing between the first metal member 50 and the second metal member 60 is the same everywhere.

[0065] Since the metal part needs to at least completely cover the contact hole, some of the metal parts are arranged flush with the contact hole so that the metal parts are as far away from each other as possible, which can reduce the parasitic capacitance between the first metal part 50 and the second metal part 60, and also reduce the parasitic capacitance between the metal part and the gate wiring 20.

[0066] Reference Figure 6 , Figure 6 A schematic diagram of a contact structure of a semiconductor device is shown. In some embodiments, the two opposite sides are arranged along the first direction, and each contact hole is flush with one of the two corresponding sides.

[0067] In this embodiment, the side of the first metal member 50 facing the second metal member 60 is parallel to the first direction, and the side of the second metal member 60 facing the first metal member 50 is parallel to the first direction. Since the two side sides are parallel to the arrangement direction of the contact holes, all the first contact holes 30 are flush with the side of the first metal member 50 facing the second metal member 60, and all the second contact holes 40 are flush with the side of the second metal member 60 facing the first metal member 50. The spacing between the first metal member 50 and the second metal member 60 reaches the maximum value, reducing the parasitic capacitance between the first metal member 50 and the second metal member 60 and between the metal members and the gate wiring 20.

[0068] Reference Figure 7 , Figure 7 A schematic diagram of a contact structure of a semiconductor device is shown. In some embodiments, the first metal member 50 and the second metal member 60 are both unequal width members, and both opposite sides form a first angle with the first direction, and the first angle is greater than 0.

[0069] In this embodiment, the first metal part 50 is arranged obliquely toward the side of the second metal part 60 and the first direction, and the second metal part 60 is arranged obliquely toward the side of the first metal part 50 and the first direction, which can also reduce the parasitic capacitance between the first metal part 50 and the second metal part 60 and between the metal parts and the gate wiring 20.

[0070] The side of the first metal member 50 facing away from the second metal member 60 is mirror-symmetrical with the side facing the second metal member 60 along the first direction, and the side of the second metal member 60 facing away from the first metal member 50 is mirror-symmetrical with the side facing the first metal member 50 along the first direction. In the first direction, the widths of the first metal member 50 and the second metal member 60 are different at different locations, thereby reducing the size of the metal members.

[0071] In other embodiments, the side of the first metal member 50 facing away from the second metal member 60 may be parallel to the first direction, and the side of the second metal member 60 facing away from the first metal member 50 may be parallel to the first direction.

[0072] Reference Figure 8 and Fig. 9 , Figure 8 and Fig. 9A schematic diagram of a contact structure of a semiconductor device is shown. An embodiment of the present application also provides a semiconductor device. In this embodiment, a silicon-on-insulator substrate 10 has a top silicon layer 14; a gate wiring 20 is formed on the upper surface of the top silicon layer 14, and a first region A and a second region B separated from each other are defined on the upper surface of the top silicon layer 14; a plurality of first contact holes 30 are formed in the first region A on the upper surface of the top silicon layer 14, and are arranged along a first direction; a plurality of second contact holes 40 are formed in the second region B on the upper surface of the top silicon layer 14, and are arranged along a first direction; a plurality of first contact holes 30 are connected to a first metal member 50, a plurality of second contact holes 40 are connected to a second metal member 60, and opposite sides of the first metal member 50 and the second metal member 60 are parallel, and at least one contact hole is flush with one of the opposite sides.

[0073] In this embodiment, the position of the contact hole does not need to be adjusted, and only the layout position of the first metal member 50 and the second metal member 60 is adjusted to reduce the parasitic capacitance between the first metal member 50 and the second metal member 60, and the parasitic capacitance between the metal members and the gate wiring 20.

[0074] like Figure 8 As shown, the first contact hole 30 and the second contact hole 40 are aligned in the left-right direction. The side of the first metal member 50 facing the second metal member 60 is parallel to the first direction, and the side of the second metal member 60 facing the first metal member 50 is parallel to the first direction. Since the two sides are parallel to the arrangement direction of the contact holes, all the first contact holes 30 are flush with the side of the first metal member 50 facing the second metal member 60, and all the second contact holes 40 are flush with the side of the second metal member 60 facing the first metal member 50. The spacing between the first metal member 50 and the second metal member 60 reaches the maximum value, reducing the parasitic capacitance between the first metal member 50 and the second metal member 60 and between the metal members and the gate wiring 20.

[0075] like Fig. 9 As shown, the first contact hole 30 and the second contact hole 40 are aligned in the left-right direction. The side of the first metal member 50 facing the second metal member 60 is arranged obliquely in the first direction, and the side of the second metal member 60 facing the first metal member 50 is arranged obliquely in the first direction, which can also reduce the parasitic capacitance between the first metal member 50 and the second metal member 60 and between the metal member and the gate wiring 20. Among them, the side of the first metal member 50 facing away from the second metal member 60 and the side facing the second metal member 60 are mirror-symmetrical along the first direction, and the side of the second metal member 60 facing away from the first metal member 50 and the side facing the first metal member 50 are mirror-symmetrical along the first direction. In the first direction, the widths of the first metal member 50 and the second metal member 60 are different at different locations, thereby reducing the size of the metal members.

[0076] According to the semiconductor device of the present application, a first contact hole 30 and a second contact hole 40 are provided on a silicon-on-insulator substrate 10. The first contact hole 30 and the first metal member 50 are used to lead out a source terminal (or a drain terminal), and the second contact hole 40 and the second metal member 60 are used to lead out a drain terminal (or a source terminal). By increasing the spacing between the first metal member 50 and the second metal member 60, the parasitic capacitance between the metal members and between the metal members and the gate wiring 20 can be reduced, thereby improving the device performance.

[0077] An embodiment of the present application further provides a radio frequency chip, comprising the semiconductor device according to the above. The structure of the semiconductor device can refer to the above embodiment, and this embodiment will not be described in detail here.

[0078] In this embodiment, the semiconductor device is implemented as an RF-SOI device. The RF chip can integrate low noise amplifiers (LNA), RF switches, antenna tuners, etc. The RF-SOI device can be used to manufacture the above circuits, so that each circuit has high quality, low loss, low noise and other RF performance.

[0079] According to the radio frequency chip of the present application, the semiconductor device used is less interfered by parasitic capacitance, and the performance of the chip and the device is higher.

[0080] An embodiment of the present application further provides an electronic device, comprising the radio frequency chip according to the above. The structure of the radio frequency chip can refer to the above embodiment, and this embodiment will not be described in detail here.

[0081] In this embodiment, the electronic device uses the above-mentioned radio frequency chip to implement the radio frequency function. Such electronic device can be a car, an Internet of Things device or a smart phone, etc.

[0082] According to the radio frequency chip and electronic device of the present application, the semiconductor devices used are less interfered by parasitic capacitance, and the performance of the chip and the device is higher.

[0083] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A silicon-on-insulator substrate having a top silicon layer; A gate wiring is formed on the upper surface of the top silicon layer, and defines a first region and a second region separated from each other on the upper surface of the top silicon layer; a plurality of first contact holes formed in the first region of the upper surface of the top silicon layer and arranged along a first direction; a plurality of second contact holes formed in the second region of the upper surface of the top silicon layer and arranged along the first direction; A first metal member connected to the plurality of first contact holes; A second metal member connected to the plurality of second contact holes; The two opposite sides of the first metal member and the second metal member are parallel, and at least one of the first contact holes is flush with a side of the first metal member facing the second metal member or at least one of the second contact holes is flush with a side of the second metal member facing the first metal member.

2. The semiconductor device according to claim 1, wherein: The distance between adjacent first contact holes and second contact holes is greater than a target distance, which is the distance when the first contact holes and the second contact holes are respectively located in the middle of the region and face each other along a second direction, and the second direction is perpendicular to the first direction.

3. The semiconductor device according to claim 2, characterized in that Along the first direction, the first contact holes and the second contact holes are arranged alternately.

4. The semiconductor device according to claim 3, characterized in that Along the second direction, a distance between the contact hole and a side edge of the region in which the contact hole is located is smaller than a distance between the contact hole and the gate wiring.

5. The semiconductor device according to claim 2, wherein: Along the second direction, the first contact hole and the second contact hole are arranged opposite to each other, and a first distance between the contact hole and a side edge of a region in which the contact hole is located is smaller than a second distance between the contact hole and the gate wiring.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The two opposite sides are arranged along the first direction, and each contact hole is flush with a corresponding one of the two sides.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that: The first metal piece and the second metal piece are both pieces of unequal width, and the two opposite sides form a first angle with the first direction, and the first angle is greater than 0.

8. A radio frequency chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising the radio frequency chip according to claim 8.

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