High-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, preparation method and chip

Abstract

The present application discloses a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference, a preparation method and a chip, belonging to the field of semiconductor technology. The highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference includes: a substrate; a body region, a source region and at least one first doping region are provided near the first side in the body region, and the doping type of the first doping region is opposite to that of the source region; a drift region, a drain region and at least one second doping region are provided near the first side of the drift region, and the doping type of the second doping region is opposite to that of the drain region; a gate functional layer; a first polarity structure, respectively connected to the source region, the first doping region and the gate functional layer; a second polarity structure, respectively connected to the drain region and the second doping region. The first doping region in the body region and the second doping region in the drift region form PN junctions inside the LDMOS device, respectively, to realize the integration of the SCR structure in the LDMOS, thereby adjusting the current outflow path and improving the electrostatic discharge capacity per unit area of ​​the LDMOS device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a highly reliable LDMOS electrostatic discharge device that is resistant to electromagnetic environment interference, a preparation method and a chip. Background Art

[0002] Industrial chips in key industrial fields such as electricity, rail transit, and automobiles are mostly mounted outdoors with terminals, and are very susceptible to strong transient electromagnetic interference generated by the operation of surrounding power devices such as IGBTs, as well as environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 hours a day, 7 days a week, in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of more than 15 years, which poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference.

[0003] Electrostatic discharge (ESD) is a phenomenon in which static voltage is generated between an object and its surroundings, and then discharged spontaneously in the form of current pulses. It is very common in life. Due to the huge losses that may be caused, electrostatic protection during chip production and use is a part that chip designers cannot ignore. The characteristics of static electricity are long-term accumulation, high voltage, low power, small current and short action time. The human body's own movements or contact, separation, friction or induction with other objects can generate thousands of volts or even tens of thousands of volts of static electricity. Static electricity causes serious harm in many fields. Triboelectric charging and human body static electricity are two major hazards in the electronics industry, which often cause electronic and electrical products to operate unstably or even damage.

[0004] The area of ​​a chip is positively correlated with its cost. How to discharge more ESD interference current per unit area is an important indicator of ESD competitiveness. Especially under the interference of multiple physical fields such as electromagnetic heat, it is crucial for industrial chips to discharge current, discharge ESD efficiently per unit area, and protect the entire chip. Traditional high-voltage ESD requires a larger LDMOS tube, which has a huge overall area and poor current discharge capability. Summary of the invention

[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a highly reliable LDMOS electrostatic discharge device, a preparation method and a chip that are resistant to electromagnetic environment interference, and by integrating an SCR (Silicon Controlled Rectifier) ​​structure in the LDMOS, the current outflow path is adjusted, thereby improving the electrostatic discharge capacity per unit area of ​​the LDMOS device.

[0006] In a first aspect, the present application provides a high-reliability LDMOS electrostatic discharge device that is resistant to electromagnetic environment interference, including:

[0007] a substrate having opposing first and second sides;

[0008] A body region is formed in the substrate and close to the first side, wherein a source region and at least one first doping region are provided in the body region close to the first side, and the doping type of the first doping region is opposite to the doping type of the source region;

[0009] A drift region is formed in the substrate and close to the first side, wherein the drift region is provided with a drain region and at least one second doping region close to the first side, and the doping type of the second doping region is opposite to the doping type of the drain region;

[0010] A gate functional layer, located on the first side of the substrate, the gate functional layer at least partially covers the body region and at least partially covers the drift region 30;

[0011] A first polarity structure is located on the first side of the substrate, and the first polarity structure is respectively connected to the source region, the first doping region and the gate functional layer;

[0012] The second polarity structure is located on the first side of the substrate, and the second polarity structure is connected to the drain region and the second doping region respectively.

[0013] According to the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference of the present application, the first doped region in the body region and the second doped region in the drift region respectively form PN junctions inside the LDMOS device, thereby integrating the SCR structure in the LDMOS, thereby adjusting the current outflow path and improving the electrostatic discharge capability per unit area of ​​the LDMOS device.

[0014] According to an embodiment of the present application, a first isolation region is provided between the source region and the adjacent first doped region, and a second isolation region is provided between the drain region and the adjacent second doped region.

[0015] According to an embodiment of the present application, the depth of the first isolation region is greater than the depth of the source region and greater than the depth of the first doping region, and the depth of the second isolation region is greater than the depth of the source region and greater than the depth of the second doping region.

[0016] According to an embodiment of the present application, the number of the first doped region is one, the number of the second doped region is one, the first doped region is located on the side of the source region close to the drift region, and the second doped region is located on the side of the drain region close to the body region.

[0017] According to an embodiment of the present application, a first distance L between the first doped region and an edge of the body region on a side close to the drift region satisfies: 0.18 um≤L≤20 um.

[0018] According to one embodiment of the present application, the first distance L satisfies: 0.6um≤L≤0.8um.

[0019] According to an embodiment of the present application, a second distance D between the second doping region and an edge of the drift region close to the body region satisfies: 0.18um≤D≤20um.

[0020] According to one embodiment of the present application, the second distance D satisfies: 0.7um≤L≤0.9um.

[0021] According to an embodiment of the present application, a silicon local oxidation isolation region is provided between the second doped region and an edge of the drift region close to the body region, and the silicon local oxidation isolation region is arranged adjacent to the edge of the drift region and the second doped region respectively.

[0022] According to one embodiment of the present application, the substrate is a high voltage N-type doped layer, the body region is a P-type doped region, and the drift region is an N-type reduced surface field region;

[0023] A P-type reduced surface field region is also provided in the substrate. The P-type reduced surface field region is located on a side of the body region and the drift region away from the first side. The P-type reduced surface field region is arranged adjacent to the body region and is spaced apart from the drift region.

[0024] According to one embodiment of the present application, the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference further includes:

[0025] A protective layer, located on the first side of the substrate, the protective layer covers the body region, the drift region and the gate functional layer, and has an opening, wherein the opening exposes the source region, the first doped region, the gate functional layer, the drain region and the second doped region;

[0026] Polar structures include:

[0027] A contact column is located in the opening and connected to the source region, the first doped region, the gate functional layer, the drain region or the second doped region;

[0028] Electrode, connected to the contact post.

[0029] In a second aspect, the present application provides a method for preparing a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, comprising:

[0030] providing a substrate;

[0031] doping the first side of the substrate to form a body region and a drift region;

[0032] doping the body region to form a source region and at least one first doping region, wherein the doping type of the first doping region is opposite to the doping type of the source region;

[0033] doping the drift region to form a drain region and at least one second doping region, wherein the doping type of the second doping region is opposite to the doping type of the drain region;

[0034] forming a gate functional layer on the first side of the substrate, wherein the gate functional layer at least partially covers the body region and at least partially covers the drift region;

[0035] A first polarity structure and a second polarity structure are formed on the first side of the substrate, the first polarity structure is respectively connected to the source region, the first doping region and the gate functional layer, and the second polarity structure is respectively connected to the drain region and the second doping region.

[0036] According to the preparation method of the present application, a first doped region is formed in the body region of a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, and a second doped region is formed in the drift region, so as to form PN junctions inside the LDMOS device respectively, thereby integrating an SCR (Silicon Controlled Rectifier) ​​structure in the LDMOS, thereby adjusting the current outflow path and improving the electrostatic discharge capability per unit area of ​​the LDMOS device.

[0037] According to one embodiment of the present application, after doping the body region, the method further includes:

[0038] forming a first isolation region between the source region and a first doped region adjacent to the source region;

[0039] After doping the drift region, it also includes:

[0040] A second isolation region is formed between the drain region and a second doping region adjacent to the drain region.

[0041] According to one embodiment of the present application, a first polarity structure and a second polarity structure are formed on a first side of a substrate, including:

[0042] forming a protection layer on the first side of the substrate, wherein the protection layer covers the body region, the drift region and the gate functional layer;

[0043] Etching the protective layer to form an opening, wherein the opening exposes the source region, the first doped region, the gate functional layer, the drain region, and the second doped region;

[0044] Depositing a first contact column in the opening, the first contact column and the source region, the first doped region and the gate functional layer;

[0045] Depositing a second contact column in the opening, wherein the second contact column is connected to the drain region or the second doped region;

[0046] A first electrode and a second electrode are deposited on a side of the protective layer away from the substrate. The first electrode is connected to the first contact column to form a first polarity structure, and the second electrode is connected to the second contact column to form a second polarity structure.

[0047] In a third aspect, the present application provides a chip, including the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference described above, or the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference prepared according to the above-mentioned preparation method.

[0048] According to the chip of the present application, a high-reliability LDMOS electrostatic discharge device with stronger anti-static ability and resistance to electromagnetic environment interference is adopted, and the chip reliability is higher.

[0049] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0051] Figure 1 This is one of the structural schematic diagrams of a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference provided in an embodiment of the present application;

[0052] Figure 2 This is the second structural schematic diagram of the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference provided in the embodiment of the present application;

[0053] Figure 3 : is an equivalent circuit diagram of a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference provided in an embodiment of the present application;

[0054] Figure 4 It is a flow chart of a method for preparing a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference provided in an embodiment of the present application.

[0055] Reference numerals:

[0056] Substrate 10, body region 20, source region 21, first doped region 22, first isolation region 23, drift region 30, drain region 31, second doped region 32, second isolation region 33, gate functional layer 40, gate dielectric layer 41, gate electrode layer 42, silicon local oxidation isolation region 50, protective layer 60, contact pillar 70, electrode 80, first electrode 81, second electrode 82. DETAILED DESCRIPTION

[0057] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0058] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0060] In related technologies, high-voltage ESD devices are usually designed with an Active Clamp structure. Since a larger LDMOS tube is required, as well as circuits such as RC triggers, the overall area is huge, and the overcurrent capability per unit area is usually below 0.2V / um^2, with poor current discharge capability. NPN and PNP structures are used for ESD protection, which requires a transistor structure that can withstand high voltage. However, not all process platforms will develop high-voltage NPN and PNP, especially when analog chips only require LDMOS, NDEMOS, and PDEMOS, and power isolation chips do not require high-voltage transistors, so the corresponding process platforms will not develop high-voltage transistors. How to use existing high-voltage devices such as LDMOS to design a high-efficiency ESD is a big challenge.

[0061] The present application proposes a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, a preparation method and a chip. By forming a first doping region 22 in a body region 20 of the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, and forming a second doping region 32 in a drift region 30, PN junctions are formed inside the LDMOS device respectively, and an SCR (Silicon Controlled Rectifier) ​​structure is integrated in the LDMOS, thereby adjusting the current outflow path, improving the electrostatic discharge capability per unit area of ​​the LDMOS device, and the overcurrent capability per unit area is usually above 3V / um^2, and the chip also has higher reliability.

[0062] It should be noted that the high-reliability LDMOS electrostatic discharge device, preparation method and chip resistant to electromagnetic environment interference proposed in this application can be applied to the BCD (Bipolar-CMOS-DMOS) process. The chip prepared under the BCD process simultaneously manufactures bipolar devices, CMOS devices and DMOS devices on the same chip, and usually only requires LDMOS, NDEMOS, PDEMOS and other structures. The NBL buried layer is not designed in the BCD process, and the electrostatic discharge capability is required to be high. This application realizes electrostatic discharge under high voltage by constructing an SCR structure in the LDMOS.

[0063] Reference Figure 1 and Figure 2 , Figure 1 The first high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference is shown. Figure 2 A second high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference is shown. An embodiment of the present application provides a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference.

[0064] It should be noted that Figure 1 and Figure 2The shapes and sizes of the regions shown in the figure are only examples and do not constitute a limitation on the electromagnetic environment interference resistant high-reliability LDMOS electrostatic discharge device of the embodiment of the present application. Its actual size and shape can be set according to requirements, and this embodiment does not limit this.

[0065] In the present embodiment, the electromagnetic environment interference resistant high-reliability LDMOS electrostatic discharge device includes a substrate 10 having a first side and a second side opposite to each other; a body region 20 formed in the substrate 10 and close to the first side, a source region 21 and at least one first doping region 22 are provided in the body region 20 close to the first side, and the doping type of the first doping region 22 is opposite to the doping type of the source region 21; a drift region 30 is formed in the substrate 10 and close to the first side, a drain region 31 and at least one second doping region 32 are provided in the drift region 30 close to the first side, and the doping type of the second doping region 32 is opposite to the doping type of the drain region 31; a gate functional layer 40 is located on the first side of the substrate 10, the gate functional layer 40 at least partially covers the body region 20, and at least partially covers the drift region 30; a first polarity structure is located on the first side of the substrate 10, and the first polarity structure is connected to the source region 21, the first doping region 22 and the gate functional layer 40 respectively; a second polarity structure is located on the first side of the substrate 10, and the second polarity structure is connected to the drain region 31 and the second doping region 32 respectively.

[0066] The substrate 10 can have P-type doping or N-type doping, the doping type of the body region 20 is opposite to the doping type of the substrate 10, the doping type of the source region 21 is the same as the doping type of the body region 20, the doping type of the drift region 30 is the same as the doping type of the substrate 10, and the doping type of the drain region 31 is the same as the doping type of the drift region 30.

[0067] exist Figure 1 and Figure 2 In the figure, the first side of the substrate 10 may refer to the upper side of the substrate 10 in the figure, and the second side of the substrate 10 may refer to the lower side of the substrate 10 in the figure. The body region 20, the source region 21, the first doping region 22, the drift region 30, the drain region 31, and the second doping region 32 are all formed on the upper side of the substrate 10, and the surfaces are all exposed on the upper surface of the substrate 10.

[0068] As an example, the substrate 10 may be N-type doped, the body region 20 and the source region 21 may be P-type doped, and the drift region 30 and the drain region 31 may be N-type doped. The doping concentration of the source region 21 may be greater than the doping concentration of the body region 20, the body region 20 may be a P-well, and the source region 21 may be a P+ well. The doping concentration of the drift region 30 is less than the doping concentration of the substrate 10, the doping concentration of the drain region 31 may be greater than the doping concentration of the drift region 30, the drift region 30 may be an N-well, and the drain region 31 may be an N+ well.

[0069] In this example, the doping concentration of the first doping region 22 may be equal to the doping concentration of the source region 21, and the doping concentration of the second doping region 32 may be equal to the doping concentration of the drain region 31. That is, the first doping region 22 is an N+ well, and the second doping region 32 is a P+ well.

[0070] Combination Figure 3 , Figure 3 The equivalent circuit diagram of a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference is shown. The drain of the LDMOS device is connected to VCC, and the source and gate are connected to GND. When the VCC high voltage is subjected to a positive ESD voltage reaching the trigger Vt1 relative to GND, the current passes through the drain region 31 (N+) and the drift region 30 (NRF), passes through the substrate 10 (HNW), and causes the drift region 30 (NRF) and the body region 20 (PB) to be broken down by the high voltage. Thus, the current flows from the drain region 31 (N+)--->drift region 30 (NRF)--->substrate 10 (HNW)--->body region 20 (PB)--->source region 21 (P+). Since the drain region 31 (N+) and the second doping region 32 (P+) are connected / short-circuited, a voltage difference is formed from the second doping region 32 (P+) to the drift region 30 (NRF), and the PN junction is turned on, with a forward current. The second doping region 32 (P+), the drift region 30 (NRF) and the body region 20 (PB) form a PNP triode structure. There is a current from the emitter to the base, so it is amplified by the triode PNP Beta, so a discharge current is formed from VCC to the body region 20 (PB) to the source region 21 (P+), which is the first current discharge path. At the same time, there is also a voltage drop between the first doping region 22 (N+) and 20 (PB), and an NPN triode structure is also formed between the first doping region 22 (N+), the body region 20 (PB) and the drift region 30 (NRF). There is a current from the emitter to the base, so it is amplified by the triode NPN Beta, so a discharge current is formed from VCC to the drift region 30 (NRF) to the body region 20 (PB), to the first doping region 22 (N+), which is the second current discharge path. When VCC is subjected to a negative ESD voltage relative to GND, the diode from the body region 20 (PB) to the drift region 30 (NRF) is directly turned on, and the ESD current can be discharged through the parasitic diode.

[0071] Reference Figure 2 In some embodiments, the substrate 10 may be a high voltage N-type doped layer (HNW), the body region 20 may be a P-type doped region (PB), and the drift region 30 may be an N-type reduced surface field region (NRF); a P-type reduced surface field region (PRF) 90 is further provided in the substrate 10, and the P-type reduced surface field region 90 is located on a side of the body region 20 and the drift region 30 away from the first side, the P-type reduced surface field region 90 is arranged adjacent to the body region 20, and the P-type reduced surface field region 90 is arranged spaced apart from the drift region 30.

[0072] In the BCD process, LDMOS electrostatic discharge devices with high reliability and resistance to electromagnetic environment interference are often used to prepare high-voltage electrostatic protection devices, and their breakdown voltage usually reaches about 4.5KV. The materials of LDMOS electrostatic discharge devices with high reliability and resistance to electromagnetic environment interference are selected to be high-voltage resistant materials to avoid damage.

[0073] The gate functional layer 40 includes a stacked gate dielectric layer 41 and a gate electrode layer 42. The gate dielectric layer 41 is located on a first side of the substrate 10, and the gate electrode layer 42 is located on a side of the gate dielectric layer 41 away from the substrate 10. The orthographic projection of the gate dielectric layer 41 on the substrate 10 partially overlaps with the body region 20, and partially overlaps with the drift region 30. The orthographic projection of the gate electrode layer 42 on the substrate 10 is located within the orthographic projection of the gate dielectric layer 41 on the substrate 10, and the orthographic projection of the gate electrode layer 42 on the substrate 10 partially overlaps with the body region 20, and partially overlaps with the drift region 30.

[0074] The gate dielectric layer 41 may be made of an insulating material, such as silicon dioxide, etc. The gate electrode layer 42 may be made of a conductive material, such as metal, etc.

[0075] In some embodiments, there is one first doping region 22 and one second doping region 32 . The first doping region 22 is located on the side of the source region close to the drift region 30 , and the second doping region 32 is located on the side of the drain region 31 close to the body region 20 .

[0076] The number of the first doping region 22 and the number of the second doping region 32 are both one. By reducing the number of well regions forming the SCR structure, the space occupied in the LDMOS device can be reduced, and the volume of the LDMOS device can be avoided from being increased, thereby improving the current capacity per unit area.

[0077] In the preparation of the LDMOS device, the source region 21 and the drain region 31 are on both sides of the device, so the first doped region 22 and the second doped region 32 are arranged between the source region 21 and the drain region 31, which can also avoid increasing the volume of the LDMOS device and improve the current capacity per unit area.

[0078] In some embodiments, a first isolation region 23 is disposed between the source region 21 and the adjacent first doping region 22 , and a second isolation region 33 is disposed between the drain region 31 and the adjacent second doping region 32 .

[0079] The first isolation region 23 and the second isolation region 33 may be made of insulating materials, such as silicon dioxide.

[0080] A PN junction is formed between the source region 21 and the first doping region 22 and between the drain region 31 and the second doping region 32. The breakdown voltage between the source region 21 and the first doping region 22 can be increased by adding the first isolation region 23, and the breakdown voltage between the drain region 31 and the second doping region 32 can be increased by adding the second isolation region 33. Thus, the withstand voltage capability of the LDMOS device can be improved.

[0081] In this embodiment, the source region 21 , the first isolation region 23 and the first doping region 22 adjacent to the source region 21 are arranged adjacent to each other, and the drain region 31 , the second isolation region 33 and the second doping region 32 adjacent to the source region 21 are arranged adjacent to each other.

[0082] It can be understood that the close arrangement means edge bonding. That is, the side of the first isolation region 23 close to the source region 21 is bonded to the source region 21, and the side of the first isolation region 23 close to the first doping region 22 is bonded to the first doping region 22; the side of the second isolation region 33 close to the drain region 31 is bonded to the drain region 31, and the side of the second isolation region 33 close to the second doping region 32 is bonded to the second doping region 32. In the case of bonding, the isolation effect of the isolation region is better, and the structure can be made more compact, which improves the discharge capacity per unit area of ​​the LDMOS device.

[0083] In some embodiments, the depth of the first isolation region 23 is greater than the depth of the source region 21 and greater than the depth of the first doping region 22 , and the depth of the second isolation region 33 is greater than the depth of the drain region 31 and greater than the depth of the second doping region 32 .

[0084] Increasing the depth of the first isolation region 23 can further increase the breakdown voltage between the source region 21 and the first doped region 22 , and increasing the depth of the second isolation region 33 can further increase the breakdown voltage between the drain region 31 and the second doped region 32 , thereby further improving the withstand voltage capability of the LDMOS device.

[0085] In some embodiments, a first distance L between the first doping region 22 and an edge of the body region 20 close to the drift region 30 satisfies: 0.18 um≤L≤20 um.

[0086] The first doping region 22 is spaced apart from the edge of the body region 20 close to the drift region 30 to increase the breakdown voltage of the entire device.

[0087] In some embodiments, the first spacing L satisfies: 0.6um≤L≤0.8um. ​​If the first spacing L is too small, the breakdown voltage of the entire SCR structure will be reduced; if the first spacing L is too large, the gain of the parasitic NPN transistor will decrease, affecting the discharge effect. Within the range of 0.6um≤L≤0.8um, the SCR structure can have good compatibility with LDMOS in the BCD process and can be produced with high reliability; at the same time, a smaller size is adopted, which increases the overcurrent capacity per unit area.

[0088] In some embodiments, a second distance D between the second doping region 32 and an edge of the drift region 30 close to the body region 20 satisfies: 0.18 um≤D≤20 um.

[0089] The second doping region 32 is spaced apart from the edge of the drift region 30 close to the body region 20 , so as to increase the breakdown voltage of the entire device.

[0090] In some embodiments, the second spacing D satisfies: 0.7um≤L≤0.9um. If the second spacing D is too small, the gate dielectric layer 41 will be easily broken down; if the second spacing D is too large, the gain Beta of the parasitic PNP tube will be affected, and the ESD electrostatic discharge effect will be reduced. Within the range of 0.7um≤L≤0.9um, the SCR structure can have good compatibility with LDMOS in the BCD process and can be produced with high reliability; at the same time, a smaller size is adopted, which increases the overcurrent capacity per unit area.

[0091] In some embodiments, a silicon local oxidation isolation region 50 is provided between the second doped region 32 and an edge of the drift region 30 close to the body region 20 , and the silicon local oxidation isolation region 50 is arranged adjacent to the edge of the drift region 30 and the second doped region 32 , respectively.

[0092] It can be understood that the close arrangement means edge alignment, that is, the edge of the silicon local oxidation isolation region 50 close to the drift region 30 close to the body region 20 is aligned, and the side of the silicon local oxidation isolation region 50 close to the second doping region 32 is aligned with the second doping region 32. Increasing the oxide layer thickness increases the gate breakdown voltage.

[0093] In some embodiments, the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference also includes a protective layer 60, which is located on the first side of the substrate 10, and the protective layer 60 covers the body region 20, the drift region 30 and the gate functional layer 40. The protective layer 60 has an opening, and the opening exposes the source region 21, the first doped region 22, the gate functional layer 40, the drain region 31 and the second doped region 32; the polarity structure includes a contact column 70, which is located in the opening and connected to the source region 21, the first doped region 22, the gate functional layer 40, the drain region 31 or the second doped region 32; the electrode 80 is connected to the contact column 70.

[0094] The material of the protection layer 60 may be silicon nitride or silicon dioxide, etc., which mainly plays the role of protecting the LDMOS device. The material of the contact pillar 70 and the electrode 80 may be a conductive material, such as metal.

[0095] The LDMOS device used as an electrostatic discharge device needs to lead out the anode and cathode. The source region 21, the first doped region 22, the gate functional layer 40, the drain region 31 and the second doped region 32 are all connected to a contact column 70, and the contact column 70 connected to the source region 21, the first doped region 22 and the gate functional layer 40 is connected to the first electrode 81 to form a first polarity structure as a cathode; the contact column 70 connected to the drain region 31 and the second doped region 32 is connected to the second electrode 82 to form a second polarity structure as an anode.

[0096] Reference Figure 4 , Figure 4 The process of a method for preparing a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference is shown. An embodiment of the present application also provides a method for preparing a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference.

[0097] In this embodiment, the method for preparing the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference includes step 10, step 20, step 30, step 40, step 50 and step 60.

[0098] Step 10: providing a substrate 10;

[0099] Step 20: doping the first side of the substrate 10 to form a body region 20 and a drift region 30;

[0100] Step 30: doping the body region 20 to form a source region 21 and at least one first doping region 22 , wherein the doping type of the first doping region 22 is opposite to the doping type of the source region 21 ;

[0101] Step 40: doping the drift region 30 to form a drain region 31 and at least one second doping region 32 , wherein the doping type of the second doping region 32 is opposite to the doping type of the drain region 31 ;

[0102] Step 50: forming a gate functional layer 40 on the first side of the substrate 10 , wherein the gate functional layer 40 at least partially covers the body region 20 and at least partially covers the drift region 30 ;

[0103] Step 60: forming a first polarity structure and a second polarity structure on the first side of the substrate 10 , wherein the first polarity structure is respectively connected to the source region 21 , the first doping region 22 and the gate functional layer 40 , and the second polarity structure is respectively connected to the drain region 31 and the second doping region 32 .

[0104] The structure of the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference prepared according to the method for preparing the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference according to the embodiment of the present application can continue to refer to Figure 1 and Figure 2 .

[0105] The method for preparing the electromagnetic environment interference resistant high-reliability LDMOS electrostatic discharge device of the embodiment of the present application can be applied to the BCD process, and the substrate 10 can be a wafer in the BCD process. The substrate 10 can have P-type doping or N-type doping; for example, the substrate 10 can be a high-voltage N-type doping layer (HNW).

[0106] As an example, the substrate 10 may be N-type doped. The first side of the substrate 10 is doped with P-type elements and N-type elements, respectively, to form a body region 20 with P-type doping and a drift region 30 with N-type doping. The P-type elements include boron atoms, etc., and the N-type elements include phosphorus atoms, etc.

[0107] Continue to dope the body region 20 and the drift region 30 to obtain the source region 21, the first doping region 22, the drain region 31 and the second doping region 32. The source region 21 and the second doping region 32 have the same doping type, so they can be prepared at the same time. The drain region 31 and the first doping region 22 have the same doping type, so they can be prepared at the same time.

[0108] The gate functional layer 40 includes a stacked gate dielectric layer 41 and a gate electrode layer 42. The gate dielectric layer 41 is located on the first side of the substrate 10, and the gate electrode layer 42 is located on the side of the gate dielectric layer 41 away from the substrate 10. The stacked gate dielectric layer 41 and the gate electrode layer 42 are formed by depositing the gate dielectric material and the gate material in sequence, and then etching. The gate dielectric material can be an insulating material, such as silicon dioxide, etc. The gate material is a conductive material, such as a metal, etc.

[0109] The LDMOS device used as an electrostatic discharge device needs to lead out the anode and cathode. The first polarity structure connects the source region 21, the first doping region 22 and the gate functional layer 40, and can be used as a cathode. The second polarity structure connects the drain region 31 and the second doping region 32, and can be used as an anode.

[0110] As an example, the specific steps of step 60 may include: forming a protective layer 60 on the first side of the substrate 10, the protective layer 60 covering the body region 20, the drift region 30 and the gate functional layer 40; etching the protective layer 60 to form an opening, the opening exposing the source region 21, the first doping region 22, the gate functional layer 40, the drain region 31 and the second doping region 32; depositing a first contact column in the opening, the first contact column being connected to the source region 21, the first doping region 22, and the gate functional layer 40; depositing a second contact column in the opening, the second contact column being connected to the drain region 31 or the second doping region 32; depositing a first electrode 81 and a second electrode 82 on a side of the protective layer 60 away from the substrate 10, the first electrode 81 being connected to the first contact column to form a first polarity structure, and the second electrode 82 being connected to the second contact column to form a second polarity structure.

[0111] The material of the protection layer 60 may be silicon nitride or silicon dioxide, etc., which mainly plays the role of protecting the LDMOS device. The material of the contact pillar 70 and the electrode 80 may be a conductive material, such as metal, etc. The first polarity structure serves as a cathode, and the second polarity structure serves as an anode.

[0112] According to the preparation method of the present application, a first doped region 22 is formed in the body region 20 of the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, and a second doped region 32 is formed in the drift region to form PN junctions inside the LDMOS device, respectively, so as to integrate an SCR (Silicon Controlled Rectifier) ​​structure in the LDMOS, thereby adjusting the current outflow path and improving the electrostatic discharge capability per unit area of ​​the LDMOS device.

[0113] In some embodiments, after doping the body region 20 , the first isolation region 23 is formed between the source region 21 and the first doped region 22 adjacent to the source region 21 ; after doping the drift region 30 , the second isolation region 33 is formed between the drain region 31 and the second doped region 32 adjacent to the drain region 31 .

[0114] The first isolation region 23 and the second isolation region 33 may be made of insulating materials, such as silicon dioxide.

[0115] In this example, the first isolation region 23 and the second isolation region 33 can be formed simultaneously. The body region 20 and the drift region 30 are etched to form a first trench between the source region 21 and the first doping region 22 adjacent to the source region 21, and a second trench is formed between the drain region 31 and the second doping region 32 adjacent to the drain region 31; and then an isolation material is deposited into the first trench and the second trench to form the first isolation region 23 and the second isolation region 33.

[0116] A PN junction is formed between the source region 21 and the first doping region 22 and between the drain region 31 and the second doping region 32. The breakdown voltage between the source region 21 and the first doping region 22 can be increased by adding the first isolation region 23, and the breakdown voltage between the drain region 31 and the second doping region 32 can be increased by adding the second isolation region 33. Thus, the withstand voltage capability of the LDMOS device can be improved.

[0117] In a third aspect, the present application provides a chip, including a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference according to the aforementioned electromagnetic environment interference resistance, or a high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference prepared according to the aforementioned preparation method. The description of the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference and its preparation method can refer to the aforementioned embodiment, and this implementation will not be repeated here.

[0118] According to the chip of the present application, a highly reliable LDMOS electrostatic discharge device with stronger anti-static ability and anti-electromagnetic environment interference is used, and the chip reliability is higher.

[0119] In this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0120] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference, characterized in that: Applied to a high-voltage device prepared under a BCD process, the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference does not have an NBL buried layer, and includes: a substrate having opposing first and second sides; a body region formed in the substrate and close to the first side, wherein a source region and a first doping region are provided in the body region close to the first side, wherein the first doping region is located on a side of the source region close to the drift region, and the doping type of the first doping region is opposite to the doping type of the source region; a drift region formed in the substrate and close to the first side, wherein the drift region is provided with a drain region and a second doped region close to the first side, the second doped region is located on a side of the drain region close to the body region, the doping type of the second doped region is opposite to the doping type of the drain region, and the depth of the body region is greater than the depth of the drift region; a gate functional layer, located on the first side of the substrate, the gate functional layer at least partially covering the body region and at least partially covering the drift region; A first polarity structure, located on the first side of the substrate, the first polarity structure being connected to the source region, the first doping region and the gate functional layer respectively; A second polarity structure, located on the first side of the substrate, the second polarity structure being connected to the drain region and the second doping region respectively; The substrate is a high-voltage N-type doped layer, the body region is a P-type doped region, and the drift region is an N-type reduced surface field region; a P-type reduced surface field region is further provided in the substrate, the P-type reduced surface field region is located on a side of the body region and the drift region away from the first side, the P-type reduced surface field region is arranged closely to the body region, and the P-type reduced surface field region is arranged spaced apart from the drift region; A first isolation region is provided between the source region and the first doped region, and two sides of the first isolation region are respectively attached to the source region and the first doped region; a second isolation region is provided between the drain region and the second doped region, and two sides of the second isolation region are respectively attached to the drain region and the second doped region; the first isolation region and the second isolation region are formed in the substrate; surfaces of the first isolation region and the second isolation region on one side close to the first polarity structure and the second polarity structure are flush with a surface of the substrate on one side close to the first polarity structure and the second polarity structure; a depth of the first isolation region is greater than a depth of the source region and greater than a depth of the first doped region; a depth of the second isolation region is greater than a depth of the drain region and greater than a depth of the second doped region; A silicon local oxidation isolation region is provided between the second doping region and an edge of the drift region close to the body region, and the silicon local oxidation isolation region is arranged adjacent to the edge of the drift region and the second doping region respectively; the adjacent arrangement is an edge-fitting arrangement; A first distance L between the first doped region and an edge of the body region close to the drift region satisfies: 0.6 μm≤L≤0.8 μm; A second distance D between the second doping region and an edge of the drift region close to the body region satisfies: 0.7 μm≤D≤0.9 μm.

2. The high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference according to claim 1 is characterized in that: The high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference also includes: a protective layer, located on the first side of the substrate, the protective layer covering the body region, the drift region and the gate functional layer, the protective layer having an opening, the opening exposing the source region, the first doped region, the gate functional layer, the drain region and the second doped region; The first polarity structure and the second polarity structure include: a contact column, located in the opening and connected to the source region, the first doped region, the gate functional layer, the drain region or the second doped region; An electrode is connected to the contact post.

3. A method for preparing a highly reliable LDMOS electrostatic discharge device resistant to electromagnetic environment interference, characterized in that: In the preparation of high-voltage devices used in the BCD process, the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference does not have an NBL buried layer, and the preparation method includes: Providing a substrate, wherein the substrate is a high voltage N-type doped layer; Doping the first side of the substrate to form a body region and a drift region, wherein the body region is a P-type doped region and the drift region is an N-type reduced surface field region; doping the body region to form a source region and a first doping region, wherein the first doping region is located on a side of the source region close to the drift region, and the doping type of the first doping region is opposite to the doping type of the source region; doping the drift region to form a drain region and a second doped region, wherein the second doped region is located on a side of the drain region close to the body region, the doping type of the second doped region is opposite to the doping type of the drain region, and the depth of the body region is greater than the depth of the drift region; forming a silicon local oxidation isolation region between the second doping region and an edge of the drift region close to the body region, wherein the silicon local oxidation isolation region is arranged adjacent to the edge of the drift region and the second doping region respectively; forming a gate functional layer on the first side of the substrate, wherein the gate functional layer at least partially covers the body region and at least partially covers the drift region; forming a first polarity structure and a second polarity structure on the first side of the substrate, wherein the first polarity structure is respectively connected to the source region, the first doped region and the gate functional layer, and the second polarity structure is respectively connected to the drain region and the second doped region; wherein a P-type reduced surface field region is further provided in the substrate, the P-type reduced surface field region is located on a side of the body region and the drift region away from the first side, the P-type reduced surface field region is arranged closely to the body region, and the P-type reduced surface field region is arranged spaced apart from the drift region; the closely arranged arrangement is an edge-fitting arrangement; After doping the body region, the method further comprises: A first isolation region is formed between the source region and the first doped region adjacent to the source region, wherein two sides of the first isolation region are respectively in contact with the source region and the first doped region, and a depth of the first isolation region is greater than a depth of the source region and greater than a depth of the first doped region; After doping the drift region, the method further includes: A second isolation region is formed between the drain region and the second doped region adjacent to the drain region, wherein two sides of the second isolation region are respectively in contact with the drain region and the second doped region, and a depth of the second isolation region is greater than a depth of the drain region and greater than a depth of the second doped region; The first isolation region and the second isolation region are formed in the substrate, and surfaces of the first isolation region and the second isolation region close to the first polarity structure and the second polarity structure are flush with a surface of the substrate close to the first polarity structure and the second polarity structure; A first distance L between the first doping region and an edge of the body region close to the drift region satisfies: 0.6 μm≤L≤0.8 μm; A second distance D between the second doping region and an edge of the drift region close to the body region satisfies: 0.7 μm≤L≤0.9 μm.

4. The preparation method according to claim 3, characterized in that: The forming of a first polarity structure and a second polarity structure on a first side of the substrate comprises: forming a protection layer on the first side of the substrate, the protection layer covering the body region, the drift region and the gate functional layer; Etching the protective layer to form an opening, wherein the opening exposes the source region, the first doped region, the gate functional layer, the drain region, and the second doped region; Depositing a first contact column in the opening, wherein the first contact column is connected to the source region, the first doped region and the gate functional layer; Depositing a second contact column in the opening, wherein the second contact column is connected to the drain region and the second doped region; A first electrode and a second electrode are deposited on a side of the protective layer away from the substrate, the first electrode is connected to the first contact column to form a first polarity structure, and the second electrode is connected to the second contact column to form a second polarity structure.

5. A chip, characterized in that: It comprises the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference according to claim 1 or 2, or the high-reliability LDMOS electrostatic discharge device resistant to electromagnetic environment interference prepared by the preparation method according to claim 3 or 4.

Images