Column-level composite analog-to-digital conversion circuit, analog-to-digital converter and electronic equipment

Abstract

The present invention provides a column-level composite analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device, and relates to the field of integrated circuits. Each sampling unit is electrically connected to a column in an array in a one-to-one correspondence, and the sampling unit is electrically connected to a successive approximation analog-to-digital converter through a flash analog-to-digital converter. One end of each capacitor in an 8-bit capacitor array is electrically connected to a flash analog-to-digital converter through a control switch, and the other end is electrically connected to an input end of a SAR comparator; the output end of the SAR comparator is electrically connected to an input end of a logic unit; the output end of the logic unit is electrically connected to a control switch, and outputs a digital quantity corresponding to an analog quantity sampled by a target sampling unit. The present invention ensures the accuracy of a flash analog-to-digital converter through a capacitor array. Since the SARADC formed by the capacitor array itself does not need to be calibrated, it will not cause SARADC quantization errors, thereby ensuring high precision of the quantization results, and is more conducive to application and implementation in large-scale array structures.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a column-level composite analog-to-digital conversion circuit, an analog-to-digital converter and electronic equipment. Background Art

[0002] At present, infrared thermal imagers are widely used in thermal imaging fields such as medical imaging, surveillance, and night vision. In recent years, readout circuits (ROICs) with on-chip analog-to-digital converters (ADCs) have been widely used due to their better noise performance and reduced system complexity, and they have shorter analog signal paths compared to traditional analog readouts.

[0003] With the development of science and technology, the readout circuit of the on-chip analog-to-digital converter has a larger array structure while being miniaturized. In general, when using column-level analog-to-digital conversion, traditional large-scale array readout circuits often use single-slope analog-to-digital conversion circuits, but single-slope analog-to-digital conversion often means that low power consumption and high precision are incompatible. The architecture that uses single-slope analog-to-digital conversion combined with other structures requires a calibration mechanism. However, due to the limitation of the layout area, especially the need for miniaturization, large-scale array circuits cannot implement a calibration mechanism, which will lead to errors in the quantization results.

[0004] Therefore, there is an urgent need to propose a large-scale array readout circuit that is more conducive to application and implementation in large-scale array structures and has high precision. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a column-level composite analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device that solve the above problems or partially solve the above problems.

[0006] A first aspect of an embodiment of the present invention provides a column-level composite analog-to-digital conversion circuit, which is applied to a large-scale array readout circuit. The column-level composite analog-to-digital conversion circuit includes: a flash analog-to-digital converter, a plurality of sampling units, and a plurality of successive approximation analog-to-digital converters;

[0007] Each sampling unit in the plurality of sampling units is electrically connected to a column in the array in a one-to-one correspondence, and the number of the sampling units is the same as the number of columns in the array;

[0008] The plurality of sampling units are electrically connected to the plurality of successive approximation analog-to-digital converters through the flash analog-to-digital converters, wherein one sampling unit corresponds to one successive approximation analog-to-digital converter, and the number of the successive approximation analog-to-digital converters is the same as the number of columns;

[0009] Each successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit;

[0010] One end of each capacitor in the 8-bit capacitor array is electrically connected to the flash analog-to-digital converter through a control switch, and the other end is electrically connected to the input end of the SAR comparator;

[0011] The output terminal of the SAR comparator is electrically connected to the input terminal of the logic unit;

[0012] The output end of the logic unit is electrically connected to the control switch, and outputs a digital quantity corresponding to an analog quantity sampled by a target sampling unit, wherein the target sampling unit is a sampling unit corresponding to a successive approximation analog-to-digital converter.

[0013] Optionally, the flash analog-to-digital converter is configured to generate a high signal and a low signal corresponding to each sampling unit based on the analog quantity sampled by each sampling unit and the maximum value and the minimum value of the preset voltage signal, and transmit the high signal and the low signal to the successive approximation analog-to-digital converter corresponding to each sampling unit.

[0014] Optionally, the flash analog-to-digital converter comprises: a plurality of unit resistors, a plurality of unit comparators, and a digital-to-analog conversion unit;

[0015] A plurality of the unit resistors form a resistor string, wherein the second end of each unit resistor is electrically connected to an inverting end of a unit comparator and to the first end of the unit resistor connected in series with itself, wherein the first end of the unit resistor at the head end of the resistor string receives the maximum value of the preset voltage signal, and the second end of the unit resistor at the tail end of the resistor string receives the minimum value of the preset voltage signal;

[0016] The non-inverting terminal of each unit comparator receives an analog quantity sampled by a sampling unit;

[0017] The output terminals of the plurality of unit comparators are electrically connected to the digital-to-analog conversion unit;

[0018] The digital-to-analog conversion unit generates a high signal and a low signal corresponding to each sampling unit, and transmits the high signal and the low signal to a successive approximation analog-to-digital converter corresponding to each sampling unit;

[0019] The number of the plurality of unit resistors and the number of the plurality of unit comparators are both the same as the number of columns.

[0020] Optionally, the plurality of control switches are configured to be opened or closed according to a control signal sent by the logic unit, so that the capacitors corresponding to the plurality of control switches receive the high signal, the low signal and the analog quantity sampled by the target sampling unit;

[0021] Wherein, each of the control switches is a three-phase switch;

[0022] The first phase switch of the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the high signal;

[0023] The second phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the low signal;

[0024] The third phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the analog quantity.

[0025] Optionally, the 8-bit capacitor array is configured to generate a comprehensive amount of corresponding analog quantities according to the high signal, the low signal and the analog quantity sampled by the target sampling unit received by each of the capacitors, and transmit the comprehensive amount to the SAR comparator.

[0026] Optionally, the SAR comparator comprises: two input terminals, one of which is a non-inverting terminal for receiving a reference voltage, and the other is an inverting terminal for receiving the integrated value;

[0027] The SAR comparator is configured to generate a comparison signal according to a comparison result between the reference voltage quantity and the comprehensive quantity and transmit the comparison signal to the logic unit;

[0028] The logic unit is configured to generate the control signal according to the comparison signal, and obtain and output the digital quantity.

[0029] Optionally, the 8-bit capacitor array includes: a first capacitor to an eighth capacitor, and the eight capacitors are connected in parallel;

[0030] The first end of each capacitor is electrically connected to one of the control switches, and the second end is electrically connected to the inverting end of the SAR comparator after being short-circuited with the second ends of the remaining capacitors;

[0031] Among them, the second capacitor has a capacitance twice the first capacitor, the third capacitor has a capacitance four times the first capacitor, and the eighth capacitor has a capacitance one hundred and twenty-eight times the first capacitor.

[0032] Optionally, the 8-bit capacitor array includes: a first capacitor to a ninth capacitor;

[0033] The first capacitor to the fourth capacitor are connected in parallel to form a first resistor group;

[0034] The fifth capacitor to the eighth capacitor are connected in parallel to form a second resistor group;

[0035] The first capacitor group and the second capacitor group are electrically connected via the ninth capacitor;

[0036] The first end of each capacitor in the first capacitor group is electrically connected to one of the control switches, and the second end is electrically connected to one end of the ninth capacitor after being short-circuited with the second ends of the remaining capacitors;

[0037] The first end of each capacitor in the second capacitor group is electrically connected to one of the control switches respectively, and the second end is short-circuited with the second ends of the remaining capacitors and then electrically connected to the other end of the ninth capacitor and the inverting end of the SAR comparator;

[0038] Among them, the second capacitor capacitance is twice the first capacitor capacitance, the third capacitor capacitance is four times the first capacitor capacitance, the fourth capacitor capacitance is eight times the first capacitor capacitance, the fifth capacitor capacitance is the same as the first capacitor capacitance, the sixth capacitor capacitance is twice the first capacitor capacitance, the seventh capacitor capacitance is four times the first capacitor capacitance, the eighth capacitor capacitance is eight times the first capacitor capacitance, and the ninth capacitor capacitance is the same as the first capacitor capacitance.

[0039] A second aspect of an embodiment of the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising a column-level composite analog-to-digital conversion circuit as described in any one of the first aspects.

[0040] A third aspect of an embodiment of the present invention provides an electronic device, comprising: the analog-to-digital converter as described in the second aspect.

[0041] The column-level composite analog-to-digital conversion circuit provided by the present invention is applied to a large-scale array readout circuit, and comprises: a flash analog-to-digital converter, a plurality of sampling units, and a plurality of successive approximation analog-to-digital converters. Each of the plurality of sampling units is electrically connected to a column in the array in a one-to-one correspondence, that is, there are as many sampling units as there are columns in the array, and the number of sampling units is the same as the number of columns in the array.

[0042] The plurality of sampling units are electrically connected to the plurality of successive approximation analog-to-digital converters through flash analog-to-digital converters, wherein one sampling unit corresponds to one successive approximation analog-to-digital converter, and the number of the successive approximation analog-to-digital converters is the same as the number of columns.

[0043] Each successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit. One end of each capacitor in the 8-bit capacitor array is electrically connected to the flash analog-to-digital converter through a control switch, and the other end is electrically connected to the input end of the SAR comparator; the output end of the SAR comparator is electrically connected to the input end of the logic unit; the output end of the logic unit is electrically connected to the control switch, and outputs a digital quantity corresponding to the analog quantity sampled by the target sampling unit.

[0044] The column-level composite analog-to-digital conversion circuit proposed in the present invention adopts a structure of a flash analog-to-digital converter combined with a successive approximation analog-to-digital converter. Since an 8-bit capacitor array is used in the successive approximation analog-to-digital converter, the accuracy of the flash analog-to-digital converter is ensured by the 8-bit capacitor array outside the flash analog-to-digital converter. And since the non-uniformity of the capacitor is less than 0.2%, the SARADC composed of the 8-bit capacitor array itself does not need to be calibrated, which will not cause SARADC quantization errors, ensuring the high accuracy of the quantization results, and is therefore more conducive to application and implementation in large-scale array structures, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0046] Figure 1 It is a schematic diagram of the architecture of a conventional large-scale array readout circuit;

[0047] Figure 2 is a schematic structural diagram of an exemplary column-level composite analog-to-digital conversion circuit in an embodiment of the present invention;

[0048] Figure 3 1 is a schematic diagram of the structure of a column-level composite analog-to-digital conversion circuit taking 16 columns as an example in an embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of a preferred flash analog-to-digital converter in an embodiment of the present invention;

[0050] Figure 5 is a schematic structural diagram of a preferred successive approximation analog-to-digital converter in an embodiment of the present invention;

[0051] Figure 6 It is a structural schematic diagram of another preferred successive approximation analog-to-digital converter in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The inventors have found that the conventional large-scale array readout circuits often use a single slope analog-to-digital conversion circuit when using column-level analog-to-digital conversion, but single slope analog-to-digital conversion often means that low power consumption and high precision are incompatible, that is, high precision is obtained by consuming huge power consumption, or low power consumption is consumed, but the precision is naturally low.

[0054] For example, refer to Figure 1 The schematic diagram of the architecture of the conventional large-scale array readout circuit is shown in FIG. For each column in the array, there is a sampling unit that samples the signal (generally a voltage signal, analog quantity) on the column to which it is electrically connected, and obtains a sampling signal V SH And transmitted to the comparator, the comparator's in-phase terminal receives the sampling signal V SH , the inverting terminal of the comparator and the single ramp signal generating module ( Figure 1 ) is electrically connected to receive a single ramp signal V RAMP .

[0055] The comparator samples the signal V SH , single ramp signal V RAMP Compare and get the comparison signal CMP OUT And transmitted to the counter, the counter compares the signal CMP OUT The memory continuously samples and stores the counting code value of the counter, and finally outputs the digital value D corresponding to the sampling signal. OUT To outside the film.

[0056] Depend on Figure 1 It can be seen that the traditional column-level single-slope analog-to-digital converter needs to implement a counter at the column level. Each column has a counter and a memory, and both work continuously. When the quantization time is fixed, the frequency of the clock signal determines the quantization accuracy. However, high-frequency clock signals are often difficult to transmit in large-array column-level circuits. This is because there are interference factors such as parasitic capacitance that are difficult to avoid in large-array column-level circuits. Therefore, high-frequency clock signals will cause signal distortion and deformation as the transmission continues, reducing the quantization accuracy. In order to prevent the signal distortion and deformation of the high-frequency clock, huge power consumption is required. And a single-column counter that implements a high-frequency clock signal also means huge power consumption. Therefore, power consumption and accuracy are difficult to be compatible.

[0057] Since high-frequency clocks are difficult to transmit and the quantization time of SSADC (single slope analog-to-digital converter) is often quite strict, this will also lead to insufficient quantization accuracy of SSADC. Based on this problem, a solution currently adopted is to use a single slope analog-to-digital conversion plus TDC architecture to implement the analog-to-digital converter. However, this architecture will lead to poor performance of analog-to-digital conversion due to power consumption limitations or sampling errors.

[0058] In order to speed up the quantization process, SARADC may be used. When the conventional SARADC is implemented above 12 bits, the SARADC quantization process itself needs to be calibrated. However, due to the limitation of layout area, especially the need for miniaturization, large-scale array circuits cannot calibrate SARADC, which leads to SARADC quantization errors and ultimately the quantization results of the entire analog-to-digital converter are incorrect.

[0059] In view of the above problems, the inventors have creatively proposed a column-level composite analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device of the present invention after in-depth research. The technical solution of the present invention is explained and illustrated in detail below.

[0060] The column-level composite analog-to-digital conversion circuit of the present invention is particularly suitable for large-scale array readout circuits. The column-level composite analog-to-digital conversion circuit includes: a flash analog-to-digital converter, a plurality of sampling units, and a plurality of successive approximation analog-to-digital converters.

[0061] Each sampling unit in the plurality of sampling units is electrically connected to a column in the array in a one-to-one correspondence, that is, there are as many sampling units as there are columns in the array, and the number of sampling units is the same as the number of columns in the array; the plurality of sampling units are electrically connected to the plurality of successive approximation analog-to-digital converters through flash analog-to-digital converters, wherein one sampling unit corresponds to one successive approximation analog-to-digital converter. The flash analog-to-digital converter is equivalent to being arranged between the sampling unit and the successive approximation analog-to-digital converter, and the number of the successive approximation analog-to-digital converters is the same as the number of columns, and naturally the same as the number of sampling units.

[0062] Each successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit. In terms of connection relationship, one end of each capacitor in the 8-bit capacitor array is electrically connected to the flash analog-to-digital converter through a control switch, and the other end is electrically connected to the input end of the SAR comparator.

[0063] The output end of the SAR comparator is electrically connected to the input end of the logic unit; the output end of the logic unit is electrically connected to the control switch, and outputs the digital quantity corresponding to the analog quantity sampled by the target sampling unit, and the target sampling unit is a sampling unit corresponding to the successive approximation analog-to-digital converter. That is, the SAR comparator not only outputs the digital quantity corresponding to the target column, but also sends a control signal to the control switch to control the opening or closing of the switch. The control signal is generated based on the digital quantity.

[0064] The flash analog-to-digital converter is configured to generate a high signal and a low signal corresponding to each sampling unit based on the analog quantity sampled by each sampling unit and the maximum and minimum values ​​of the preset voltage signal, and transmit the high signal and the low signal to the successive approximation analog-to-digital converter corresponding to each sampling unit respectively.

[0065] In order to better understand the structure of the above column-level composite analog-to-digital conversion circuit, refer to Figure 2 A schematic diagram of the structure of an exemplary column-level composite analog-to-digital conversion circuit is shown, Figure 2 For the sake of simplicity, the circuit structure of one column is shown as an example, which includes: a sampling unit 1, a flash analog-to-digital converter, and a successive approximation analog-to-digital converter 1. For more information, refer to Figure 3 The structure shown can be obtained without further elaboration.

[0066] Figure 2 The sampling unit 1 samples the sampled signal V TH1 , transmitted to the flash ADC and the successive approximation ADC 1. The flash ADC is based on the analog quantity V sampled by sampling unit 1. TH1 , and the maximum value of the preset voltage signal V TOP , minimum value V BOT , generating a high signal V corresponding to the sampling unit TOPM1 , low signal V BOTM1 , and the high signal V TOPM1 , low signal V BOTM1 The digital value D is transmitted to the successive approximation analog-to-digital converter 1. OUT .

[0067] Figure 3 Taking 16 columns as an example, the circuit architecture of multiple columns is shown. Figure 3 The 16 columns correspond to 16 sampling units: sampling unit 1 to sampling unit 16, and their respective sampling signals V TH1 ~V TH16Transmitted to the flash ADC and the corresponding SAR ADC: SAR 1 to SAR 16, each SAR ADC receives not only the corresponding sampling signal, but also the corresponding high signal V TOPM , low signal V BOTM , for example, the successive approximation analog-to-digital converter 1 receives the corresponding high signal V TOPM1 , low signal V BOTM1 The other columns are the same and can be obtained through simple reasoning, so I will not go into details.

[0068] The structure of the flash analog-to-digital converter preferably includes: a plurality of unit resistors, a plurality of unit comparators, and a digital-to-analog conversion unit. Figure 4 The schematic diagram of the structure of a preferred flash analog-to-digital converter is shown in FIG. 1 , wherein a plurality of unit resistors form a resistor string, and the second end of each unit resistor is electrically connected to the inverting end of a unit comparator and the first end of the unit resistor connected in series with itself, respectively, wherein the first end of the unit resistor R1 at the head end of the resistor string receives the maximum value V of the preset voltage signal TOP The second end of the unit resistor R2 at the end of the resistor string receives the minimum value V of the preset voltage signal BOT .

[0069] The non-inverting terminal of each unit comparator receives an analog quantity sampled by a sampling unit; Figure 4 In order to simplify the diagram, V SH Represents all sampling signals. The output terminals of the plurality of unit comparators are electrically connected to the digital-to-analog conversion unit.

[0070] The digital-to-analog conversion unit generates a high signal V corresponding to each sampling unit. TOPM , low signal V BOTM , Figure 4 In order to simplify the diagram, V TOPM 、V BOTM Indicates all high signals and low signals. And the high signal V TOPM , low signal V BOTM are transmitted to the successive approximation analog-to-digital converter ( Figure 4 (not shown). The number of the plurality of unit resistors and the number of the plurality of unit comparators are the same as the number of columns. For example, if there are 16 columns, the number of the unit resistors is 16 and the number of the unit comparators is 16.

[0071] The successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit. The plurality of control switches are configured to be opened or closed according to a control signal sent by the logic unit, so that the capacitors corresponding to the plurality of control switches receive a high signal, a low signal, and an analog quantity sampled by a target sampling unit.

[0072] Among them, each control switch is a three-phase switch; the first phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives a high signal; the second phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives a low signal; the third phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives an analog quantity.

[0073] The 8-bit capacitor array is configured to generate a comprehensive amount of the corresponding analog quantity according to the analog quantity sampled by each capacitor, the high signal, the low signal and the target sampling unit, and transmit the comprehensive amount to the SAR comparator. Based on the general structure of the comparator, the SAR comparator includes: two input terminals, one of which is a non-inverting terminal that receives a reference voltage, and the other is an inverting terminal that receives a comprehensive amount.

[0074] The SAR comparator is configured to generate a comparison signal according to the comparison result between the reference voltage and the comprehensive quantity and transmit the comparison signal to the logic unit. The logic unit is configured to generate a control signal according to the comparison signal and obtain and output a digital quantity.

[0075] There are multiple structures for the 8-bit capacitor array, one of which is a better structure including: the first capacitor to the eighth capacitor, and the eight capacitors are connected in parallel. The first end of each capacitor is electrically connected to a control switch, and the second end is short-circuited with the second ends of the remaining capacitors and then electrically connected to the inverting end of the SAR comparator. Among them, the capacitance of the second capacitor is twice the capacitance of the first capacitor, the capacitance of the third capacitor is four times the capacitance of the first capacitor... The capacitance of the eighth capacitor is one hundred and twenty-eight times the capacitance of the first capacitor.

[0076] For a better understanding of successive approximation analog-to-digital converters, refer to Figure 5 A schematic diagram of a preferred successive approximation analog-to-digital converter is shown in FIG. Figure 5 In the figure, each capacitor is marked with its capacitance value. The leftmost capacitor in the 8-bit capacitor array is the first capacitor 1C, the adjacent capacitor is the second capacitor 2C, and so on. The rightmost capacitor is the eighth capacitor 128C. The first end of each capacitor is electrically connected to a control switch, so that each capacitor receives a high signal V according to the opening and closing of the control switch. TOPM , low signal V BOTM and the sampling signal V SH .

[0077] The second end of each capacitor is short-circuited with the second ends of the other capacitors and then electrically connected to the inverting end of the SAR comparator. The non-inverting end of the SAR comparator receives the reference voltage V REF The SAR comparator measures the reference voltage VREF The comparison result with the comprehensive quantity generates a comparison signal and transmits it to the logic unit. The logic unit generates a control signal based on the comparison signal, and obtains and outputs the digital quantity D OUT .

[0078] Considering that the capacitors in the above 8-bit capacitor array need to have larger capacitance, and the larger capacitance naturally means larger volume of capacitors, which requires larger space and affects miniaturization, another preferred 8-bit capacitor array structure includes: first capacitor to ninth capacitor.

[0079] The first capacitor to the fourth capacitor are connected in parallel to form a first resistor group; the fifth capacitor to the eighth capacitor are connected in parallel to form a second resistor group; the first capacitor group and the second capacitor group are electrically connected through a ninth capacitor. The first end of each capacitor in the first capacitor group is electrically connected to a control switch, and the second end is short-circuited with the second ends of the remaining capacitors and then electrically connected to one end of the ninth capacitor; the first end of each capacitor in the second capacitor group is electrically connected to a control switch, and the second end is short-circuited with the second ends of the remaining capacitors and then electrically connected to the other end of the ninth capacitor and the inverting end of the SAR comparator.

[0080] Among them, the second capacitor capacitance is twice the first capacitor capacitance, the third capacitor capacitance is four times the first capacitor capacitance, the fourth capacitor capacitance is eight times the first capacitor capacitance, the fifth capacitor capacitance is the same as the first capacitor capacitance, the sixth capacitor capacitance is twice the first capacitor capacitance, the seventh capacitor capacitance is four times the first capacitor capacitance, the eighth capacitor capacitance is eight times the first capacitor capacitance, and the ninth capacitor capacitance is the same as the first capacitor capacitance.

[0081] To better understand this successive approximation analog-to-digital converter, refer to Figure 6 Another structural diagram of a preferred successive approximation analog-to-digital converter is shown in FIG. Figure 6 In the figure, each capacitor is marked by its capacitance value. The leftmost capacitor in the 8-bit capacitor array is the first capacitor 1C, and the adjacent one is the second capacitor 2C. Similarly, the 4 capacitors on the left are the first capacitor group, and the 4 capacitors on the right are the second capacitor group. The largest capacitance is 8C. The ninth capacitor with a capacitance value of 1C is placed in the middle of the two capacitor groups. The rest of the structure is the same as Figure 5 The structures shown are the same and will not be described in detail. In this structure, since the maximum capacitance is 8C, the space occupied by the capacitor can be well reduced, which is very conducive to miniaturization.

[0082] Through the above structure, the entire column-level composite analog-to-digital conversion circuit adopts a structure of a flash analog-to-digital converter combined with a successive approximation analog-to-digital converter. Since an 8-bit capacitor array is used in the successive approximation analog-to-digital converter, the accuracy of the flash analog-to-digital converter is guaranteed by the 8-bit capacitor array outside the flash analog-to-digital converter. And since the non-uniformity of the capacitor is less than 0.2%, the SARADC composed of the 8-bit capacitor array itself does not need to be calibrated, which will not cause SARADC quantization errors, ensuring the high accuracy of the quantization results, and is therefore more conducive to application and implementation in large-scale array structures.

[0083] Based on the above-mentioned column-level composite analog-to-digital conversion circuit, an embodiment of the present invention further provides an analog-to-digital converter, and the analog-to-digital converter includes any of the above-mentioned column-level composite analog-to-digital conversion circuits.

[0084] Based on the above-mentioned column-level composite analog-to-digital conversion circuit, an embodiment of the present invention further provides an electronic device, and the electronic device includes: the above-mentioned analog-to-digital converter.

[0085] Through the above embodiments, the column-level composite analog-to-digital conversion circuit provided by the present invention is applied to a large-scale array readout circuit, and includes: a flash analog-to-digital converter, a plurality of sampling units, and a plurality of successive approximation analog-to-digital converters. Each of the plurality of sampling units is electrically connected to a column in the array in a one-to-one correspondence, that is, there are as many sampling units as there are columns in the array, and the number of sampling units is the same as the number of columns in the array.

[0086] The plurality of sampling units are electrically connected to the plurality of successive approximation analog-to-digital converters through flash analog-to-digital converters, wherein one sampling unit corresponds to one successive approximation analog-to-digital converter, and the number of the successive approximation analog-to-digital converters is the same as the number of columns.

[0087] Each successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit. One end of each capacitor in the 8-bit capacitor array is electrically connected to the flash analog-to-digital converter through a control switch, and the other end is electrically connected to the input end of the SAR comparator; the output end of the SAR comparator is electrically connected to the input end of the logic unit; the output end of the logic unit is electrically connected to the control switch, and outputs a digital quantity corresponding to the analog quantity sampled by the target sampling unit.

[0088] The column-level composite analog-to-digital conversion circuit proposed in the present invention adopts a structure of a flash analog-to-digital converter combined with a successive approximation analog-to-digital converter. Since an 8-bit capacitor array is used in the successive approximation analog-to-digital converter, the accuracy of the flash analog-to-digital converter is ensured by the 8-bit capacitor array outside the flash analog-to-digital converter. And since the non-uniformity of the capacitor is less than 0.2%, the SARADC composed of the 8-bit capacitor array itself does not need to be calibrated, which will not cause SARADC quantization errors, ensuring the high accuracy of the quantization results, and is therefore more conducive to application and implementation in large-scale array structures, and has high practicality.

[0089] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0090] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A column-level composite analog-to-digital conversion circuit, characterized in that: The column-level composite analog-to-digital conversion circuit is applied to a large-scale array readout circuit, and the column-level composite analog-to-digital conversion circuit comprises: a flash analog-to-digital converter, a plurality of sampling units, and a plurality of successive approximation analog-to-digital converters; Each sampling unit in the plurality of sampling units is electrically connected to a column in the array in a one-to-one correspondence, and the number of the sampling units is the same as the number of columns in the array; The plurality of sampling units are electrically connected to the plurality of successive approximation analog-to-digital converters through the flash analog-to-digital converters, wherein one sampling unit corresponds to one successive approximation analog-to-digital converter, and the number of the successive approximation analog-to-digital converters is the same as the number of columns; Each successive approximation analog-to-digital converter includes: an 8-bit capacitor array, a plurality of control switches, a SAR comparator, and a logic unit; One end of each capacitor in the 8-bit capacitor array is electrically connected to the flash analog-to-digital converter through a control switch, and the other end is electrically connected to the input end of the SAR comparator; The output terminal of the SAR comparator is electrically connected to the input terminal of the logic unit; The output end of the logic unit is electrically connected to the control switch, and outputs a digital quantity corresponding to the analog quantity sampled by a target sampling unit, wherein the target sampling unit is a sampling unit corresponding to a successive approximation analog-to-digital converter.

2. The column-level composite analog-to-digital conversion circuit according to claim 1, characterized in that: The flash analog-to-digital converter is configured to generate a high signal and a low signal corresponding to each sampling unit based on the analog quantity sampled by each sampling unit and the maximum value and the minimum value of the preset voltage signal, and transmit the high signal and the low signal to the successive approximation analog-to-digital converter corresponding to each sampling unit.

3. The column-level composite analog-to-digital conversion circuit according to claim 2, characterized in that: The flash analog-to-digital converter comprises: a plurality of unit resistors, a plurality of unit comparators, and a digital-to-analog conversion unit; A plurality of the unit resistors form a resistor string, wherein the second end of each unit resistor is electrically connected to an inverting end of a unit comparator and to the first end of the unit resistor connected in series with itself, wherein the first end of the unit resistor at the head end of the resistor string receives the maximum value of the preset voltage signal, and the second end of the unit resistor at the tail end of the resistor string receives the minimum value of the preset voltage signal; The non-inverting terminal of each unit comparator receives an analog quantity sampled by a sampling unit; The output terminals of the plurality of unit comparators are electrically connected to the digital-to-analog conversion unit; The digital-to-analog conversion unit generates a high signal and a low signal corresponding to each sampling unit, and transmits the high signal and the low signal to a successive approximation analog-to-digital converter corresponding to each sampling unit; The number of the plurality of unit resistors and the number of the plurality of unit comparators are both the same as the number of columns.

4. The column-level composite analog-to-digital conversion circuit according to claim 2, characterized in that: The plurality of control switches are configured to be opened or closed according to the control signal sent by the logic unit, so that the capacitors corresponding to the plurality of control switches receive the high signal, the low signal and the analog quantity sampled by the target sampling unit; Wherein, each of the control switches is a three-phase switch; The first phase switch of the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the high signal; The second phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the low signal; The third phase switch in the three-phase switch is configured to be opened or closed according to the control signal, so that the capacitor electrically connected to the control switch receives the analog quantity.

5. The column-level composite analog-to-digital conversion circuit according to claim 4, characterized in that: The 8-bit capacitor array is configured to generate a comprehensive amount of corresponding analog quantities according to the high signal, the low signal and the analog quantity sampled by the target sampling unit received by each capacitor, and transmit the comprehensive amount to the SAR comparator.

6. The column-level composite analog-to-digital conversion circuit according to claim 5, characterized in that: The SAR comparator comprises: two input terminals, one of which is a non-inverting terminal, which receives a reference voltage, and the other is an inverting terminal, which receives the integrated value; The SAR comparator is configured to generate a comparison signal according to a comparison result between the reference voltage quantity and the comprehensive quantity and transmit the comparison signal to the logic unit; The logic unit is configured to generate the control signal according to the comparison signal, and obtain and output the digital quantity.

7. The column-level composite analog-to-digital conversion circuit according to claim 1, characterized in that: The 8-bit capacitor array includes: a first capacitor to an eighth capacitor, and the eight capacitors are connected in parallel; The first end of each capacitor is electrically connected to one of the control switches, and the second end is electrically connected to the inverting end of the SAR comparator after being short-circuited with the second ends of the remaining capacitors; Among them, the second capacitor has a capacitance twice the first capacitor, the third capacitor has a capacitance four times the first capacitor, and the eighth capacitor has a capacitance one hundred and twenty-eight times the first capacitor.

8. The column-level composite analog-to-digital conversion circuit according to claim 1, characterized in that: The 8-bit capacitor array includes: a first capacitor to a ninth capacitor; The first capacitor to the fourth capacitor are connected in parallel to form a first capacitor group; The fifth capacitor to the eighth capacitor are connected in parallel to form a second capacitor group; The first capacitor group and the second capacitor group are electrically connected via the ninth capacitor; The first end of each capacitor in the first capacitor group is electrically connected to one of the control switches, and the second end is electrically connected to one end of the ninth capacitor after being short-circuited with the second ends of the remaining capacitors; The first end of each capacitor in the second capacitor group is electrically connected to one of the control switches respectively, and the second end is short-circuited with the second ends of the remaining capacitors and then electrically connected to the other end of the ninth capacitor and the inverting end of the SAR comparator; Among them, the second capacitor capacitance is twice the first capacitor capacitance, the third capacitor capacitance is four times the first capacitor capacitance, the fourth capacitor capacitance is eight times the first capacitor capacitance, the fifth capacitor capacitance is the same as the first capacitor capacitance, the sixth capacitor capacitance is twice the first capacitor capacitance, the seventh capacitor capacitance is four times the first capacitor capacitance, the eighth capacitor capacitance is eight times the first capacitor capacitance, and the ninth capacitor capacitance is the same as the first capacitor capacitance.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a column-level composite analog-to-digital conversion circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises: the analog-to-digital converter as claimed in claim 9.

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