A redundant calibration method and redundant calibration circuit

Abstract

The present application discloses a redundant calibration method and a redundant calibration circuit. When converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion cycle based on the analog signal, and generates a second digital code value corresponding to a second conversion cycle. If a control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit updates a comparison threshold of the comparison unit, and the comparison unit executes a third conversion cycle based on the updated comparison threshold. When there is a deviation in the comparison result, the control unit updates the comparison threshold of the comparison unit through the determined redundant comparison result, and the comparison unit executes the third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation in the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular, relates to a redundant calibration method and a redundant calibration circuit. Background Art

[0002] With the rapid increase in the degree of digitization at home and abroad in recent years, it has become more common to use analog-to-digital converters to convert analog signals into digital signals to achieve digitization. Generally, analog-to-digital converters need to sample, hold, quantize, encode and other processes on analog signals to convert them into digital signals. In the quantization process, a comparison threshold for comparison with the analog signal needs to be generated.

[0003] At present, there are some application scenarios that require the analog-to-digital converter to provide a higher sampling rate. The sampling rate is expressed as the rate of collecting and converting analog signals. The higher the sampling rate, the faster the rate of collecting and converting analog signals, and the shorter the time required for analog-to-digital conversion. However, too short analog-to-digital conversion time will result in too little setup time for comparison in the quantization process, and insufficient setup time, resulting in deviations in the comparison results. In the encoding process, erroneous digital signals will be generated due to erroneous comparison results, reducing the accuracy of encoding the analog signal.

[0004] Generally, a redundant circuit can be constructed to compensate for the situation where an erroneous comparison result is generated. However, if the error between the erroneous comparison result and the correct comparison result is larger than the range that the redundant circuit can compensate, the redundant circuit cannot be used to compensate for the erroneous comparison result, thereby reducing the accuracy of encoding the analog signal and the reliability of compensation based on the redundant circuit. Summary of the invention

[0005] The embodiments of the present application provide a redundant calibration method and a redundant calibration circuit, which aim to solve the problem that the existing method of using redundant circuits for compensation has low compensation accuracy and reduces the accuracy of encoding analog signals.

[0006] In a first aspect, an embodiment of the present application provides a redundant calibration circuit, including:

[0007] A capacitor array, comprising at least one positive redundant capacitor, at least one negative redundant capacitor and at least one conversion capacitor, wherein the positive redundant capacitor and the negative redundant capacitor are used to output redundant calibration signals, and the conversion capacitor is used for analog signal conversion;

[0008] A comparison unit connected to the capacitor array, and configured to determine a redundant comparison result when a redundant calibration condition is met, wherein the redundant comparison result is determined based on the redundant calibration signal;

[0009] A control unit is connected to the capacitor array and the comparison unit, and is used to determine a target redundant capacitor in the capacitor array and update a comparison threshold of the comparison unit based on a redundant comparison result, wherein the redundant comparison result is determined by the comparison unit based on a redundant calibration signal output by the target redundant capacitor.

[0010] In a possible implementation manner of the first aspect above, the capacitor array further includes a first receiving end and a second receiving end, the first receiving end is used to obtain a reference voltage, and the second receiving end is grounded;

[0011] The control unit is further used to control the target redundant capacitor to be connected to the first receiving end or the second receiving end.

[0012] In a second aspect, an embodiment of the present application provides a redundant calibration method, the method is applied to a redundant calibration circuit, the redundant calibration circuit includes a comparison unit and a control unit, the method includes:

[0013] When converting the analog signal, the comparison unit generates a first digital code value corresponding to a first conversion period based on the analog signal, and generates a second digital code value corresponding to a second conversion period;

[0014] If the control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit updates a comparison threshold of the comparison unit;

[0015] The comparison unit performs a third conversion cycle based on the updated comparison threshold.

[0016] In a possible implementation manner of the second aspect, the redundant calibration circuit further includes a capacitor array, and the control unit updates the comparison threshold of the comparison unit, including:

[0017] The control unit determines a target redundant capacitor from the capacitor array according to the first digital code value;

[0018] A comparison threshold of the comparison unit is updated according to the target redundant capacitance.

[0019] In a possible implementation manner of the second aspect, the capacitor array includes at least one positive redundant capacitor and at least one negative redundant capacitor, and the control unit determines a target redundant capacitor from the capacitor array according to the first digital code value, including:

[0020] The control unit determines whether the first digital code value is a target code value;

[0021] When the first digital code value is a target code value, determining a target positive terminal redundant capacitor corresponding to the second conversion period from all the positive terminal redundant capacitors;

[0022] When the first digital code value is a non-target code value, a target negative terminal redundant capacitor corresponding to the second conversion period is determined from all the negative terminal redundant capacitors.

[0023] In a possible implementation manner of the second aspect, updating the comparison threshold of the comparison unit according to the target redundant capacitance includes:

[0024] When the first digital code value is a target code value, the control unit connects the target positive-end redundant capacitor to a reference signal, and updates a comparison threshold of the comparison unit based on the reference signal and the analog signal;

[0025] When the first digital code value is a non-target code value, the control unit connects the target negative-end redundant capacitor to the reference signal, and updates a comparison threshold of the comparison unit based on the reference signal and the analog signal.

[0026] In a possible implementation manner of the second aspect, the redundant calibration circuit further includes a conversion capacitor, the conversion capacitor includes at least one positive-end conversion capacitor, the control unit connects the target negative-end redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal, including:

[0027] The control unit determines a target positive terminal conversion capacitance corresponding to the second conversion period from all the conversion capacitances;

[0028] Connecting the target negative-end redundant capacitor and the target positive-end conversion capacitor to the reference signal to generate a weight coefficient corresponding to the second conversion period;

[0029] The comparison threshold of the comparison unit is updated according to the weight coefficient to obtain a target comparison unit.

[0030] In a possible implementation manner of the second aspect, if the control unit determines that a redundant calibration condition is met based on the first digital code value and the second digital code value, before the control unit updates the comparison threshold of the comparison unit, the method further includes:

[0031] The control unit compares the first digital code value with the second digital code value;

[0032] When the first digital code value is not equal to the second digital code value, determining that the redundant calibration condition is not satisfied;

[0033] When the first digital code value is equal to the second digital code value, it is determined that the redundant calibration condition is satisfied.

[0034] In a third aspect, an embodiment of the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the redundant calibration method provided in the second aspect above is implemented.

[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the redundant calibration method provided in the second aspect is implemented.

[0036] It can be understood that the beneficial effects of the first, third and fourth aspects mentioned above can be found in the relevant description of the second aspect mentioned above, and will not be repeated here.

[0037] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0038] In an embodiment of the present invention, when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion cycle based on the analog signal, and generates a second digital code value corresponding to a second conversion cycle. If the control unit determines that a redundant calibration condition is met based on the first digital code value and the second digital code value, the control unit updates the comparison threshold of the comparison unit, and the comparison unit executes a third conversion cycle based on the updated comparison threshold, so that when there is a deviation in the comparison result, the control unit updates the comparison threshold of the comparison unit through the determined redundant comparison result, so that the comparison unit executes the third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation in the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1a is a conversion schematic diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0040] Figure 1b It is a schematic diagram of a relatively erroneous conversion in a successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0041] Figure 1c It is a schematic diagram of redundant calibration based on a successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0042] Figure 2a is a structural block diagram of a redundant calibration circuit provided by an embodiment of the present invention;

[0043] Figure 2b is a structural schematic diagram of a redundant calibration circuit provided by an embodiment of the present invention;

[0044] Figure 3 is a calibration effect diagram of a redundant calibration circuit provided by an embodiment of the present invention;

[0045] Figure 4 is a flowchart of a redundant calibration method provided by an embodiment of the present invention;

[0046] Figure 5 is a flowchart of another redundant calibration method provided by an embodiment of the present invention;

[0047] Figure 6 is an example flow chart of a redundant calibration method provided by an embodiment of the present invention;

[0048] Figure 7 It is a structural block diagram of a terminal device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] In recent years, in order to achieve digitization, an analog to digital converter (ADC) can be used to convert analog signals into digital signals. Among them, the analog to digital converter will include a capacitor array for sampling and holding analog signals, a comparator for comparing analog signals with comparison thresholds, and a controller for quantizing and encoding analog signals based on comparison results in different conversion cycles. Analog signals can be information represented by continuously changing physical quantities, such as voltage information, current signals, frequency signals, etc., and analog signals can be obtained based on acquisition sensors, amplifiers and other devices. Digital signals can be discrete signals using binary codes.

[0051] When an analog-to-digital converter converts an analog signal into a digital signal, it generally needs to sample, hold, quantize, encode, and perform other processes on the analog signal. That is, a complete analog-to-digital conversion cycle includes sampling, holding, quantizing, encoding, and other processes. Among them, in the quantization process, a comparison threshold for comparison with the analog signal needs to be generated by a digital-to-analog converter (DAC), and the digital signal is determined based on the comparison result between the analog signal and the comparison threshold.

[0052] At present, different application scenarios have different requirements for the sampling rate of analog-to-digital converters, and some application scenarios require analog-to-digital converters to provide higher sampling rates. The sampling rate is expressed as the rate at which analog signals are collected and converted, that is, the higher the sampling rate, the faster the rate at which analog signals are collected and converted, and the shorter the analog-to-digital conversion cycle. However, a too short conversion cycle will result in too little setup time for comparison in the quantization process, and insufficient setup, which will cause deviations in the comparison results based on the insufficient setup. In addition, the coupling between the traces in various locations in the analog-to-digital converter will also affect the accuracy of the comparison, and then in the encoding process, due to incorrect comparison results, erroneous digital signals will be generated, reducing the accuracy of encoding the analog signal.

[0053] Generally, a redundant calibration circuit can be constructed to compensate for the situation where an erroneous comparison result is generated. However, if the error between the erroneous comparison result and the correct comparison result is greater than the range that the redundant calibration circuit can compensate, the redundant calibration circuit cannot be used to compensate for the erroneous comparison result, thereby reducing the accuracy of encoding the analog signal and the reliability of compensation based on the redundant circuit.

[0054] For example, a successive approximation analog-to-digital converter (SAR ADC) can be one type of analog-to-digital converter. In each process of converting an analog signal, the SAR ADC will undergo at least one conversion cycle corresponding to the number of bits of the SAR ADC, and the weight value of each conversion cycle corresponds to the number of bits. For example, if the number of bits of the SAR ADC is 4, then 4 conversion cycles are required, and the weight value of each conversion cycle decreases with the value of the number of bits of the SAR ADC, that is, the weight value of the first conversion cycle is the number of bits of the SAR ADC minus one, and the weight value of the second conversion cycle is the number of bits of the SAR ADC minus two, and so on.

[0055] In the process of converting analog signals each time, the SAR ADC determines the quantization value of the analog signal in each conversion cycle and compares the quantization value with the comparison threshold one by one to obtain the comparison result of each conversion cycle, as well as the digital signal output based on the comparison result and its corresponding weight in each conversion cycle. That is, any analog signal can correspond to a unique digital signal, which can be specifically expressed by the following formula:

[0056] Dout=2^(n3)*b3+2^(n2)*b2+2^(n1)*b1+2^(n0)*b0

[0057] Among them, Dout can be represented as a digital signal, n3 can be the weight value corresponding to the first conversion cycle, n2 can be the weight value corresponding to the second conversion cycle, n1 can be the weight value corresponding to the third conversion cycle, and n0 can be the weight value corresponding to the fourth conversion cycle.

[0058] See also Figure 1a , Figure 1a FIG. 4 shows a conversion diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present invention. Figure 1a As shown, Vi can be an analog signal, and the bit number of the successive approximation analog-to-digital converter can be 4 bits, and then a conversion cycle corresponding to the bit number of the successive approximation analog-to-digital converter is required to convert the analog signal into a digital signal, that is, 4 conversion cycles are required to convert the analog signal into a digital signal.

[0059] Among them, b3 can be expressed as the digital code value of the first conversion cycle, and its corresponding weight value is 4, b2 can be expressed as the digital code value of the second conversion cycle, and its corresponding weight value is 3, and so on, and a3 can be expressed as the comparison threshold of the first conversion cycle, and a2 can be expressed as the comparison threshold of the second conversion cycle, and so on. Among them, the range of 0 to 16 of the first conversion cycle can be expressed as the maximum signal range of the analog signal input in the analog-to-digital converter, and the maximum signal range is divided into 16 parts, and the range of 0 to 8 of the second conversion cycle can be expressed as the range of reducing the maximum signal range according to the weight value of the second conversion cycle.

[0060] When converting an analog signal, the analog signal can be compared with a comparison threshold value of each conversion cycle, and a digital code value can be output based on the comparison result, and then the digital signal can be determined according to all the digital code values. For each conversion cycle, when the analog signal is less than the comparison threshold value, the digital code value corresponding to the output comparison result is 0, and when the analog signal is greater than the comparison threshold value, the digital code value corresponding to the output comparison result is 1.

[0061] For example, in the first conversion cycle, the analog signal Vi is compared with the comparison threshold a3 of the first conversion cycle, and the comparison result of Vi being less than a3 is obtained, and then the value of b3 is determined to be 0 based on the comparison result. In the second conversion cycle, the analog signal Vi is compared with the comparison threshold a2 of the second conversion cycle, and the comparison result of Vi being greater than a2 is obtained, and then the value of b2 is determined to be 1 based on the comparison result, and so on, all digital code values ​​are obtained, b3=0, b2=1, b1=0, b0=0. The weight value corresponding to b3 is 4, the weight value corresponding to b2 is 3, the weight value corresponding to b1 is 2, and the weight value corresponding to b0 is 1, and then the output digital signal is 2^3*b3+2^2*b2+2^1*b1+2^0*b0, that is, 4, and the binary expression can be 0100.

[0062] However, if there is a deviation in the comparison result in any conversion cycle, the digital signal outputted in the conversion cycle will be erroneous.

[0063] See also Figure 1b , Figure 1b FIG. 4 shows a schematic diagram of a conversion error in a successive approximation analog-to-digital converter provided by an embodiment of the present invention. Figure 1b As shown in the figure, in the second conversion cycle, Vi is greater than a2, and the comparison result should be that the analog signal is greater than the comparison threshold, and the value of b2 should be 1. However, due to the lack of setup time and other reasons, the actual value of b2 is output as 0, and there is a comparison error, resulting in the output digital signal being 0011, which is different from the digital signal 0100 that should be output, that is, an erroneous digital signal is output, that is, Figure 1b At point A in the middle.

[0064] Based on this, a redundant calibration circuit is constructed to increase the redundant conversion cycle, and when an erroneous comparison result is generated, a redundant digital signal is output through the redundant conversion cycle, and then the erroneous digital signal is compensated based on the redundant digital signal to obtain a correct digital signal.

[0065] See also Figure 1c , Figure 1c FIG. 4 shows a schematic diagram of a redundant calibration based on a successive approximation analog-to-digital converter provided by an embodiment of the present invention, such as Figure 1c As shown, a redundant conversion cycle is added after the third conversion cycle and before the original fourth conversion cycle, and the original fourth conversion cycle is changed to the fifth conversion cycle. The weight value of the redundant conversion cycle is the same as the weight value of the third conversion cycle.

[0066] like Figure 1c As shown, when a comparison error occurs in the second conversion cycle, that is, Figure 1cAt A in the figure, a redundant calibration operation is performed to output a redundant digital code value b1r corresponding to a redundant conversion cycle. After the redundant conversion cycle is completed, the signal range and the comparison threshold are moved up by a unit corresponding to the weight of the redundant conversion cycle. Then, in the next conversion cycle, the analog signal is compared with the updated comparison threshold, and the comparison result and its corresponding digital code value b0 are output. The digital signal 00110 is output in combination with b1r and b0. The following formula can be used to express this:

[0067] Dout=2^3*b3+2^2*b2+2^1*b1+2^1*b1r+2^0*b0

[0068] However, the error range that can be compensated by the redundant calibration circuit is limited, and its limit is related to the weight of the redundant conversion cycle in all conversion cycles. As a result, the error between the erroneous comparison result and the correct comparison result may be greater than the range that can be compensated by the redundant calibration circuit, and an erroneous digital signal will still be output, reducing the accuracy of encoding the analog signal.

[0069] Based on this, an embodiment of the present invention provides a redundant calibration circuit, see Figure 2a , Figure 2a FIG. 4 shows a structural block diagram of a redundant calibration circuit provided by an embodiment of the present invention. Figure 2a As shown, the redundant calibration circuit may include a capacitor array 1 , a comparison unit 2 , and a control unit 3 .

[0070] The capacitor array 1 can be used to collect analog signals and output quantized output signals. The capacitor array 1 can be connected to analog signals, reference signals VREFP and ground signals GND, wherein the analog signals can include analog signal positive input VINP and analog signal negative input VINM.

[0071] The comparison unit 2 may be connected to the capacitor array 1 , and the comparison unit 2 may be used to generate a comparison result between an output signal of the capacitor array 1 and a reference signal and a corresponding digital code value.

[0072] The control unit 3 may be connected to the comparison unit 2 and the capacitor array 1 . The control unit 3 may be used to control the capacitor array 1 to access a reference voltage or ground, and to update a comparison threshold in the comparison unit 2 .

[0073] See also Figure 2b , Figure 2b FIG. 4 shows a schematic diagram of a redundant calibration circuit provided by an embodiment of the present invention. Figure 2bAs shown, the capacitor array 1 may include redundant capacitors and conversion capacitors. Specifically, the capacitor array 1 may adopt a segmented capacitor array, that is, it may be composed of a positive terminal capacitor array 11 and a negative terminal capacitor array 12. The positive terminal capacitor array 11 may include at least one positive terminal conversion capacitor and at least one positive terminal redundant capacitor. The negative terminal capacitor array 12 may include at least one negative terminal conversion capacitor and at least one negative terminal redundant capacitor. The capacitor array 1 may be connected to an analog signal, a reference signal, and a ground signal. The redundant capacitors may output redundant calibration signals based on the analog signal, the reference signal, and the ground signal. The conversion capacitors may be used for analog signal conversion, and specifically may output digital code values ​​based on the analog signal, the reference signal, and the ground signal. The reference signal may be a reference voltage that the circuit always maintains constant. The reference signal may be used to determine the voltage range of the analog signal. The reference signal may be Figure 2b The VREFP module in.

[0074] The capacitor array may include a positive input side VINP for accessing the positive input of the analog signal and a negative input side VINM for accessing the negative input of the analog signal. The positive capacitor array may include all conversion capacitors and all redundant capacitors located on the positive input side of the capacitor array. The positive conversion capacitor may be a conversion capacitor located on the positive input side, and the positive redundant capacitor may be a redundant capacitor located on the positive input side. The negative capacitor array may include all conversion capacitors and all redundant capacitors located on the negative input side of the capacitor array. The negative conversion capacitor may be a conversion capacitor located on the negative input side, and the negative redundant capacitor may be a redundant capacitor located on the negative input side.

[0075] In one embodiment of the present invention, the positive terminal conversion capacitor may include a high-order positive terminal conversion capacitor and a low-order positive terminal conversion capacitor. The high-order positive terminal conversion capacitor may include C3p and C2p, and the low-order positive terminal conversion capacitor may include C1p and C0p. The positive terminal redundant capacitor may be arranged between any two positive terminal conversion capacitors, such as Figure 2b The positive-end redundant capacitor C1pr can be set between C1p and C0p.

[0076] Similarly, the negative terminal conversion capacitor may include a high-order negative terminal conversion capacitor and a low-order negative terminal conversion capacitor. The high-order negative terminal conversion capacitor may include C3m and C2m, and the low-order negative terminal conversion capacitor may include C1m and C0m. The negative terminal redundant capacitor may be set between any two positive terminal conversion capacitors, such as Figure 2b The middle negative terminal redundant capacitor C1mr can be set between C1m and C0m.

[0077] In one embodiment of the present invention, the capacitor array 1 may include a sampling capacitor and a bridging capacitor. The sampling capacitor may be used to sample analog signals. The sampling capacitor may include a positive sampling capacitor Cip and a negative sampling capacitor Cim. The upper plate of the positive sampling capacitor may be connected to the positive input side of the analog signal, and the upper plate of the negative sampling capacitor may be connected to the negative input side of the analog signal. The bridging capacitor may be used to bridge the high-order conversion capacitor and the low-order conversion capacitor. Specifically, the bridging capacitor may include a positive bridging capacitor Ccp and a negative bridging capacitor Ccm. The positive bridging capacitor may bridge the high-order positive conversion capacitor and the low-order positive conversion capacitor, and the negative bridging capacitor may bridge the high-order negative conversion capacitor and the low-order negative conversion capacitor.

[0078] In one embodiment of the present invention, each capacitor in the capacitor array 1 has a different capacitance weight, and the different capacitance weights may correspond to weight values ​​of different conversion cycles. Figure 2b As shown, the capacitance weight of C3p is 2C, the capacitance weight of C2p is 1C, the capacitance weight of C1p is 2C, the capacitance weight of C1pr is 2C, the capacitance weight of C0p is 1C, the capacitance weight of C3m is 2C, the capacitance weight of C2m is 1C, the capacitance weight of C1m is 2C, the capacitance weight of C1mr is 2C, the capacitance weight of C0m is 2C, the capacitance weight of Ccp is 6C, and the capacitance weight of Ccm is 6C. Among them, C1m and C0m do not participate in the conversion.

[0079] In an embodiment of the present invention, the capacitor array 1 may further include a complementary capacitor 13 , which may be used to complement the binary weight, and whose capacitance weight is 1C.

[0080] In an embodiment of the present invention, the capacitor array 1 may further include a first receiving end and a second receiving end. The first receiving end may obtain a reference voltage by accessing a reference voltage. The first receiving end may be used to obtain a reference voltage. The second receiving end may be grounded.

[0081] Specifically, each positive terminal conversion capacitor in the positive terminal capacitor array 11 may include a first sub-receiving terminal and a second sub-receiving terminal, and each positive terminal redundant capacitor may include a first sub-receiving terminal and a second sub-receiving terminal, while each high-order negative terminal conversion capacitor in the negative terminal capacitor array 12 includes a first sub-receiving terminal and a second sub-receiving terminal, and each negative terminal redundant capacitor may include a first sub-receiving terminal and a second sub-receiving terminal. Each first sub-receiving terminal may be connected to a reference voltage, and each second sub-receiving terminal may be grounded.

[0082] The comparison unit 2 can be connected to the capacitor array 1. The comparison unit 2 can obtain the first output signal SJP output by the positive-end capacitor array 11 and the second output signal SJM output by the negative-end capacitor array 12. The comparison unit 2 can determine the comparison result based on SJP and SJM, that is, the analog-to-digital conversion result corresponding to each analog-to-digital conversion cycle can be determined based on SJP and SJM, and the SJP and SJM during the redundant conversion cycle can be redundant calibration signals, and then the redundant comparison result can be determined based on the redundant calibration signal, that is, the comparison unit 2 can determine the redundant comparison result, and the redundant comparison result can be determined based on the redundant calibration signal.

[0083] The redundant calibration signal may be an output signal output by the capacitor array in a redundant conversion period.

[0084] As an example, the comparison unit 2 can output the comparison result and its corresponding digital code value by calculating the difference between SJP and SJM. When the comparison result is SJP-SJM>0, the corresponding digital code value is output as 0; when the comparison result is SJP-SJM<0, the corresponding digital code value is output as 1.

[0085] Specifically, the difference between SJP and SJM can be calculated by the following formula:

[0086]

[0087] Wherein, n can be the number of bits of the analog-to-digital converter, a can be an adjustment coefficient, which can be a fixed value for adjusting the input range of the analog voltage, (VINP-VINM) can be an analog signal, (VREFP-VREFM) can be a full-scale reference voltage, It can be expressed as a comparison threshold, k can be a weight coefficient, and the value of k can be related to the number of capacitors connected to the reference voltage in the positive terminal capacitor array in each conversion cycle and their weights.

[0088] The control unit 3 can be connected to the capacitor array 1 and the comparison unit 2, and the control unit 3 can be used to control the capacitor array 1 to access the reference voltage or to be grounded. Specifically, the first switch can be controlled to be opened and closed, and the second switch can be controlled to be opened and closed. The first switch can be a switch between the capacitor array 1 and the first receiving end, and the first switch can be used to control the capacitor array to access the reference voltage. The second switch can be a switch between the capacitor array 1 and the second receiving end, and the second switch can be used to control the capacitor array to be grounded.

[0089] The control unit 3 can also be used to determine the target redundant capacitor in the capacitor array 1 for performing analog signal conversion in the redundant conversion cycle, and update the comparison threshold of the comparison unit based on the redundant comparison result output by the target redundant capacitor. Specifically, the control unit 3 can control the target redundant capacitor to be connected to the reference voltage or grounded during the redundant conversion cycle, and then adjust the number of capacitors connected to the reference voltage in the positive terminal capacitor array during the conversion cycle and their weights, that is, update the value of k, so that the comparison threshold of the comparison unit 2 can be updated.

[0090] When the above redundant calibration circuit is used for analog-to-digital conversion, the same process of sampling, holding, quantization, encoding, etc. is also performed. Figure 2b In the sampling process, switches S1, S2, S5, and S6 are closed, and the analog signal is collected in the upper plates of Cip and Cim, and enters the conversion process after being kept for a period of time. In the conversion process, switches S1, S2, S5, and S6 are opened, and switches S3 and S4 are closed. The upper plates of Cip and Cim are disconnected from the analog signal and short-circuited, so that the collected analog signal is stored in the lower plate, and enters the first conversion cycle.

[0091] In the first conversion cycle, the control unit 3 controls the switch between C3p and the first sub-receiving end to close, so that the upper plate of C3p is connected to the reference voltage, and then the comparison unit 2 obtains the SJP and SJM of the first conversion cycle and outputs the comparison result and its digital code value b3, and enters the second conversion cycle after obtaining the digital code value b3.

[0092] In the second conversion cycle, the control unit 3 controls the switch between C3p and the first sub-receiving end to close or open, and controls the switch between C3p and the second sub-receiving end to close or open according to the value of b3, so that the upper plate of C3p maintains access to the reference voltage or switches to ground. At the same time, the switch between C2p and the first sub-receiving end is controlled to close, so that the upper plate of C2p is connected to the reference voltage. The comparison unit 2 outputs the digital code value b2 of the second conversion cycle, and so on. Similar operations are repeated in the third conversion cycle and the fifth conversion cycle to obtain the digital signal after analog-to-digital conversion.

[0093] In an embodiment of the present invention, when there is a deviation in the comparison result, the redundancy calibration circuit can cause the control unit 3 to determine the target redundant capacitance and enter a redundant conversion cycle to compensate for the deviation in the comparison result.

[0094] For example, the digital code value of the third conversion cycle can be compared with the digital code value of the fourth conversion cycle. When the digital code value of the third conversion cycle is equal to the digital code value of the fourth conversion cycle, it is determined that there is a deviation in the comparison result, and then the target redundant capacitor is determined from all redundant capacitors, such as Figure 2bIn the embodiment, the target redundant capacitor is determined from C1mr and C1pr, and in the fifth conversion cycle, the target redundant capacitor is controlled to access the reference voltage, and the comparison result and its digital code value are output.

[0095] Specifically, when the digital code value of the third conversion cycle is 0, the fifth conversion cycle can be a redundant conversion cycle, and when the digital code value of the third conversion cycle is 1, the fourth conversion cycle can be a redundant conversion cycle. When the digital code value of the third conversion cycle is 0, it can be determined that the comparison threshold needs to be moved down to compensate for the deviation of the comparison result, and then C1mr can be determined as the target redundant capacitor, and when the digital code value of the third conversion cycle is 1, it can be determined that the comparison threshold needs to be moved up to compensate for the deviation of the comparison result, and then C1pr can be determined as the target redundant capacitor.

[0096] See also Figure 3 , Figure 3 FIG. 4 shows a calibration effect diagram of a redundant calibration circuit provided by an embodiment of the present invention, such as Figure 3 As shown, a comparison error occurs in the second conversion cycle, and then when a comparison error occurs in the second conversion cycle, a redundant conversion cycle is executed after the next conversion cycle is executed. When executing the redundant conversion cycle, the control unit can control the upper plates of C1mr and C0p to access the reference voltage, and then the signal range and the comparison threshold can be shifted down by the unit corresponding to the weight of the redundant conversion cycle. The comparison unit compares the analog signal with the comparison threshold of the redundant conversion cycle, outputs the redundant comparison result and its corresponding redundant digital code value b1r, and outputs the digital signal 10001 in combination with b1r. It can be specifically expressed by the following formula:

[0097] Dout=2^3*b3+2^2*b2+2^1*b1+2^0*b0-2^1*xnor(b1,b1r)wherein, xnor refers to the exclusive OR operation. When b1=b1r, xnor outputs 1, that is, xnor(b1,b1r)=1. When b1≠b1r, xnor outputs 0, that is, xnor(b1,b1r)=0. Specifically, when calculating the decimal number corresponding to the digital signal, the digital code value corresponding to the negative redundant capacitor needs to be subtracted.

[0098] In an embodiment of the present invention, a redundant calibration circuit is constructed, wherein the redundant calibration circuit includes: a capacitor array, including at least one positive redundant capacitor, at least one negative redundant capacitor and at least one conversion capacitor, the positive redundant capacitor and the negative redundant capacitor are used to output redundant calibration signals, and the conversion capacitor is used for analog signal conversion; a comparison unit connected to the capacitor array and used to determine a redundant comparison result, the redundant comparison result is determined based on the redundant calibration signal; a control unit connected to the capacitor array and the comparison unit, used to determine a target redundant capacitor in the capacitor array, and update a comparison threshold of the comparison unit based on the redundant comparison result, the redundant comparison result is determined by the comparison unit based on the redundant calibration signal output by the target redundant capacitor, so that when there is a deviation in the comparison result, the target redundant capacitor is determined by the control unit, and the comparison threshold of the comparison unit is updated based on the redundant comparison result determined by the target redundant capacitor output, so that the comparison unit performs a third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation of the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit.

[0099] See also Figure 4 , Figure 4 A flowchart of a redundant calibration method provided by an embodiment of the present invention is shown. The redundant calibration method can be applied to a redundant calibration circuit. The redundant calibration circuit may include a comparison unit and a control unit. The redundant calibration method may specifically include the following steps:

[0100] Step 401 : when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion period based on the analog signal, and generates a second digital code value corresponding to a second conversion period.

[0101] The first conversion cycle may be a conversion cycle among all conversion cycles except the redundant conversion cycle and before the redundant conversion cycle is executed, and the second conversion cycle may be the redundant conversion cycle.

[0102] After the analog signal is collected, it is necessary to perform analog-to-digital conversion on the analog signal for the purpose of digital processing or communication confidentiality. When converting the analog signal, the comparison unit can output a first digital code value based on the analog signal in a first conversion cycle and output a second digital code value based on the analog signal in a second conversion cycle.

[0103] Step 402: If the control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit updates a comparison threshold of the comparison unit.

[0104] The redundant calibration condition may be a condition for determining whether redundant calibration is required, that is, determining whether there is a deviation in the comparison result that requires compensation.

[0105] After obtaining the first digital code value and the second digital code value, the control unit can obtain the first digital code value and the second digital code value, and then determine whether the redundant calibration condition is met based on the first digital code value and the second digital code value, and update the comparison threshold of the comparison unit when the control unit determines that the redundant calibration condition is met based on the first digital code value and the second digital code value.

[0106] In an embodiment of the present application, the redundant calibration circuit may further include a capacitor array, and the control unit updating the comparison threshold of the comparison unit in step 402 may include steps 4021 to 4022:

[0107] Step 4021: The control unit determines a target redundant capacitor from the capacitor array according to the first digital code value.

[0108] The target redundant capacitor may be a redundant capacitor among all redundant capacitors in the capacitor array that is used to perform analog signal conversion in a redundant conversion cycle.

[0109] After obtaining the first digital code value, the control unit may determine the target redundant capacitor from the capacitor array according to the first digital code value.

[0110] In an embodiment of the present application, the capacitor array may include at least one positive redundant capacitor and at least one negative redundant capacitor. The target redundant capacitor may be determined from the capacitor array in the following manner:

[0111] The control unit determines whether the first digital code value is a target code value, and when the first digital code value is the target code value, determines a target positive-end redundant capacitor corresponding to the second conversion period from all positive-end redundant capacitors, and when the first digital code value is not a target code value, determines a target negative-end redundant capacitor corresponding to the second conversion period from all negative-end redundant capacitors.

[0112] Among them, the target code value can be the digital code value corresponding to the analog signal being greater than the comparison threshold, the target positive-end redundant capacitor can be the redundant capacitor among all the positive-end redundant capacitors in the capacitor array used to perform analog signal conversion in the second conversion cycle, and the target negative-end redundant capacitor can be the redundant capacitor among all the negative-end redundant capacitors in the capacitor array used to perform analog signal conversion in the second conversion cycle.

[0113] After obtaining the first digital code value, the control unit can determine whether the first digital code value is a target code value. When the first digital code value is a target code value, the target positive terminal redundant capacitor corresponding to the second conversion cycle can be determined from all positive terminal redundant capacitors.

[0114] In practical applications, since the positive terminal redundant capacitor can be set between every two positive terminal conversion capacitors, the positive terminal redundant capacitor between the positive terminal conversion capacitor corresponding to the first conversion cycle and the positive terminal conversion capacitor corresponding to the next conversion cycle can be determined as the target positive terminal redundant capacitor.

[0115] When the first digital code value is a non-target code value, a target negative terminal redundant capacitor corresponding to the second conversion period may be determined from all negative terminal redundant capacitors.

[0116] In practical applications, since the negative redundant capacitor can be set between every two negative conversion capacitors, the negative redundant capacitor between the negative conversion capacitor corresponding to the first conversion cycle and the negative conversion capacitor corresponding to the next conversion cycle can be determined as the target negative redundant capacitor.

[0117] Step 4022: Update the comparison threshold of the comparison unit according to the target redundant capacitance.

[0118] When the target redundant capacitance is determined and the redundant calibration condition is satisfied, the control unit may update the comparison threshold of the comparison unit based on the redundant comparison result determined by the target redundant capacitance output.

[0119] In an embodiment of the present application, step 4022 may also be performed in the following manner:

[0120] When the first digital code value is the target code value, the control unit connects the target positive redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal. When the first digital code value is a non-target code value, the control unit connects the target negative redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal.

[0121] The third conversion cycle may be a conversion cycle among all conversion cycles except the redundant conversion cycle and after the redundant conversion cycle is executed, and the reference signal may be a reference voltage.

[0122] When the target redundant capacitor is determined, the redundant calibration condition is met, and the first digital code value is the target code value, the control unit can control the target positive redundant capacitor to be connected to the reference voltage, and then adjust the number of capacitors in the positive capacitor array connected to the reference voltage and their weights in the second conversion cycle, that is, update the value of k, so that the comparison threshold of the comparison unit can be updated.

[0123] When the target redundant capacitance is determined, the redundant calibration conditions are met, and the first digital code value is a non-target code value, the control unit can control the target negative redundant capacitance to be connected to the reference voltage, and then adjust the weight of the reference voltage connected to the positive capacitance array in the second conversion cycle, that is, update the value of k, so that the comparison threshold of the comparison unit can be updated.

[0124] In an embodiment of the present application, before step 402, the following steps may also be included:

[0125] The control unit compares the first digital code value with the second digital code value, and determines that the redundant calibration condition is not satisfied when the first digital code value is not equal to the second digital code value, and determines that the redundant calibration condition is satisfied when the first digital code value is equal to the second digital code value.

[0126] After obtaining the first digital code value and the second digital code value, the control unit can compare the first digital code value with the second digital code value. When the first digital code value is not equal to the second digital code value, it can be explained that the weight corresponding to the redundant capacitor is greater than the difference between the analog signal and the unupdated comparison threshold, that is, the error between the erroneous comparison result and the correct comparison result is within the range that can be compensated by the redundant conversion cycle, and there is no need to perform redundant calibration, and it is determined that the redundant calibration condition is not met.

[0127] It should be understood that during a redundant conversion cycle, the signal range and the comparison threshold can be shifted up by a unit corresponding to the weight of the redundant conversion cycle by accessing the reference signal, that is, the comparison threshold of the comparison unit is updated.

[0128] When the first digital code value is equal to the second digital code value, it can be explained that the digital code value output after the comparison threshold is updated is equal to the digital code value after the comparison threshold is not updated, that is, the error between the erroneous comparison result and the correct comparison result is greater than the range that can be compensated by the redundant conversion cycle, and then redundant calibration is required to determine that the redundant calibration conditions are met.

[0129] As an example, when determining that the digital code value corresponding to any first conversion cycle is the target code value, the control unit can also ground the positive conversion capacitor in the next first conversion cycle of the first conversion cycle, and determine whether the first digital code value corresponding to the next first conversion cycle is equal to the target code value. When it is determined that the first digital code value corresponding to the next first conversion cycle is equal to the target code value, it means that the error between the erroneous comparison result and the correct comparison result is greater than the range that can be compensated by the redundant conversion cycle, and then redundant calibration is required to determine that the redundant calibration conditions are met. When they are not equal, it means that the error between the erroneous comparison result and the correct comparison result is within the range that can be compensated by the redundant conversion cycle, and then there is no need to perform redundant calibration, and it is determined that the redundant calibration conditions are not met.

[0130] Step 403: the comparison unit executes a third conversion cycle based on the updated comparison threshold.

[0131] After the comparison threshold of the comparison unit is updated, the comparison unit may perform a conversion cycle after the redundant conversion cycle based on the updated comparison threshold until the digital signal is output.

[0132] In an embodiment of the present invention, when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion cycle based on the analog signal, and generates a second digital code value corresponding to a second conversion cycle. If the control unit determines that a redundant calibration condition is met based on the first digital code value and the second digital code value, the control unit updates the comparison threshold of the comparison unit, and the comparison unit executes a third conversion cycle based on the updated comparison threshold, so that when there is a deviation in the comparison result, the control unit updates the comparison threshold of the comparison unit through the determined redundant comparison result, so that the comparison unit executes the third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation in the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit.

[0133] See also Figure 5 , Figure 5 A flowchart of another redundant calibration method provided by an embodiment of the present invention is shown, which may specifically include the following steps:

[0134] Step 501 : when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion period based on the analog signal, and generates a second digital code value corresponding to a second conversion period.

[0135] Step 502: If the control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit determines whether the second digital code value is a target code value.

[0136] Step 503, when the first digital code value is the target code value, determine the target positive end redundant capacitor corresponding to the second conversion period from all positive end redundant capacitors, and when the first digital code value is not the target code value, determine the target negative end redundant capacitor corresponding to the second conversion period from all negative end redundant capacitors.

[0137] Step 504, when the first digital code value is the target code value, the control unit connects the target positive redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal; when the first digital code value is a non-target code value, the control unit connects the target negative redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal.

[0138] For the related descriptions of steps 501 to 504, please refer to steps 401 to 402, and steps 4021 to 4022, and they will not be repeated here.

[0139] In an embodiment of the present application, in step 504, when the first digital code value is a non-target code value, the control unit connects the target negative terminal redundant capacitor to the reference signal, and the method of updating the comparison threshold of the comparison unit based on the reference signal and the analog signal may also include steps 5041 to 5043:

[0140] Step 5041: The control unit determines a target positive terminal conversion capacitor corresponding to the second conversion cycle from all conversion capacitors.

[0141] The target positive terminal conversion capacitor may be a positive terminal conversion capacitor corresponding to a conversion cycle after the original first conversion cycle.

[0142] When the first digital code value is not a target code value, the control unit may determine a target positive terminal conversion capacitor corresponding to the second conversion period from all conversion capacitors.

[0143] In practical applications, the control unit can determine the positive end conversion capacitor corresponding to the next conversion cycle as the target positive end conversion capacitor from all conversion capacitors when the current conversion cycle is completed and it is determined that the next conversion cycle needs to execute a redundant conversion cycle.

[0144] Step 5042: Connect the target negative-end redundant capacitor and the target positive-end conversion capacitor to the reference signal to generate a weight coefficient corresponding to the second conversion period.

[0145] The weight coefficient may be a weight value determined based on the number of capacitors connected to the reference voltage in the positive terminal capacitor array in the second conversion period and their weights.

[0146] After determining the target positive-end conversion capacitor, the control unit can connect the target negative-end redundant capacitor and the target positive-end conversion capacitor to the reference signal, and determine the number of capacitors in the positive-end capacitor array connected to the reference voltage and their weights in the second conversion cycle, and then calculate the weight coefficient based on the number of all capacitors connected to the reference voltage and their weights.

[0147] In practical applications, the control unit can control the switch between the reference voltage and the target negative redundant capacitor to close, so that the target negative redundant capacitor is connected to the reference voltage, and control the switch between the reference voltage and the target positive conversion capacitor to close, so that the target positive conversion capacitor is connected to the reference voltage.

[0148] Step 5043, updating the comparison threshold of the comparison unit according to the weight coefficient to obtain the target comparison unit.

[0149] The target comparison unit may be a comparison unit after the comparison threshold is updated.

[0150] After obtaining the weight coefficient, the weight of the reference voltage connected to the positive terminal capacitor array in the second conversion cycle can be adjusted based on the weight coefficient, that is, the value of k is updated, so that the comparison threshold of the comparison unit can be updated to obtain the comparison unit after the comparison threshold is updated.

[0151] Step 505 : The comparison unit executes a third conversion cycle based on the updated comparison threshold.

[0152] For the relevant description of step 505, please refer to step 403 and will not be repeated here.

[0153] In an embodiment of the present invention, when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion cycle based on the analog signal, and generates a second digital code value corresponding to a second conversion cycle. If the control unit determines that the redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit determines whether the second digital code value is a target code value. When the first digital code value is a target code value, a target positive redundant capacitor corresponding to the second conversion cycle is determined from all positive redundant capacitors. When the first digital code value is a non-target code value, a target negative redundant capacitor corresponding to the second conversion cycle is determined from all negative redundant capacitors. When the first digital code value is a target code value, the control unit sets the target positive redundant capacitor to the target positive redundant capacitor. The capacitor is connected to a reference signal, and the comparison threshold of the comparison unit is updated based on the reference signal and the analog signal. When the first digital code value is a non-target code value, the control unit connects the target negative redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal. The comparison unit performs a third conversion cycle based on the updated comparison threshold, so that when there is a deviation in the comparison result, the control unit updates the comparison threshold of the comparison unit through the determined redundant comparison result, so that the comparison unit performs a third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation of the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit.

[0154] See also Figure 6 , Figure 6 An example flow chart of a redundant calibration method provided by an embodiment of the present invention is shown, which may specifically include the following steps:

[0155] S1, process starts;

[0156] S2, determine whether the digital code value bir corresponding to the first conversion period is 1, if so, execute step S3, if not, execute step S4;

[0157] S3, determining to enter the second conversion cycle, and controlling the positive redundant capacitor corresponding to the second conversion cycle to access the reference voltage, and executing step S5;

[0158] S4, determine the positive terminal conversion capacitor corresponding to the next first conversion period and ground it, and execute step S6;

[0159] S5, determining whether the digital code value bir corresponding to the second conversion period is 1, if so, executing step S7, if not, executing step S8;

[0160] S6, determine whether the digital code value bir corresponding to the next first conversion cycle is 1, if so, execute step S9, if not, execute step S10;

[0161] S7. Determine the digital code value corresponding to the third conversion period, and calculate the digital signal according to all the digital code values.

[0162] Specifically, when the digital code value corresponding to the first conversion cycle is equal to the digital code value corresponding to the second conversion cycle, it can be determined that the redundant calibration condition is met, and then it is necessary to control the positive terminal conversion capacitor corresponding to the third conversion cycle to access the reference voltage, and calculate the digital signal by the following formula:

[0163] Dout=Dout+2 i

[0164] Among them, i can be the weight value corresponding to the redundant capacitor, and Dout can be a digital signal. For details, please refer to the above formula of the digital signal.

[0165] S8. Determine the digital code value corresponding to the third conversion period, and calculate the digital signal according to all the digital code values.

[0166] Specifically, when the digital code value corresponding to the first conversion cycle is not equal to the digital code value corresponding to the second conversion cycle, it can be determined that the redundant calibration condition is not satisfied, and then there is no need to control the positive terminal conversion capacitor corresponding to the third conversion cycle to access the reference voltage, and the digital signal can be directly calculated by the following formula:

[0167] Dout=Dout

[0168] S9. Determine the digital code value corresponding to the third conversion period, and calculate the digital signal according to all the digital code values.

[0169] Specifically, when the digital code values ​​corresponding to two adjacent first conversion cycles are not equal, it can be determined that the redundant calibration condition is not satisfied, and there is no need to control the negative redundant capacitor corresponding to the second conversion cycle to access the reference voltage, and control the positive conversion capacitor corresponding to the original next first conversion cycle to access the reference voltage, and the digital signal can be directly calculated by the following formula:

[0170] Dout=Dout

[0171] S10, determining the digital code value corresponding to the second conversion period, and calculating the digital signal according to all the digital code values.

[0172] Specifically, when the digital code values ​​corresponding to two adjacent first conversion cycles are equal, it can be determined that the redundant calibration condition is met, and then it is necessary to control the negative redundant capacitor corresponding to the second conversion cycle to access the reference voltage, and control the positive conversion capacitor corresponding to the original next first conversion cycle to access the reference voltage, and calculate the digital signal by the following formula:

[0173] Dout=Dout-2 i

[0174] S11. End the process.

[0175] In an embodiment of the present invention, when converting an analog signal, a comparison unit generates a first digital code value corresponding to a first conversion cycle based on the analog signal, and generates a second digital code value corresponding to a second conversion cycle. If the control unit determines that a redundant calibration condition is met based on the first digital code value and the second digital code value, the control unit updates the comparison threshold of the comparison unit, and the comparison unit executes a third conversion cycle based on the updated comparison threshold, so that when there is a deviation in the comparison result, the control unit updates the comparison threshold of the comparison unit through the determined redundant comparison result, so that the comparison unit executes the third conversion cycle based on the updated comparison threshold, and outputs a digital signal after compensating for the deviation in the comparison result, thereby improving the accuracy of encoding the analog signal and improving the reliability of compensation based on the redundant circuit.

[0176] Reference Figure 7 , Figure 7 A structural block diagram of a terminal device provided in one embodiment of the present application is shown, wherein the terminal device 71 comprises: at least one processor 711, a memory 712, and a computer program 7121 stored in the memory 712 and executable on the at least one processor 711, wherein the processor 711 implements the steps in any of the above-mentioned method embodiments when executing the computer program 7121.

[0177] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any one of the above method embodiments can be implemented.

[0178] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0179] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the camera device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium.

[0180] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A redundant calibration circuit, characterized in that: The redundant calibration circuit comprises: A capacitor array, comprising at least one positive redundant capacitor, at least one negative redundant capacitor and at least one conversion capacitor, wherein the positive redundant capacitor and the negative redundant capacitor are used to output redundant calibration signals, and the conversion capacitor is used for analog signal conversion; a comparison unit connected to the capacitor array, and configured to determine a redundant comparison result when a redundant calibration condition is met, wherein the redundant comparison result is determined based on the redundant calibration signal; wherein the comparison unit is further configured to generate a comparison result between an output signal of the capacitor array and a reference signal and a corresponding digital code value thereof, wherein the redundant calibration condition is a condition for determining whether redundant calibration is required; a control unit connected to the capacitor array and the comparison unit, configured to determine a target redundant capacitor in the capacitor array, and update a comparison threshold of the comparison unit based on the redundant comparison result, wherein the redundant comparison result is determined by the comparison unit based on a redundant calibration signal output by the target redundant capacitor; wherein the target redundant capacitor is a redundant capacitor used to perform analog signal conversion in a redundant conversion cycle among all redundant capacitors in the capacitor array; Wherein, the control unit is further used to determine the target redundant capacitor from the capacitor array according to the first digital code value, and update the comparison threshold of the comparison unit according to the target redundant capacitor; the control unit is also used to determine whether the first digital code value is the target code value; when the first digital code value is the target code value, determine the target positive redundant capacitor corresponding to the second conversion cycle from all the positive redundant capacitors, and when the first digital code value is not the target code value, determine the target negative redundant capacitor corresponding to the second conversion cycle from all the negative redundant capacitors; the control unit is also used to connect the target positive redundant capacitor to the reference signal when the first digital code value is the target code value, and update the comparison threshold of the comparison unit based on the reference signal and the analog signal, and when the first digital code value is not the target code value, connect the target negative redundant capacitor to the reference signal, and update the comparison threshold of the comparison unit based on the reference signal and the analog signal; Wherein, the target code value is a digital code value corresponding to when the analog signal is greater than the comparison threshold of the comparison unit; The capacitor array further includes a first receiving end and a second receiving end, wherein the first receiving end is used to obtain a reference voltage, and the second receiving end is grounded; The control unit is further configured to control the target redundant capacitor to be connected to the first receiving end or the second receiving end, so as to update a comparison threshold of the comparison unit.

2. A redundant calibration method, characterized in that: The method is applied to a redundant calibration circuit, the redundant calibration circuit includes a comparison unit, a control unit, and a capacitor array, and the method includes: When converting the analog signal, the comparison unit generates a first digital code value corresponding to a first conversion period based on the analog signal, and generates a second digital code value corresponding to a second conversion period; If the control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, the control unit updates a comparison threshold of the comparison unit; The comparison unit performs a third conversion cycle based on the updated comparison threshold; The control unit updates the comparison threshold of the comparison unit, including: The control unit determines a target redundant capacitor from the capacitor array according to the first digital code value; Updating a comparison threshold of the comparison unit according to the target redundant capacitance; The capacitor array includes at least one positive redundant capacitor and at least one negative redundant capacitor, and the control unit determines a target redundant capacitor from the capacitor array according to the first digital code value, including: The control unit determines whether the first digital code value is a target code value; wherein the target code value is a digital code value corresponding to when the analog signal is greater than a comparison threshold of the comparison unit; When the first digital code value is a target code value, determining a target positive terminal redundant capacitor corresponding to the second conversion period from all the positive terminal redundant capacitors; When the first digital code value is not the target code value, determining a target negative terminal redundant capacitor corresponding to the second conversion period from all the negative terminal redundant capacitors; Wherein, updating the comparison threshold of the comparison unit according to the target redundant capacitance includes: When the first digital code value is a target code value, the control unit connects the target positive-end redundant capacitor to a reference signal, and updates a comparison threshold of the comparison unit based on the reference signal and the analog signal; When the first digital code value is not the target code value, the control unit connects the target negative-end redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal.

3. The redundant calibration method according to claim 2, characterized in that: The redundant calibration circuit further includes a conversion capacitor, the conversion capacitor includes at least one positive end conversion capacitor, the control unit connects the target negative end redundant capacitor to the reference signal, and updates the comparison threshold of the comparison unit based on the reference signal and the analog signal, including: The control unit determines a target positive terminal conversion capacitance corresponding to the second conversion period from all the conversion capacitances; Connecting the target negative-end redundant capacitor and the target positive-end conversion capacitor to the reference signal to generate a weight coefficient corresponding to the second conversion period; The comparison threshold of the comparison unit is updated according to the weight coefficient to obtain a target comparison unit.

4. The redundant calibration method according to claim 2 or 3, characterized in that: If the control unit determines that a redundant calibration condition is satisfied based on the first digital code value and the second digital code value, before the control unit updates the comparison threshold of the comparison unit, the method further includes: The control unit compares the first digital code value with the second digital code value; When the first digital code value is not equal to the second digital code value, determining that the redundant calibration condition is not satisfied; When the first digital code value is equal to the second digital code value, it is determined that the redundant calibration condition is satisfied.

5. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 2 to 4 is implemented.

6. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 2 to 4 is implemented.

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