A FLASH control method and controller for a system-on-chip suitable for multiple process platforms

Abstract

The present invention relates to a FLASH control method and a controller for a system on a chip applicable to a multi-process platform. The method comprises: step S1: after the chip is powered on, the FLASH controller is initialized; step S2: when different application instructions are received, the corresponding state machine and sub-state machine are started to complete the operation function of the Flash; step S3: after the application instruction from the chip is executed, the master control module returns to the idle state and waits for receiving the next application instruction; the present invention can design a test circuit by using the control mechanism of the master control state machine and the sub-state machine group to realize the function of performing corresponding tests on the FLASH in the test mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of FLASH controllers, and in particular relates to a FLASH control method and a controller thereof for a system on a chip applicable to a multi-process platform. Background Art

[0002] Flash memory (FLASH) is an electrically erasable non-volatile semiconductor memory. Flash memory has become very popular in the field of embedded devices due to its high storage density, low power consumption, no data loss during power failure, and good shock resistance. In recent years, as the storage density of flash memory has further increased, the single-chip storage capacity has reached more than 8G bytes, so it has gradually replaced traditional disks in many occasions. This also puts higher requirements on the performance of FLASH controllers. In order to better meet the storage performance requirements of computer systems, it is urgent to design a higher-speed flash memory controller.

[0003] The command sets of FLASH chips produced by different process platforms are not exactly the same. Even the command sets of different models of FLASH on the same process platform are not exactly the same. This requires the FLASH controller to be compatible with various commands. When performing functional testing on the FLASH controller, a FLASH controller test platform is built to verify the FLASH controller's ability to parse the FLASH operation instructions sent by the central processor and send the FLASH operation instructions to the off-chip FLASH chip. Due to the different process technologies of various process platform factories, the FLASH interfaces provided by various process platform factories are not unified. Therefore, it is difficult to achieve mutual compatibility when designing FLASH controllers, resulting in the need to redesign FLASH controllers when changing processes between different process platforms. In addition, FLASH must complete several test programs before leaving the factory to calibrate the configuration parameters of FLASH. However, the process platform often does not provide a test control circuit; so how to make the process platform transparent and applicable without reducing the control efficiency is a technical problem to be solved.

[0004] The present invention proposes a FLASH controller structure suitable for transplantation on multiple process platforms. When changing the process, only the underlying sub-state machine needs to be changed, and the upper-level control logic and registers can be kept unchanged to the maximum extent, effectively reducing the development difficulty and time of redesigning the FLASH controller when changing the process. The present invention uses the control mechanism of the master control state machine and the sub-state machine group to design the test circuit, realizes the function of performing corresponding tests on the FLASH in the test mode, and greatly improves the scalability and compatibility on the basis of transparent applicability. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention proposes a FLASH control method and a controller for a system on a chip applicable to a multi-process platform, wherein the controller comprises: an upper layer application control module and a lower layer interface control module;

[0006] The upper layer application control module includes an application interface, a register module, a state machine group and a master control module thereof; the upper layer application control module is set in a test terminal or a user terminal in an updateable manner;

[0007] The updateable mode is performed in a software configurable mode; a version number is set to support the updateable mode; in a lower version number, the lower interface control module is configured with a first sub-state machine group; in a higher version number, the lower interface control module is configured with a second sub-state machine group or a first sub-state machine group and a second sub-state machine group; as the version number increases, the number of sub-state machine groups is expandable;

[0008] The register module is used to convert the test task into the state machine usage sequence of the state machine group; it is also used to save the configuration information of the state machine group;

[0009] The state machine group includes one or more state machines, and the state machines in the state machine group are controlled by the master control module; each state machine in the state machine group includes one or more states, and after each reconfiguration, the state machines included in the state machine group and the state transition relationship of each state machine are the same or different;

[0010] The master control module starts or operates the state machine group in the master control module based on the application command, and schedules and controls the corresponding sub-state machine modules through the use of the state machine; specifically: the master control module starts each state machine in sequence based on the state machine use sequence corresponding to the test task; during the use of each state machine in the state machine use sequence, the sub-state machine number is sent to the lower layer interface control module in sequence according to the state entered in real time by each state machine; the states sent in sequence constitute a sub-state machine number sequence; the sub-state machine with the sub-state machine number is started based on the sub-state machine number sequence; until all state machines in the sequence are used up or fail to be used;

[0011] The lower layer interface control module comprises a sub-state machine group module and a FLASH interface signal module; after receiving the sub-state machine number signal, the lower layer interface control module drives the sub-state machine corresponding to the sub-state machine number; the sub-state machines belong to the same or different sub-state machine groups;

[0012] The sub-state machine group module is configured as a first sub-state machine group and a second sub-state machine group; the first sub-state machine group is a state machine group divided according to FLASH functions, and each sub-state machine therein corresponds to a FLASH function; the second sub-state machine group is a state machine group divided according to FLASH process platform type, and each sub-state machine therein corresponds to a FLASH process platform type; each sub-state machine in the sub-state machine group is used to send a timing signal related to its state transition after being driven based on its own configuration information, thereby completing an operation process consisting of one or more operations;

[0013] The FLASH interface signal module is used to connect one or more FLASH arrays.

[0014] Furthermore, the updateable mode is carried out by cooperating between a software configurable mode and a hardware updateable mode.

[0015] Furthermore, the one or more FLASH arrays operate and communicate in parallel when connected in parallel.

[0016] Furthermore, the sub-state machines in the first and second sub-state machine groups are numbered consecutively.

[0017] Furthermore, the state machine and sub-state machine are both finite state machines.

[0018] A FLASH control method for a system on a chip applicable to multiple process platforms based on the FLASH controller of the system on a chip applicable to multiple process platforms, the method comprising:

[0019] Step S1: After the chip is powered on, the FLASH controller is initialized; Step S2: When different application instructions are received, the corresponding state machine and sub-state machine are started to complete the operation function of the Flash; Step S3: After the application instruction is executed, the master control module returns to the idle state and waits to receive the next application instruction.

[0020] Furthermore, the application instruction comes from a chip of a test terminal or a user terminal.

[0021] A processor, characterized in that the processor is used to run a program, wherein when the program is running, the FLASH control method of the system on chip applicable to a multi-process platform is executed.

[0022] A programmable logic array, when programmed, executes the above-mentioned FLASH control method of the system on chip applicable to multiple process platforms.

[0023] A chip, characterized in that it includes a processor, the processor is coupled to a memory, the memory stores program instructions, and when the program instructions stored in the memory are executed by the processor, the FLASH control method of the on-chip system applicable to a multi-process platform is implemented.

[0024] The beneficial effects of the present invention include:

[0025] (1) By modifying the configuration of the state machine and expanding the sub-state machine group module, the FLASH control of multiple process platforms can be supported; by reconfiguring the software, different process platforms can be supported to the maximum extent, and by reconfiguring the sub-state machines in multiple dimensions, the differentiated changes of multiple process platforms can be supported with minimal software and hardware overhead;

[0026] (2) Through dynamic configuration, the correspondence between the application instructions and the state machine usage sequence of the state machine group and the update of the configuration information of the state machine group are realized, thereby supporting the two-way compatibility and expansion of multiple process platforms and diversified application instructions; further, through this hierarchical update method, when the configuration information of the state machine group changes, the correspondence between each state and the sub-state machine in each state machine is dynamically changed, and the functional configuration of the state machine and its state is updateable, so that the use of the sub-state machine and its use method can be changed on the upper control module side. In the case of hardware transparency, the old function implementation method of the same process platform can be upgraded, and it can also be simply compatible with different process platforms; the dynamic configuration overhead of the controller is greatly reduced and more flexible;

[0027] (3) It supports transparent update configuration of sub-state machine groups, so that the sub-state machine groups can be set up and configured from multiple dimensions. In the two special cases where the applicable process platform types are limited or the applicable process platform types are large and there are high-frequency operations, the execution path length of the involved FLASH operations is shortened by expanding the dimensions of the state machine group, thereby improving the overall access efficiency of the FLASH. Furthermore, the sub-state machine group can be easily expanded by dynamically configuring the corresponding relationship between the state and the sub-state machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings:

[0029] Figure 1 It is a schematic diagram of a FLASH controller of a system on a chip applicable to a multi-process platform of the present invention.

[0030] Figure 2 It is a schematic diagram of the FLASH control method of the system on chip applicable to multiple process platforms of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0032] As attached Figure 1 As shown, the present invention proposes a FLASH controller for a system on a chip applicable to a multi-process platform, the controller comprising an upper layer application control module and a lower layer interface control module;

[0033] The upper layer application control module includes an application interface, a register module, a state machine group and a master control module thereof; the upper layer application control module is set in a test terminal or a user terminal in an updateable manner;

[0034] Preferably: a version number is set to support the updateable mode; for example: a version number is set in the upper-layer application control module, and the configuration mode of the upper-layer interface control module and the lower-layer interface control module is determined according to the version corresponding to the version number; for example: a configuration mode in which a state machine group Configuration A is configured in the upper-layer interface control module, and a configuration mode in which a sub-state machine group Configuration B is configured in the lower-layer interface control module;

[0035] Preferably, the updateable mode is performed in a software configurable manner, for example, installation and setting by means of an application or a driver;

[0036] Replaceable: The updateable mode is implemented in a hardware configurable manner, for example, by using a programmable array or memory;

[0037] Preferably: the updateable mode is a hierarchical update mode, and the hierarchical update mode is: fully updateable or hierarchical partially updateable mode; all updates can be made in an overwrite manner (such as: fully updating the upper interface control module); hierarchical partial updates include: reconfiguring the register content in the register module to update the correspondence between the application instruction and the state machine group, and the configuration mode of each state machine in the state machine group; the configuration mode of the state machine includes the states contained in the state machine and their state transition relationship; or only modifying the functional configuration of all or part of the states in part or all of the state machines to modify the sub-state machines started in this state and their startup sequence; obviously, the simplest effect of this modification is to upgrade the implementation mode of the FLASH function. Through this hierarchical update mode, the old function implementation mode of the same process platform can be upgraded, and it can also be simply compatible with different process platforms;

[0038] Preferably: by modifying the configuration mode of the state machine, the states contained in the state machine and their state transition relationships are modified, so that after the modification, the sub-state machines and their startup sequence generated by the same numbered state machine in the conversion process are different, so that when the process platform change does not require the expansion of the FLASH function, that is, when the new process platform can be completed by the existing FLASH function expansion, the configuration mode of the state machine is modified; the state machine can support the new state transition sequence, so that the sub-state machine numbering sequence corresponding to the new state transition sequence can support the new process platform (corresponding to the new instruction); at this time, there is no need to expand the sub-state machine group; that is, by changing the configuration mode, the first sub-state machine group can support most process platform expansion changes; especially for the generation change of the same process platform, the underlying logic is not changed, only the driving sequence of the sub-state machine is changed; when the change of the process platform cannot be supported by the change of the sub-state machine driving sequence, the sub-state machine group at the hardware level is changed, and the second sub-state machine group is updated so that the sub-state machine in the second sub-state machine group can support the new process platform type; the FLASH change of complex multi-process platforms is supported by the reconfiguration of software and hardware in coordination;

[0039] Of course, when the first sub-state machine group, the second sub-state machine group, and the third sub-state machine group are simulated and implemented by software, the configuration method of the sub-state machine group is modified by software. Of course, this will bring higher flexibility. However, in fact, because the state machine group is displayed by software, the flexibility is already very high;

[0040] Preferably: the first sub-state machine group is set in an unmodifiable storage medium; and a programmable storage medium is set to accommodate the second sub-state machine group, the third sub-state machine group, etc.; thereby supporting hardware-level update support with limited hardware overhead;

[0041] Preferably, the sub-state machine in the first sub-state machine and the sub-state machine in the second sub-state machine work independently or cooperate with each other; that is, the state machine can continuously issue sub-state machines across different sub-state machine groups so that the sub-state machines in two different sub-state machine groups can cooperate with each other; of course, through the reconfiguration of the sub-state machine group, the sub-state machine numbers issued by it may correspond to different FLASH operations;

[0042] Preferably: the numbers of the sub-state machines in the second sub-state machine group and the numbers of the sub-state machines in the first sub-state machine group are consecutively numbered, so that seamless expansion can be performed;

[0043] Preferably: in a lower version number, the lower layer interface control module is configured with a first sub-state machine group; in a higher version number, the lower layer interface control module is configured with a second sub-state machine group or a first sub-state machine group and a second sub-state machine group; extensible, as the version number increases, the number of sub-state machine groups is extensible;

[0044] Preferably: when an update is required, a new version is downloaded to overwrite the old version, thereby updating the upper layer application control module; when the version is updated, the corresponding register group and / or state machine group will change; the register group and / or state machine group data of the old version are overwritten with the register group and state machine group data of the new version;

[0045] The application interface is used to receive application instructions, including a user interface and a test interface, which are respectively used to receive application instructions containing user instructions or test instructions; preferably: the test interface and the user interface are the same interface;

[0046] The state machine group includes one or more state machines, and the state machines in the state machine group are controlled by the master control module; each state machine in the state machine group includes one or more states, and after each reconfiguration, the state machines included in the state machine group and the state transition relationship of each state machine are the same or different;

[0047] The register module is used to convert application instructions into the state machine usage sequence of the state machine group of the corresponding master control module; it is also used to save the configuration information of the master control state machine group; specifically, the register module stores the correspondence between application instructions and the state machine usage sequence of the state machine group; the application instructions are converted into the state machine usage sequence by searching the corresponding register (for example: instruction R1 corresponds to the state machine usage sequence<NM1,NM2,NM3> , where: NM1, NM2, NM3 are the state machine numbers in the state machine group); when the master control module is initialized, each state machine is configured by reading the configuration information of the state machine group in the register module; for example: according to the configuration information, the state machine NM1 has 2 states, 11 and 12; the state of the state machine and its state transition relationship are configured according to the configuration information; that is, each time the chip is restarted, the register module will be reconfigured according to the configuration information. Therefore, after the supported process platform changes, the number of state machines in the state machine group and the corresponding relationship between them and the application instructions can be expanded; the number of the sub-state machine indicated by the state machine during the state change process can be changed after each restart, and the state transition mode of the state machine itself can also be changed; this depends on whether the sub-state machine group is updated;

[0048] The present invention realizes the correspondence between the application instruction and the state machine use sequence of the state machine group and the update of the configuration information of the state machine group through dynamic configuration, thereby supporting the two-way compatibility and expansion of multiple process platforms and diversified application instructions; further, through the hierarchical update method, when the configuration information of the state machine group changes, the correspondence between each state and the sub-state machine in each state machine is dynamically changed, and the functional configuration of the state machine and its state is updateable, so that the use of the sub-state machine and the use method can be changed on the upper control module side. In the case of hardware transparency, the old function implementation method of the same process platform can be upgraded, and different process platforms can also be simply compatible; the dynamic configuration overhead of the controller is greatly reduced and more flexible;

[0049] The master control module starts / operates the state machine group in the master control module based on the application command, and schedules and controls the corresponding sub-state machine module through the use of the state machine; specifically: after receiving the application instruction through the application interface, the master control module checks the FLASH array identifier; converts the application instruction into the state machine use sequence of the state machine group of the corresponding master control module by reading the corresponding relationship in the register module; the state machine use sequence contains one or more state machines and their use order, and each state machine in the sequence corresponds to a state machine in the master control module; the master control module starts each state machine in sequence based on the state machine use sequence; during the use of each state machine in the state machine use sequence, the sub-state machine number is sent to the lower interface control module in sequence according to the state entered in real time by each state machine; the states sent in sequence constitute the sub-state machine number sequence; because of the existence of the master control module, the upper interface control module can complete a test task, rather than just a single test instruction; that is, during the use of each state machine in the state machine use sequence, after the state machine enters the current state in real time, according to the configuration of the state, the corresponding sub-state machine number is sent to the lower interface control module to start the sub-state machine with the sub-state machine number;

[0050] The master control module checks the FLASH array identifier, specifically: the master control module is used to detect the connected FLASH array identifier, parse the application instruction to determine the FLASH array identifier targeted by the application instruction; if the targeted FLASH array identifier belongs to the connected FLASH array identifier, then continue the subsequent operation; otherwise, enter the error process;

[0051] In the process of using each state machine in the state machine use sequence, the sub-state machine number is sent to the lower interface control module in sequence according to the state entered in real time by each state machine; specifically: the master control module uses the state machine group to generate a sub-state machine number sequence; when entering a current state of a state machine, one or more operations are completed according to the functional configuration of the state, and the one or more operations include sending the corresponding sub-state machine number to the lower interface control module to start the sub-state machine with the sub-state machine number; until all state machines in the sequence are used up or fail to be used; that is, the sub-state machine number corresponding to the state NM1 in the state machine can be a sub-state machine in the first sub-state machine group or a sub-state machine in the second sub-state machine group, so as to achieve hardware transparent compatibility;

[0052] The lower layer interface control module comprises a sub-state machine group module and a FLASH interface signal module; after receiving the sub-state machine number signal, the lower layer interface control module drives the sub-state machine corresponding to the sub-state machine number; (for example: when the upper layer interface control module sends SM1, the corresponding sub-state machine SM1 is driven); as the sub-state machine is started and driven, the FLASH interface signal module sends a timing signal corresponding to the state transition of the sub-state machine, so that the sub-state machine completes the corresponding operation; if the sub-state machine cannot complete the operation process for all target addresses by starting once, the master control module will jump to the next target address, and then start the corresponding sub-state machine again through the state cycle until the whole process is completed;

[0053] Preferably: the FLASH interface signal module is used to connect one or more FLASH arrays, and the one or more FLASH arrays work and communicate in parallel when connected in parallel;

[0054] Each sub-state machine in the sub-state machine group module, when activated, forms a timing combination for completing a corresponding function or operation and sends it to the FLASH interface signal module, so that the FLASH array indicated by the FLASH array identifier can complete the specific operation involved in the corresponding application instruction;

[0055] Preferably, the lower layer interface control module is arranged in the communication interface module of the user terminal / test terminal by means of hardware; for example, it may be an independent interface module arranged between the FLASH array and the user terminal;

[0056] Preferably: the sub-state machine group module is dynamically configurable or expandable; the state machine group module is configured as a first sub-state machine group and / or a second sub-state machine group; the first sub-state machine group is a state machine group divided according to FLASH functions, each of which corresponds to a FLASH function; the second sub-state machine group is a state machine group divided according to FLASH process platform type, each of which corresponds to a FLASH process platform type (FLASH type for short);

[0057] Preferably: the first sub-state machine group includes a sub-state machine for implementing a programming function, a sub-state machine for implementing an erasing function, a sub-state machine for implementing an erasing function, etc.; these functions are the minimum functional units for completing different types of FLASH operations, and for some types of FLASH, there may be some special functions. In this case, the functions of the sub-state machines can be correspondingly expanded according to the required functions;

[0058] Among them: when receiving different sub-state machine numbers in the sub-state machine number sequence, start the corresponding sub-state machine to complete the operation function of FLASH; that is, each sub-state in the second sub-state machine group serves a specific FLASH process platform type, so its execution efficiency is higher and does not involve or rarely involves state switching between sub-state machines; when this switching is a software-level switch (using simulation mode), the efficiency will be higher; and each sub-state in the first sub-state machine group serves each FLASH function, so when it completes an access instruction for a type of FLASH, its execution efficiency will be reduced due to the state switching between sub-state machines, and when the number of switching times of the sub-state machine increases and the switching time increases, such efficiency reduction will be more obvious; however, its flexibility will be higher, and operations suitable for different platforms can be completed by combining sub-state machines corresponding to functions;

[0059] Preferably: the sub-state machine included in the first sub-state corresponds to a cross-platform FLASH micro-operation; and the second sub-state machine group includes FLASH micro-operations or composite micro-operations for different process platforms;

[0060] Preferably: the sub-state machine group module further includes a third sub-state machine group; the third state machine group is set according to the FLASH operation frequency; based on the cross-FLASH type and cross-function FLASH operation analysis, the FLASH operation with high operation frequency is obtained, and the corresponding sub-state machine is set for the FLASH operation with high operation frequency, so as to form the third sub-state machine group; thereby shortening the execution path length of these high-frequency operations and improving the overall access efficiency of FLASH; when the sub-state machine group module is further expanded to have more sub-state machine groups, it can be selectively expanded from multiple perspectives such as efficiency and compatibility;

[0061] Preferably: when further version is updated, the third sub-state machine group can be updated and set; a common way is that when high-frequency coordination occurs across the first sub-state machine group and the second sub-state machine group, the third sub-state machine is set for the high-frequency coordination fragment (the fragment that crosses and appears continuously across the first sub-state machine group and the second sub-state machine group) and an update configuration or version update prompt is initiated; so that the FLASH operation in the third sub-state machine group corresponds to the high-frequency sub-state machine operation, and the execution path length of these high-frequency operations is shortened by setting and expanding the third sub-state machine;

[0062] The present invention expands and configures the sub-state machine group from multiple dimensions. For various situations such as limited applicable process platform types, a large number of applicable process platform types, and the presence of high-frequency operations, the multi-dimensional expansion of the state machine group shortens the execution path length of the involved FLASH operations and improves the overall access efficiency of FLASH. Furthermore, the dynamic configuration of the corresponding relationship between the state and the sub-state machine and the multi-level update method enable the expansion of the sub-state machine group to seamlessly connect the control of the upper interface control module.

[0063] Preferably: when the supported FLASH process platform type is less than a preset value, the sub-state machine number sequence issued by the master control state machine only involves the sub-state machines in the first sub-state machine group; and when the supported FLASH type is greater than or equal to the preset value, the sub-state machine number sequence issued by the master control state machine involves the sub-state machines in the first sub-state machine group and the second sub-state machine group, or only involves the sub-state machines in the second sub-state machine group; when the version number is greater than the high version number threshold, the sub-state machine number sequence issued by the master control state machine involves the sub-state machines in the first sub-state machine group, the second sub-state machine group and the third sub-state machine group, or only involves the sub-state machines in the first sub-state machine group or the second sub-state machine group, and the third sub-state machine group;

[0064] Preferably, the preset value is the number of sub-state machines in the second sub-state machine group; of course, it can also be measured by the size of the storage resources and computing resources occupied by the state machine; measuring by number is a relatively simple method;

[0065] Preferably: the sub-state machines in the first, second and third sub-state machine groups are numbered consecutively;

[0066] Preferably: the sub-state machines in the first, second and third sub-state machine groups are numbered independently and are not repeated; that is, no matter which method is adopted, the sub-state machines in each sub-state machine group are numbered differently, so that seamless update can be better achieved;

[0067] Preferably: the type is a FLASH type that is compatible with the FLASH controller of the system-on-chip applicable to the multi-process platform;

[0068] As attached Figure 2 As shown, based on the same inventive concept, the present invention proposes a FLASH control method for a system on a chip applicable to a multi-process platform, the method comprising the following steps:

[0069] Step S1: After the chip is powered on, the initialization is started first to initialize the FLASH controller. After the initialization is completed, the master control module returns to the idle state and can receive application instructions from the user end or the test end;

[0070] Step S2: When receiving different application instructions, start the corresponding state machine and sub-state machine to complete the operation function of FLASH. If starting the sub-state machine once cannot complete the operation process of all target addresses, the master control module will jump to the next target address and then start the corresponding sub-state machine again until the whole process is completed;

[0071] Step S3: After the application instruction is executed, the master control module returns to the idle state and waits for the next application instruction;

[0072] The terms "user terminal", "test terminal", or "computing device" encompass all kinds of devices, equipment and machines for processing data, examples of which include programmable processors, computers, systems on chips, or multiple or combinations of the above. The device can include dedicated logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application-specific integrated circuits). In addition to hardware, the device can also include code to create an execution environment for the computer program, for example, code that constitutes processor firmware, protocol stacks, database management systems, operating systems, cross-platform operating environments, virtual machines, or a combination of one or more of the above. The device and execution environment can implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0073] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of a programming language, including an assembled or interpreted language, a declarative or procedural language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0074] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0076] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0077] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A FLASH controller for a system on a chip suitable for a multi-process platform, characterized in that: The controller includes an upper layer application control module and a lower layer interface control module; The upper layer application control module includes an application interface, a register module, a state machine group and a master control module thereof; the upper layer application control module is set in a test terminal or a user terminal in an updateable manner; The updateable mode is performed in a software configurable mode; a version number is set to support the updateable mode; in a lower version number, the lower interface control module is configured with a first sub-state machine group; in a higher version number, the lower interface control module is configured with a second sub-state machine group or a first sub-state machine group and a second sub-state machine group; as the version number increases, the number of sub-state machine groups is expandable; The register module is used to convert the test task into the state machine usage sequence of the state machine group; it is also used to save the configuration information of the state machine group; The state machine group includes one or more state machines, and the state machines in the state machine group are controlled by the master control module; each state machine in the state machine group includes one or more states, and after each reconfiguration, the state machines included in the state machine group and the state transition relationship of each state machine are the same or different; The master control module starts or operates the state machine group in the master control module based on the application command, and schedules and controls the corresponding sub-state machine modules through the use of the state machine; specifically: the master control module starts each state machine in sequence based on the state machine use sequence corresponding to the test task; during the use of each state machine in the state machine use sequence, the sub-state machine number is sent to the lower layer interface control module in sequence according to the state entered in real time by each state machine; the states sent in sequence constitute a sub-state machine number sequence; the sub-state machine with the sub-state machine number is started based on the sub-state machine number sequence; until all state machines in the sequence are used up or fail to be used; The lower layer interface control module comprises a sub-state machine group module and a FLASH interface signal module; after receiving the sub-state machine number signal, the lower layer interface control module drives the sub-state machine corresponding to the sub-state machine number; the sub-state machines belong to the same or different sub-state machine groups; The sub-state machine group module is configured as a first sub-state machine group and a second sub-state machine group; the first sub-state machine group is a state machine group divided according to FLASH functions, and each sub-state machine therein corresponds to a FLASH function; the second sub-state machine group is a state machine group divided according to FLASH process platform type, and each sub-state machine therein corresponds to a FLASH process platform type; each sub-state machine in the sub-state machine group is used to send a timing signal related to its state transition after being driven based on its own configuration information, thereby completing an operation process consisting of one or more operations; The FLASH interface signal module is used to connect one or more FLASH arrays.

2. The FLASH controller of a system on chip applicable to a multi-process platform according to claim 1, characterized in that: The updateable mode is achieved by the cooperation between the software configurable mode and the hardware updateable mode.

3. The FLASH controller of the system on chip applicable to multiple process platforms according to claim 2, characterized in that: The one or more FLASH arrays operate and communicate in parallel when connected in parallel.

4. The FLASH controller of a system on chip applicable to a multi-process platform according to claim 3, characterized in that: The sub-state machines in the first and second sub-state machine groups are numbered consecutively.

5. The FLASH controller of the system on chip applicable to multiple process platforms according to claim 4, characterized in that: The state machine and sub-state machine are both finite state machines.

6. A FLASH control method for a system on a chip applicable to a multi-process platform based on the FLASH controller according to any one of claims 1 to 5, characterized in that: The method comprises: Step S1: After the chip is powered on, the FLASH controller is initialized; Step S2: When different application instructions are received, the corresponding state machine and sub-state machine are started to complete the operation function of the Flash; Step S3: After the application instruction is executed, the master control module returns to the idle state and waits to receive the next application instruction.

7. The FLASH control method of a system on chip applicable to multiple process platforms according to claim 6, characterized in that: The application instruction comes from a chip of a test terminal or a user terminal.

8. A processor, characterized in that: The processor is used to run a program, wherein the program, when running, executes the FLASH control method of a system on a chip applicable to a multi-process platform according to any one of claims 6 to 7.

9. A programmable logic array, characterized in that: When it is programmed, the FLASH control method of the system on chip applicable to a multi-process platform as described in any one of claims 6 to 7 is executed.

10. A chip, characterized in that: It includes a processor, the processor is coupled to a memory, the memory stores program instructions, and when the program instructions stored in the memory are executed by the processor, the FLASH control method of the system on chip applicable to a multi-process platform as described in any one of claims 6-7 is implemented.

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