A layout method for standard unit circuit transistors

Abstract

The present invention provides a layout method for standard unit circuit transistors, and the layout method includes the following steps: S1, first establish a two-stage model, and fold transistors of preset width through the two-stage model; S2, for a preset small-scale case, establish a mixed integer programming model, and solve the small-scale case through the mixed integer programming model to obtain a layout result; S3, for a preset large-scale case, solve the preset large-scale case through a greedy beam search algorithm to obtain an optimal layout result; S4, use a computer drawing method to visualize the layout result. The layout method of the standard unit circuit transistor of the present invention can effectively reduce the tedious operation of manual layout and improve the efficiency and accuracy of standard unit library development.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor layout, and in particular to a layout method of standard unit circuit transistors. Background Art

[0002] In the development of standard cell libraries for digital circuits, the optimization of transistor layout is a crucial link. The transistor layout of traditional standard cells mainly relies on manual calculation and drawing, but this method not only has major defects in layout time, but also the layout plan is prone to not meeting the constraints. In addition, employees need to consume a lot of brainpower and attention during the layout process, and over-reliance on the experience of old employees will also have certain constraints on the company's business development.

[0003] However, standard cell libraries play a vital role in the design of integrated circuits, and traditional manual layout methods can no longer keep up with the rapid development of standard cell libraries. Previous manual layout methods have constraints, such as long layout time, poor layout results, and layout results that do not meet constraints. Summary of the invention

[0004] The present invention provides a layout method for standard unit circuit transistors, aiming to solve the problems of long transistor layout time, poor layout results, and layout results not meeting constraints.

[0005] An embodiment of the present invention provides a layout method for standard unit circuit transistors, the layout method comprising the following steps:

[0006] S1, firstly establish a two-stage model, and perform folding processing on transistors of preset width through the two-stage model;

[0007] S2. For a preset small-scale case, a mixed integer programming model is established, and a layout result is obtained by solving the small-scale case through the mixed integer programming model;

[0008] S3. For a preset large-scale case, solving the preset large-scale case by a greedy beam search algorithm to obtain an optimal layout result;

[0009] S4. Visually display the layout result using a computer graphics method.

[0010] Preferably, in step S1, the establishment of the two-stage model specifically includes the following steps:

[0011] Establish the first stage model: fold the wider transistor into multiple small transistors, each with a width between 120-220nm, minimizing the number of transistors obtained by folding;

[0012] Establish a second-stage model: while the number of transistors in the first-stage model remains unchanged, redistribute the widths of the sub-transistors to make the widths of the sub-transistors as similar as possible. When the maximum width of the sub-transistors is the smallest, the widths of the sub-transistors are as similar as possible, and minimizing the maximum width of the sub-transistors is taken as the optimization goal.

[0013] Preferably, the step S1, the folding process specifically includes the following steps:

[0014] When the width is ≤220nm, no folding process is required;

[0015] When 220nm≤width≤240nm, no legal folding method can be found, that is, no folding process is required;

[0016] When 240nm≤width≤440nm, set the width of the original transistor to And fold out a width of The width of the original transistor is represented by w. To round down;

[0017] When the width is ≥440 nm, the two-stage model is used to fold the transistor.

[0018] Preferably, the step S2, establishing the mixed integer programming model specifically comprises the following sub-steps:

[0019] S21, numbering each transistor, and storing the transistor number in a key of a preset dictionary;

[0020] S22. Establish a mixed integer programming model according to the transistor numbering, and obtain a final transistor layout according to the mixed integer programming model.

[0021] Preferably, in step S21, the numbering specifically includes the following sub-steps:

[0022] Create a dictionary, define the key of the dictionary as the network name, and the value as the number;

[0023] Traverse all transistors, and determine whether the network names connected to the source, drain, and gate of the traversed transistor have been added to the dictionary; if they do not exist in the dictionary, add them to the dictionary; the first network name added to the dictionary is numbered 1, the second network name added to the dictionary is numbered 2, and so on, until all network names are stored in the dictionary keys and the numbering ends.

[0024] Preferably, the step S3 specifically includes the following sub-steps:

[0025] S31, pairing two transistors of the PMOS type and the NMOS type;

[0026] S32, finding all pairing solutions that can cover all transistors;

[0027] S33, using a greedy strategy to arrange the pairing scheme;

[0028] S34, selecting the top ten layouts with the highest scores as initial layouts for beam search optimization;

[0029] S35, attempting to perform post-processing optimization on the layout obtained by the beam search;

[0030] S36. Get the highest score layout.

[0031] Preferably, the step S32 specifically includes the following sub-steps:

[0032] S321, using an external loop to traverse all transistors in the PMOS transistor set;

[0033] S322, nesting a loop inside to traverse each transistor of the NMOS transistor set;

[0034] S323, determining whether the line network connected to the gate of the traversed PMOS transistor and the line network connected to the gate of the NMOS transistor are the same, and if they are the same, combining the PMOS transistor and the NMOS transistor into a transistor pair;

[0035] S324. Package each transistor individually into a transistor pair and find all pairing methods.

[0036] Preferably, the step S33 specifically includes the following sub-steps:

[0037] S331, sorting the transistor pairs in descending order according to the matching network counts;

[0038] S332, taking out the first pair in the set of transistor pairs, adding x to it and setting it to 0; defining that the first transistor pair in the layout has an abscissa x coordinate of 0;

[0039] S333, determining the addition x of the remaining transistor pairs in the transistor pair set, first obtaining the last transistor pair in the layout, wherein the last transistor pair is defined as the end pair;

[0040] S334. Select a transistor pair from the set of transistor pairs that can share an active area with the last pair. If there are multiple transistor pairs that meet this condition, select the one that has the most common wire nets with the last pair for layout.

[0041] Preferably, the step S34 specifically includes the following sub-steps:

[0042] S341, using the beam search algorithm to select some nodes at each level of the tree according to the constraint evaluation rules for the next step of search;

[0043] S342. Obtain the optimal result by setting the evaluation rules and beam width.

[0044] Compared with the prior art, the beneficial effect of the present invention is that a two-stage model is first established, and transistors of preset width are folded by the two-stage model; for a preset small-scale case, a mixed integer programming model is established, and the small-scale case is solved by the mixed integer programming model to obtain a layout result; for a preset large-scale case, the preset large-scale case is solved by a greedy beam search algorithm to obtain the optimal layout result; and the layout result is visualized using a computer drawing method. The advantage of the layout algorithm is that it can fully consider various constraints and automatically perform layout planning during the solution process. In addition, compared with manual layout, the algorithm has a higher solution efficiency, and the solution result can be accurately guaranteed. This method is undoubtedly a very potential solution in the development of digital circuit standard cell libraries, and can play a certain role in accelerating the speed of circuit design development and improving the quality of circuit design. At the same time, its efficient, accurate and high-quality layout scheme can replace the traditional manual layout results. The application prospect of this method is broad, and it is expected to play an important role in the field of integrated circuit design in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0046] Figure 1 is a flow chart of a layout method of a standard unit circuit transistor provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic diagram of the layout of a standard unit circuit transistor provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of a shared active area provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of a first-stage solution demonstration provided by an embodiment of the present invention;

[0050] Figure 5 is a schematic diagram of a second stage solution demonstration provided by an embodiment of the present invention;

[0051] Figure 6 The embodiment of the present invention provides Schematic diagram of the maximum horizontal coordinate value of ;

[0052] Figure 7 The embodiment of the present invention provides Schematic diagram of the maximum horizontal coordinate value of ;

[0053] Figure 8 is a schematic diagram of a transistor pairing process provided by an embodiment of the present invention;

[0054] Fig. 9 is a schematic diagram of addX of m1 being 1 provided by an embodiment of the present invention;

[0055] Fig.10 is a schematic diagram of addX of m1 being 2 provided by an embodiment of the present invention;

[0056] Fig.11 is a schematic diagram of a beam search process provided by an embodiment of the present invention;

[0057] Fig.12 is a schematic diagram of two update pairing methods of post-processing optimization provided by an embodiment of the present invention;

[0058] Fig.13 is a layout diagram of the test of case 1 provided in an embodiment of the present invention;

[0059] Fig.14 is a layout diagram of the test of case 2 provided in an embodiment of the present invention;

[0060] Fig.15 It is a layout diagram of the test of case three provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0062] Combined with Figure 1-Figure 15 As shown, an embodiment of the present invention provides a layout method of a standard unit circuit transistor, and the layout method includes the following steps:

[0063] S1. First, a two-stage model is established, and transistors of a preset width are folded using the two-stage model.

[0064] S2. For a preset small-scale case, a mixed integer programming model is established, and the small-scale case is solved by the mixed integer programming model to obtain a layout result.

[0065] The transistor layout includes an NMOS transistor region, a PMOS transistor region, a shared active region, and an unshared active region.

[0066] S3. For a preset large-scale case, the preset large-scale case is solved by a greedy beam search algorithm to obtain an optimal layout result.

[0067] The preset large-scale case is larger than the preset small-scale case. When it is a small-scale case, the small-scale case is solved by a mixed integer programming model to obtain a layout result. When it is a large-scale case, the preset large-scale case is solved by a greedy beam search algorithm to obtain the optimal layout result.

[0068] S4. Visually display the layout result using a computer graphics method.

[0069] Specifically, a two-stage model is first established, and transistors of preset width are folded through the two-stage model; for preset small-scale cases, a mixed integer programming model is established, and the small-scale cases are solved through the mixed integer programming model to obtain layout results; for preset large-scale cases, the preset large-scale cases are solved through a greedy beam search algorithm to obtain the optimal layout results; the layout results are visualized using computer drawing methods. The advantage of this layout algorithm is that it can fully consider various constraints and automatically perform layout planning during the solution process. In addition, compared with manual layout, the algorithm has a higher solution efficiency, and the solution results can be accurately guaranteed. This method is undoubtedly a very potential solution in the development of digital circuit standard cell libraries, and can play a certain role in accelerating the speed of circuit design development and improving the quality of circuit design. At the same time, its efficient, accurate, and high-quality layout solution can replace the traditional manual layout results.

[0070] In this embodiment, the step S1, the establishment of the two-stage model specifically includes the following steps:

[0071] Establish the first stage model: fold the wider transistor into multiple small transistors, each with a width between 120-220nm, and minimize the number of transistors obtained by folding.

[0072] Specifically, a transistor with a larger width is folded into multiple small transistors, and the width of each small transistor is between [120,220]nm. The goal is to minimize the number of transistors obtained by folding, which can reduce the scale of the layout problem and at the same time make the layout width smaller with a high probability. Let the width of the original transistor be represented by w, and the maximum number of small transistors is The reason for rounding down is that the remainder of w / 120 is definitely less than 120, but it is stipulated that transistors with a width less than 120 cannot be folded. The established model is as follows:

[0073]

[0074]

[0075]

[0076]

[0077] α i ∈{0,1} i∈{1,2,…,n} (2.5)

[0078] x i ∈{0, 1,…,220} i∈{1, 2,…,n} (2.6)

[0079] The objective function (2.1) represents minimizing the number of folded transistors; formula (2.2) represents when x i >0, α i The value of is limited to 1; Formula (2.3) indicates that α i When the value of x is 1, i The value of is greater than or equal to 120; Combining equations (2.2) and (2.3), it can be understood that when x i When it is not equal to 0, its value must be greater than or equal to 120; Formula (2.4) limits the sum of the widths of all folded sub-transistors to be equal to the width of the original transistor before folding; Formula (2.5) represents the decision variable α i is a 0-1 variable; Formula (2.6) limits x i The value of is between [0,220]. Figure 4 As shown, a transistor with a width of 560 is folded into three transistors with widths of 220, 220, and 120 respectively.

[0080] Establishing the second stage model: while the number of transistors in the first stage model remains unchanged, the widths of the sub-transistors are redistributed to make the widths of the sub-transistors as similar as possible. When the maximum width of the sub-transistors is the smallest, the widths of the sub-transistors are as similar as possible, and minimizing the maximum width of the sub-transistors is used as the optimization goal. Preferably, the widths of the sub-transistors are the same, and minimizing the maximum width of the sub-transistors is used as the optimization goal, which has a better optimization effect.

[0081] Specifically, in the first stage, the number of transistors does not change, and the width of the sub-transistors is redistributed. The goal is to make the width of the sub-transistors as similar as possible, so as to reduce the probability of the appearance of active area grooves. When the maximum width of the sub-transistor is the smallest, the widths of the sub-transistors will be as similar as possible, so minimizing the maximum width of the sub-transistor is taken as the optimization goal, and the model is established as follows:

[0082] min z (2.7)

[0083]

[0084]

[0085] z∈{0,1,…,220} (2.10)

[0086] x i ∈{0, 1,…,220} i∈{1, 2,…,n} (2.11)

[0087] The objective function (2.7) represents minimizing the maximum width of all sub-transistors; equation (2.8) limits z to be greater than or equal to each x i The value of; Formula (2.9) limits the sum of the widths of all folded sub-transistors to be equal to the width of the original transistor before folding; Formulas (2.10) and (2.11) limit z and x respectively. i The value of is between [0,220]. Figure 5 As shown, the three transistors with widths of 220, 220, and 120, after the widths are redistributed, the widths of the three transistors are 187, 187, and 186 respectively.

[0088] In this embodiment, the step S1, the folding process specifically includes the following steps:

[0089] When the width is ≤220nm, no folding process is required;

[0090] When 220nm≤width≤240nm, no legal folding method can be found, that is, no folding process is required;

[0091] When 240nm≤width≤440nm, set the width of the original transistor to And fold out a width of The width of the original transistor is represented by w. To round down;

[0092] When the width is ≥440 nm, the two-stage model is used to fold the transistor.

[0093] In this embodiment, the step S2, establishing the mixed integer programming model specifically includes the following sub-steps:

[0094] S21, numbering each transistor, and storing the transistor number in a key of a preset dictionary;

[0095] S22. Establish a mixed integer programming model according to the transistor numbering, and obtain a final transistor layout according to the mixed integer programming model.

[0096] Specifically, it is known that there are n transistors in a standard cell, and there are φ PMOS transistors, NMOS transistors The i-th transistor t i The type is y i , the number of the wire network connected on the left is s i , the number of the wire network connected on the right is d i , the grid connected to the wire network number is g i , width is w i The nets connected to all transistors in the standard cell are summarized to form a collection called netList, with a collection size of N. The width reference value of the standard cell is R, and the number of pins of the standard cell is P. These two parameters can be directly obtained based on the netlist data.

[0097] First, we need to decide the horizontal coordinate x of the i-th transistor i and whether to flip the transistor left or right i When the transistor is flipped left and right, the left and right connection nets will also be swapped. In order to facilitate modeling, the left i To indicate the actual number of the wire net connected to the left side of the transistor, where left i =(1-f i )s i +f i d i , right i Indicates the number of the network actually connected to the right side of the transistor, where right i =f i s i +(1-f i )d i .

[0098] Next, we need to decide i and t j Whether to share active area α ij (where i∈{1, 2, ..., n}, j∈{1, 2, ..., n}, i≠j), α ij is a zero-one variable, whose value can only be 0 or 1. ij =1, indicating ti and t j Shared active area, and x i <x j When α ij =0, indicating t i and t j Do not share the active area. i ≠y j , force α ij = 0, because different types of transistors cannot share the same active area; when t i and t j When the source and drain of the transistor are connected to completely different wire networks (no matter how the two transistors are flipped, t i and t j The source and drain of the connected wire net cannot match, that is, s i ≠s j 、s i ≠d j ,d i ≠s j And d i ≠d j ), mandatory α ij =0.

[0099] In addition, decision t i and t j Is the gate shared? ij , β ij is a zero-one variable. ij =1, indicating t i and t j Common gate; when β ij =0, indicating t i and t j No common gate. i ≠y j When β ij = 0, because transistors of the same type cannot share a gate; when g i ≠g j When β ij = 0, because the two transistor gates are connected to different wire networks, and the two cannot share the same gate; otherwise, it is necessary to decide β ij The value is 1 or 0.

[0100] Finally, in order to facilitate modeling, a very large constant M is introduced, and the established model is as follows:

[0101] max widthScore+symmetricScore+bsScore (3.1)

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108] p ij1 +p ij2 =1 i∈{1,2,…,n-1},j∈{i+1,i+2,…,n} (3.8)

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128]

[0129]

[0130]

[0131]

[0132]

[0133]

[0134] β ij ∈{0,1} i∈{1,2,…,n-1}, j∈{i+1,i+2,…,n} (3.34)

[0135] p ij1 ∈{0,1} i∈{1,2,…,n-1}, j∈{i+1,i+2,…,n} (3.35)

[0136] p ij2 ∈{0, 1} i∈{1, 2…, n-1}, j∈{i+1, i+2,…, n} (3.36)

[0137] z ij1 ∈{0,1} i∈{1,2,…,n-1}, j∈{i+1,i+2,…,n} (3.37)

[0138] z ij2 ∈{0,1} i∈{1,2,…,n-1}, j∈{i+1,i+2,…,n} (3.38)

[0139]

[0140]

[0141] Among them, formula (3.1) represents the objective function, and the optimization goal is to maximize the score, including the layout width score, symmetry score, and routability score. Formulas (3.2) and (3.3) jointly limit that when t i The right side of the wire mesh and t j When the left side wire network is the same, t i and t j You can choose whether to share the active area, i.e. α ij =1 or 0, otherwise α ij = 0. When t i The right side of the wire mesh and t jIf the left side of the network is different, if the right i -left j >0, formula (3.2) limits α ij =0; if right i -left j <0, formula (3.3) limits α ij = 0. And t i The right side of the wire mesh and t j When the left side of the network is the same, right i -left j =0, regardless of α ij =1 or 0, equations (3.2) and (3.3) are satisfied, so there is no limit on α ij The value of . Equations (3.4) and (3.5) limit the value of ij =1, x j =x i +1, when α ij = 0, equations (3.4) and (3.5) are always valid and lose their limiting effect. Equations (3.6), (3.7) and (3.8) limit the i and t j When the active area is not shared, the horizontal coordinates of the two must differ by two unit lengths or more. The function of equation (3.8) is to constrain x i ≥x j +2 or constraint x j ≥x i +2 holds. Equations (3.9) and (3.10) together limit that when t i The gate connection network and t j When the same, t i and t j You can choose whether to share the gate, that is, β ij =1 or 0; otherwise, β ij = 0. Equations (3.11) and (3.12) limit the ij =1, x i =x j . Equations (3.13), (3.14) and (3.15) limit the i and t j When the gate is not shared, x i ≠x j , where the function of formula (3.15) is to make the constraint x i ≥x j +1 or x j ≥x i +1 holds. Formula (3.16) limits when y i =y j =y k And w i <wj <w k When α ij and α jk At most one of them can be 0, indicating that t i and t j ,t j and t k The active area cannot be shared at the same time, which effectively avoids the appearance of active area grooves. Formula (3.17) limits the layout width w to be greater than the horizontal coordinates of all transistors. Formula (3.18) is used to calculate the layout width score, and formulas (3.19) to (3.29) are used together to represent the calculation method of the routability score. Formulas (3.19) to (3.27) are used to find the maximum horizontal coordinate value max of the kth line net k and the minimum horizontal coordinate value min k The bbox in formula (3.28) is used to represent the sum of the maximum horizontal coordinate values ​​of all nets minus the sum of the minimum horizontal coordinate values ​​of all nets. The bsScore in formula (3.29) represents the routability score. Formula (3.30) is used to calculate the symmetry score. For t i , if there is no other transistor sharing the gate with it, that is Then the symmetry score is deducted by 1 point. Equations (3.31) to (3.40) are used to define the range of decision variables. Equation (3.31) defines x i The maximum value is That is, first assume that all transistors cannot share active areas and gates. At this time, all x i Are less than or equal to For example, when When , the maximum horizontal coordinate value is 2φ-1, such as Figure 6 As shown; when When , the maximum horizontal coordinate value is 2φ-2, such as Figure 7 As shown; similarly, when When

[0142] In this embodiment, in the step S21, the numbering specifically includes the following sub-steps:

[0143] The names of the wire nets connected to the source, drain, and gate of the transistor in the data set are all strings. In order to facilitate the establishment of the model, a dictionary is created, and the key of the dictionary is defined as the wire net name and the value is the number;

[0144] Traverse all transistors, and determine whether the network names connected to the source, drain, and gate of the traversed transistor have been added to the dictionary; if they do not exist in the dictionary, add them to the dictionary; the first network name added to the dictionary is numbered 1, the second network name added to the dictionary is numbered 2, and so on, until all network names are stored in the dictionary keys and the numbering ends.

[0145] In this embodiment, step S3 specifically includes the following sub-steps:

[0146] S31, pairing two transistors of the PMOS type and the NMOS type;

[0147] S32, finding all pairing solutions that can cover all transistors;

[0148] S33, using a greedy strategy to arrange the pairing scheme;

[0149] S34, selecting the top ten layouts with the highest scores as initial layouts for beam search optimization;

[0150] S35, attempting to perform post-processing optimization on the layout obtained by the beam search to reduce the impact of unreasonable early pairing;

[0151] S36. Get the highest score layout.

[0152] Among them, the layout of S34 may have a higher score after step S35, and the layout with the highest score after step S35 is finally returned.

[0153] In this embodiment, step S32 specifically includes the following sub-steps:

[0154] S321, using an external loop to traverse all transistors in the PMOS transistor set;

[0155] S322, nesting a loop inside to traverse each transistor of the NMOS transistor set;

[0156] S323, determining whether the line network connected to the gate of the traversed PMOS transistor and the line network connected to the gate of the NMOS transistor are the same, and if they are the same, combining the PMOS transistor and the NMOS transistor into a transistor pair;

[0157] S324. Package each transistor individually into a transistor pair and find all pairing methods.

[0158] Specifically, transistor pairing is the basic work of the greedy beam search layout algorithm. The reason for transistor pairing is that transistor pairing can simplify the original two-dimensional layout problem into a one-dimensional layout problem, which can improve the search efficiency of the algorithm.

[0159] First, we need to find all the transistor pairings, by using an outer loop to iterate over all transistors in the PMOS transistor set.

[0160] Then a loop is nested inside to iterate over each transistor in the NMOS transistor set.

[0161] It is determined whether the wire net connected to the gate of the traversed PMOS transistor is the same as the wire net connected to the gate of the NMOS transistor. If they are the same, the PMOS transistor and the NMOS transistor are combined into a transistor pair. The transistor pairs found in this way all contain two transistors.

[0162] Finally, each transistor needs to be individually packaged into a transistor pair in order to find all the pairing methods. One reason for building a single transistor into a transistor pair is that some transistors cannot find other transistors with which to share a gate, and another reason is that in the optimal layout, each transistor does not necessarily share a gate with other transistors. Although sharing a gate with other transistors can improve the similarity score, it may also affect the current transistor pair and other transistor pairs sharing the active area, thereby affecting the width score. In addition, it may also affect the layout's routability score. For example, it would be better to place transistor 2 in other locations in the layout, but because it is paired with transistor 1, it can only be together with transistor 2, thereby reducing the routability score. The transistor pairs found in this way contain only one transistor. An example of a pairing is Figure 8 As shown, there are three PMOS transistors and two NMOS transistors in this example, and finally ten transistor pairs are found. When pairing, we only pay attention to which transistor is in a pair, and do not determine the flip state of the transistor. The flip state can only be determined during layout. The properties of a transistor pair are as follows:

[0163] pMosCode: (PMOS code) The number of the PMOS transistor. If there is no PMOS in the transistor pair, the value is -1;

[0164] nMosCode: (NMOS code) The number of the NMOS transistor. If there is no NMOS in the transistor pair, the value is -1;

[0165] matchNetCount: (matching network count) The number of nets that the PMOS transistor and the NMOS transistor share. For example, if the nets connected to the three poles of the PMOS transistor are {A1, A2, A3}, and the nets connected to the three poles of the NMOS transistor are {A1, A2, P1}, then the number of nets that the two transistors share is 2;

[0166] pMosF: The flip state of the PMOS transistor in the transistor pair. 0 means no flip, and 1 means flip. This attribute can only be determined during layout.

[0167] nMosF: The flip state of the NMOS transistor in the transistor pair. 0 means no flip, and 1 means flip. This attribute can only be determined during layout.

[0168] addX: The coordinates added relative to the previous transistor pair. If the active area can be shared with the previous transistor pair, the value is 1, otherwise the value is 2. This property can also be determined during layout. The advantage of using relative coordinates instead of absolute coordinates is that in the subsequent search process and post-processing process, the order of transistor pairs in the layout and the transistors in the transistor pairs need to be repeatedly adjusted. Using relative coordinates allows most transistors to be adjusted without modification during layout adjustment. If absolute coordinates are used, changes in the coordinates of the transistor pairs in the front of the layout will affect the coordinates in the back of the layout, requiring a large number of modification operations on the properties of the transistor pairs.

[0169] gate: The gate of the transistor in the transistor pair. This property is recorded to improve the efficiency of finding swappable transistor pairs in the post-processing stage.

[0170] In this embodiment, the step S33 specifically includes the following sub-steps:

[0171] S331, sorting the transistor pairs in descending order according to the matching network counts;

[0172] S332, taking out the first pair in the set of transistor pairs, adding x to it and setting it to 0; defining that the first transistor pair in the layout has an abscissa x coordinate of 0;

[0173] S333, determining the addition x of the remaining transistor pairs in the transistor pair set, first obtaining the last transistor pair in the layout, wherein the last transistor pair is defined as the end pair;

[0174] S334. Select a transistor pair from the set of transistor pairs that can share an active area with the last pair. If there are multiple transistor pairs that meet this condition, select the one that has the most common wire nets with the last pair for layout.

[0175] Specifically, before greedy layout, it is necessary to find all transistor pair selection schemes that can cover all transistors. We have found all the transistor pairing methods, and we need to select some transistor pairs from them to form a scheme. The transistor pairs of this scheme need to cover all transistors, that is, any transistor in the case is included in one of the transistor pairs in the scheme, and each transistor can only be covered once, otherwise the resulting layout may lack some transistors or some transistors may be repeated, resulting in illegal layout results. For example, the transistor numbering inside transistor pair 1 is {1,2}, and the transistor numbering inside transistor pair 2 is {1,5}, then transistor pair 1 and transistor pair 2 cannot be selected at the same time, otherwise transistor 1 will be covered twice, resulting in an extra transistor 1 in the final layout. We use a backtracking algorithm to find all transistor pair selection schemes, then find all feasible solutions from them, and finally use a greedy strategy to layout these feasible solutions.

[0176] First, sort the transistor pairs in the scheme in descending order according to matchNetCount (matching network count);

[0177] Then take the first pair in the transistor pair set and set its addX to 0, because it is the first transistor pair in the layout and its x coordinate is 0;

[0178] Next, we need to determine the addX of the remaining transistor pairs in the transistor pair set. First, we get the last transistor pair in the layout, which is called the end pair.

[0179] Then select a transistor pair from the set of transistor pairs that can share an active area with the last pair. If there are multiple transistor pairs that meet this condition, select the one that has the most common nets with the last pair, because this allows the same nets to be put together, thereby effectively improving the routability score.

[0180] For example, the nets connected to the transistors in the last pair are {A1, M1, MN2, MP1, M1, A1}, and the nets connected to transistor pair 1 are {P3, MP2, MN2, MP1, MP2, A2}, so the number of common nets between the two is 2. If there are multiple transistor pairs with the same number of common nets as the last pair, select the transistor pair with the smallest index in the set; if no transistor pair can share the active area with the last pair, select the transistor pair with the largest number of common nets with the last pair; if there are multiple transistor pairs, select the transistor pair with the smallest index in the set; repeat the above operation until the transistor pair set is empty and the greedy layout is completed.

[0181] The method to determine whether the unplaced transistor pair m2 and the placed transistor pair m1 can share the active area is as follows: If addX of m1 is 1, the transistor flipping state of m1 cannot be adjusted because it has shared the active area with the transistor pair before the layout. At this time, you can only try to flip the transistor of m2 to see whether it can share the active area with the transistor of m1. Fig. 9 As shown, you only need to flip the NMOS transistor of m2, and m1 and m2 can share the active area; if addX of m1 is 2, it means that m1 does not share the active area with the transistor pair in the previous layout, so the flip state of the transistor in m1 can be modified. At this time, you need to try to flip the transistors of m1 and m2 at the same time to see if the two can share the active area. Fig.10 As shown, as long as the pMosF of m1 is set to 1 and the nMosF is set to 1, and the pMosF of m2 is set to 0 and the nMosF is set to 1, the two transistor pairs can share the active area. When m1 and m2 can share the active area, addX of m2 is set to 1, otherwise addX of m2 is set to 2.

[0182] In this embodiment, step S34 specifically includes the following sub-steps:

[0183] S341, using the beam search algorithm to select some nodes at each level of the tree according to the constraint evaluation rules for the next step of search;

[0184] S342. Obtain the optimal result by setting the evaluation rules and beam width.

[0185] Specifically, breadth-first traversal can help us find all transistor pair sequences, but as the tree depth increases, the number of tree nodes increases exponentially. In the face of large-scale cases, breadth-first traversal takes a long time to solve and occupies a lot of memory.

[0186] The beam search algorithm uses some evaluation rules to select some nodes for the next search at each level of the tree. By setting good evaluation rules and beam width, it can find better results while ensuring search efficiency. After using the greedy strategy to obtain 10 initial layouts, the beam search strategy needs to be used to optimize each initial layout.

[0187] like Fig.11As shown, the beam width is 2, and the two nodes with the highest scores are retained in each layer. The other nodes are pruned and no longer searched. Note that when changing the order of transistor pairs in the layout, it is necessary to reconsider whether the connection can share the active area. For example, the order of transistor pairs before the layout modification is M3, M1, M2, M5, M4. Now it is necessary to insert M5 in front of M1 to adjust the layout. The layout order after adjustment is M3, M5, M1, M2, M4. It is necessary to determine whether M3 and M5 can share the active area, whether M5 and M1 can share the active area, whether M2 and M4 can share the active area, and then adjust the flip state of the transistors in the transistor pair.

[0188] In addition to pruning based on beam width, this article also prunes based on routability score, because if the routability score of the current layout is already relatively poor, there is no need to search further. During the beam search process, we will record the routability score bestBsScore of the optimal layout. When the routability score of a node is less than [bestBsScore-100*(1-deep / matchNum)-10], it will be pruned, where deep refers to the depth of the beam search and matchNum refers to the number of transistor pairs in the layout. The reason for this setting is that as the depth increases, the range of changes in the layout routability score will gradually decrease, so the probability of finding a better solution will also begin to decrease. Therefore, the deeper the depth, the less acceptable the poor solution will be.

[0189] In this embodiment, a greedy strategy is used when selecting transistor pairings, so the transistor pairings of the layout are not necessarily optimal. The layout post-processing optimization exchanges the transistors of any two transistor pairs to determine whether the layout score can be improved. If so, the exchange is accepted and this step is repeated until the layout score cannot be improved any further. Fig.12 As shown, there are two ways to update the transistor pair in the post-processing stage. One is to exchange the same type of transistors in the two transistor pairs, such as exchanging the PMOS in the two transistor pairs. When the same type of transistor is missing in the other transistor pair, the transistors in transistor pair 1 are directly moved to transistor pair 2. Note that the transistor pair update operation can only be performed when the gates of the two transistor pairs are the same.

[0190] In this embodiment, the above-mentioned layout method is used to perform corresponding tests, and the test method is as follows:

[0191] After the transistors in the first case are folded, there are a total of 18 transistors, including 9 PMOS type transistors and 9 NMOS type transistors. The case is provided in the form of a netlist file. The first line "ADH1V4" represents the name of the standard unit. From the second line to the second to last line, each line represents the information of a transistor, such as the line "MM5 CO nandab VDDW = 400.00n L = 30.00n", where "MM5" represents the name of the transistor, "CO nandab VDD" represents the name of the wire network connected to the drain, gate, and source, "W = 400.00n" represents the width of the transistor, and "L = 30.00n" represents the length of the transistor.

[0192] The final layout score is 95.03, and the layout diagram is as follows Fig.13 shown.

[0193] The second case has a total of 38 transistors after transistor folding, of which 19 are PMOS type transistors and 19 are NMOS type transistors. The final layout score is 93.15, and the layout diagram is as follows Fig.14 shown.

[0194] The third case contains a total of 60 transistors after transistor folding, of which 30 are PMOS type transistors and 30 are NMOS type transistors. The final layout score is 90.74. The layout diagram is as follows: Fig.15 shown.

[0195] It can be seen that no matter which layout is tested in the present invention, the final layout score is greater than 90 points. Therefore, the present invention has an efficient, accurate, and high-quality layout solution that can replace the traditional manual layout results. The application prospect of this method is broad and is expected to play an important role in the future field of integrated circuit design.

[0196] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0197] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A layout method for a standard unit circuit transistor, characterized in that: The layout method comprises the following steps: S1, firstly establish a two-stage model, and perform folding processing on transistors of preset width through the two-stage model; S2. For a preset small-scale case, a mixed integer programming model is established, and a layout result is obtained by solving the small-scale case through the mixed integer programming model; S3. For a preset large-scale case, solving the preset large-scale case by a greedy beam search algorithm to obtain an optimal layout result; S4, using a computer graphics method to visualize the layout result; The step S1, the establishment of the two-stage model specifically includes the following steps: Establish the first stage model: fold the wider transistor into multiple small transistors, each with a width between 120-220nm, minimizing the number of transistors obtained by folding; Establishing a second-stage model: while the number of transistors in the first-stage model remains unchanged, the widths of the sub-transistors are redistributed to make the widths of the sub-transistors as similar as possible. When the maximum width of the sub-transistors is the smallest, the widths of the sub-transistors are as similar as possible, and minimizing the maximum width of the sub-transistors is taken as an optimization goal. The step S1, the folding process specifically includes the following steps: When the width At 220nm, no folding process is required; When 220nm width 240nm, no legal folding method can be found, that is, no folding process is required; When 240nm width 440nm, setting the width of the original transistor to , and fold out a width of The new transistor is: , To round down; When the width At 440nm, the two-stage model is used to fold the transistor; The step S2, establishing the mixed integer programming model specifically comprises the following sub-steps: S21, numbering each transistor, and storing the transistor number in a key of a preset dictionary; S22, establishing a mixed integer programming model according to the transistor numbering, and obtaining a final transistor layout according to the mixed integer programming model; The step S3 specifically includes the following sub-steps: S31, pairing two transistors of the PMOS type and the NMOS type; S32, finding all pairing solutions that can cover all transistors; S33, using a greedy strategy to arrange the pairing scheme; S34, selecting the top ten layouts with the highest scores as initial layouts for beam search optimization; S35, attempting to perform post-processing optimization on the layout obtained by the beam search; S36. Get the highest score layout.

2. The layout method of standard unit circuit transistors according to claim 1, characterized in that: In the step S21, the numbering specifically includes the following sub-steps: Create a dictionary, define the key of the dictionary as the network name, and the value as the number; Traverse all transistors, and determine whether the network names connected to the source, drain, and gate of the traversed transistor have been added to the dictionary; if they do not exist in the dictionary, add them to the dictionary; the first network name added to the dictionary is numbered 1, the second network name added to the dictionary is numbered 2, and so on, until all network names are stored in the dictionary keys and the numbering ends.

3. The layout method of standard unit circuit transistors according to claim 1, characterized in that: The step S32 specifically includes the following sub-steps: S321, using an external loop to traverse all transistors in the PMOS transistor set; S322, nesting a loop inside to traverse each transistor of the NMOS transistor set; S323, determining whether the line network connected to the gate of the traversed PMOS transistor and the line network connected to the gate of the NMOS transistor are the same, and if they are the same, combining the PMOS transistor and the NMOS transistor into a transistor pair; S324. Package each transistor individually into a transistor pair and find all pairing methods.

4. The layout method of standard unit circuit transistors according to claim 3, characterized in that: The step S33 specifically includes the following sub-steps: S331, sorting the transistor pairs in descending order according to the matching network counts; S332, take out the first pair in the set of transistor pairs and add it x Set to 0; Definition: The first transistor pair in the layout has its horizontal axis x The coordinate is 0; S333, determining the addition of the remaining transistor pairs in the transistor pair set x , first get the last transistor pair in the layout, the last transistor pair is defined as the end pair; S334. Select a transistor pair from the set of transistor pairs that can share an active area with the last pair. If there are multiple transistor pairs that meet this condition, select the one that has the most common wire nets with the last pair for layout.

5. The layout method of standard unit circuit transistors according to claim 1, characterized in that: The step S34 specifically includes the following sub-steps: S341, using the beam search algorithm to select some nodes at each level of the tree according to the constraint evaluation rules for the next step of search; S342. Obtain the optimal result by setting the evaluation rules and beam width.

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