On-orbit update system and method for field-programmable gate arrays

Abstract

The present application provides a field programmable gate array on-orbit update system and method, the system includes: controlling a field programmable gate array, a magnetic random access memory, a refresh chip, a non-volatile memory and a baseband processing field programmable gate array; controlling the field programmable gate array to obtain target data corresponding to a target functional module and cache it in the magnetic random access memory, extracting updated target configuration data from the target data and sending it to the refresh chip, the target functional module is a module in which a functional upgrade occurs among a plurality of mutually independent dynamic reconstruction modules included in the baseband processing field programmable gate array; the refresh chip updates the configuration data in the non-volatile memory based on the target configuration data, and after the update, loads all the configuration data into the baseband processing field programmable gate array, and updates the target functional module on-orbit. The present application can reduce the difference in layout and wiring before and after the functional upgrade, and shorten the on-orbit update time.

Description

Technical Field

[0001] The present application relates to the field of space exploration technology, and in particular to an on-orbit updating system and method for a field programmable logic gate array. Background Art

[0002] Dynamic partial reconstruction technology divides the logic resources of the Field Programmable Gate Array (FPGA) into a static area and several dynamic areas. The static modules corresponding to the static area remain unchanged, and the dynamic modules corresponding to the dynamic area are completely independent of each other. When a dynamic module is modified, only the layout and routing of the dynamic module changes, and the layout and routing of the remaining dynamic modules and static modules remain unchanged.

[0003] On-orbit reconfiguration means that when the satellite is on-orbit, the payload fails or needs a function upgrade. The ground control station uploads new configuration data to the payload through the ground-to-space link to achieve hardware reconfiguration and program update, thereby achieving the purpose of fault repair and function upgrade. The transmission rate between the satellite and the ground is relatively low. The uplink rate of the control is about 4kbit / s. The configuration data volume of JFM7V690T (an FPGA product) is about 230Mbit, and the upload time is 57500s. Therefore, for ultra-large-scale FPGAs, an on-orbit reconfiguration takes a lot of time.

[0004] In order to improve the single-particle upset resistance of the static random access memory (SRAM) FPGA system circuit, the occultation receiver adopts the refresh chip + FPGA (JFM7V690T) solution. The timed refresh function of the refresh chip can effectively reduce the impact of single particles on the FPGA.

[0005] If the on-orbit reconstruction solution of the entire bitstream file is adopted, it will take too long and is not practical. If the traditional dynamic partial reconstruction solution is adopted, the FPGA function update is completed by injecting the bitstream file of the dynamic reconstruction module. Although this solution can realize dynamic loading without interrupting the normal operation of the FPGA, it cannot use the refresh function of the refresh chip, which reduces the reliability of the system. In addition, additional memory is required to store the bitstream file of the dynamic reconstruction module, which increases the hardware resource overhead. Summary of the invention

[0006] In view of the above problems, embodiments of the present application provide a field programmable gate array on-orbit update system and method that overcomes the above problems or at least partially solves the above problems.

[0007] In a first aspect, an embodiment of the present application provides an on-orbit update system for a field programmable logic gate array, which is deployed on a global satellite navigation system occultation receiver, and includes: a control field programmable logic gate array, a magnetic random access memory, a refresh chip, a non-volatile memory, and a baseband processing field programmable logic gate array;

[0008] The control field programmable logic gate array is connected to the magnetic random access memory and the refresh chip, and is used to receive target data corresponding to a target functional module sent by a satellite platform, cache the target data in the magnetic random access memory, extract target configuration data from the target data cached in the magnetic random access memory, and send the target configuration data to the refresh chip, wherein the target configuration data is updated configuration data corresponding to the target functional module, and the target data is generated by packaging the target configuration data according to the above-mentioned update data packet format, and the target functional module is at least one module of the multiple functional modules included in the baseband processing field programmable logic gate array that undergoes functional upgrade, and the multiple functional modules are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other;

[0009] The refresh chip is connected to the non-volatile memory and the baseband processing field programmable logic gate array, and is used to update the configuration data in the non-volatile memory based on the target configuration data, and load all the configuration data in the non-volatile memory to the baseband processing field programmable logic gate array after the update is completed;

[0010] The baseband processing field programmable logic gate array is used to perform data operation after loading all configuration data and perform on-orbit update of the target functional module.

[0011] In a second aspect, an embodiment of the present application provides an on-track update method for a field programmable logic gate array, which is applied to control a field programmable logic gate array, and the method includes:

[0012] Receive target data corresponding to a target functional module sent by a satellite platform, wherein the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, and the target configuration data is updated configuration data corresponding to the target functional module, and the target functional module is at least one module of a plurality of functional modules included in a baseband processing field programmable logic gate array, and the plurality of functional modules are all dynamically reconfigurable modules, and the plurality of functional modules are independent of each other;

[0013] caching the target data into a magnetic random access memory;

[0014] Extracting the target configuration data from the target data cached in the magnetic random access memory, sending the target configuration data to a refresh chip, allowing the refresh chip to update the configuration data in the non-volatile memory, and loading all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array;

[0015] The baseband processing field programmable logic gate array completes the on-orbit update of the target functional module by running all the loaded configuration data.

[0016] In a third aspect, an embodiment of the present application provides an on-orbit update method for a field programmable gate array, which is applied to an on-orbit update system for a field programmable gate array, wherein the on-orbit update system for a field programmable gate array includes: controlling a field programmable gate array, a magnetic random access memory, a refresh chip, a non-volatile memory, and a baseband processing field programmable gate array, wherein the method includes:

[0017] The control field programmable logic gate array receives target data corresponding to a target functional module sent by a satellite platform and provides the target data to the magnetic random access memory, wherein the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, and the target configuration data is updated configuration data corresponding to the target functional module, and the target functional module is at least one module of a plurality of functional modules included in the baseband processing field programmable logic gate array that undergoes a function upgrade, and the plurality of functional modules are all dynamically reconfigurable modules, and the plurality of functional modules are independent of each other;

[0018] The magnetic random access memory receives and caches the target data sent by the control field programmable logic gate array;

[0019] The control field programmable logic gate array extracts the target configuration data from the target data cached in the magnetic random access memory, and sends the target configuration data to the refresh chip;

[0020] The refresh chip updates the configuration data in the non-volatile memory based on the target configuration data, and loads all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array after the update is completed;

[0021] The baseband processing field programmable logic gate array performs data operation after loading all configuration data, and performs on-orbit update on the target functional module.

[0022] In a fourth aspect, an embodiment of the present application provides a global satellite navigation system occultation receiver, comprising the field programmable logic gate array in-orbit update system described in the first aspect.

[0023] In a fifth aspect, an embodiment of the present application provides an electronic device, the electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;

[0024] Memory, used to store computer programs;

[0025] The processor is used to implement the steps of the above-mentioned field programmable logic gate array on-orbit update method when executing the program stored in the memory.

[0026] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned field programmable gate array on-orbit update method are implemented.

[0027] The embodiments of the present application include at least the following technical effects:

[0028] By utilizing the characteristic of FPGA dynamic reconstruction technology that the function of the dynamic reconstruction module in the dynamic area can be modified without affecting the logic layout and wiring of other areas, multiple functional modules included in the baseband processing field programmable logic gate array are set to be dynamic reconstruction modules, so that only the updated configuration data corresponding to the module with function upgrade can be obtained, thereby reducing the amount of configuration data uploaded to the satellite platform, thereby shortening the on-orbit update time; and the on-orbit update system provided by the present application supports the refresh chip to continue to enable the refresh function, effectively reducing the impact of single particles in space, and improving the space environment adaptability and reliability of the occultation receiver; because no additional memory is required to store the bit stream file of the dynamic reconstruction module, the hardware overhead is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0030] Figure 1 A schematic diagram of an on-orbit update system for a field programmable gate array provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the connection between the field programmable logic gate array on-orbit update system and peripheral components provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the connection between the baseband processing field programmable logic gate array and peripheral components provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of importing a dynamic reconstruction module into a dynamic reconstruction area provided in an embodiment of the present application;

[0034] Figure 5A Hardware resources of the FPGA chip provided in the embodiment of the present application Figure 1 ;

[0035] Figure 5B Hardware resources of the FPGA chip provided in the embodiment of the present application Figure 2 ;

[0036] Figure 6 A schematic diagram of design update based on the functional modules that need to be upgraded and modified provided in the embodiment of the present application;

[0037] Figure 7 A schematic diagram of an on-orbit update method for a field programmable logic gate array provided in an embodiment of the present application Figure 1 ;

[0038] Figure 8 A schematic diagram of an on-orbit update method for a field programmable logic gate array provided in an embodiment of the present application Figure 2 ;

[0039] Fig. 9 A structural block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In the embodiments of the present application, the term "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0041] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] An embodiment of the present application provides an FPGA on-orbit update system based on dynamic partial reconstruction technology, which does not require additional memory overhead. While reducing the on-orbit reconstruction time, it supports the refresh function of the normal use of the refresh chip, effectively reduces the impact of single particles in space, and improves the reliability of the Global Navigation Satellite System (GNSS) occultation receiver.

[0044] The following is an introduction to the field programmable logic gate array on-orbit update system deployed on a GNSS occultation receiver provided in an embodiment of the present application. Figure 1 As shown, the field programmable gate array on-orbit update system 10 includes: a control field programmable gate array 11, a magnetic random access memory 12, a refresh chip 13, a non-volatile memory 14 and a baseband processing field programmable gate array 15.

[0045] The control field programmable logic gate array 11 is connected to the magnetic random access memory 12 and the refresh chip 13, and is used to receive target data corresponding to the target functional module sent by the satellite platform, cache the target data to the magnetic random access memory 12, extract target configuration data from the target data cached in the magnetic random access memory 12, and send the target configuration data to the refresh chip 13, wherein the target configuration data is the updated configuration data corresponding to the target functional module, and the target data is generated by packaging the target configuration data according to the above-mentioned update data packet format, and the target functional module is at least one module of the multiple functional modules included in the baseband processing field programmable logic gate array 15 that has undergone functional upgrade, and the multiple functional modules are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other;

[0046] The refresh chip 13 is connected to the non-volatile memory 14 and the baseband processing field programmable logic gate array 15, and is used to update the configuration data in the non-volatile memory 14 based on the target configuration data, and load all the configuration data in the non-volatile memory 14 to the baseband processing field programmable logic gate array 15 after the update is completed;

[0047] The baseband processing field programmable logic gate array 15 is used to perform data operation after loading all configuration data and perform on-orbit update of the target functional module.

[0048] The field programmable gate array on-orbit update system (referred to as FPGA on-orbit update system) provided in the embodiment of the present application includes the following devices: a control field programmable gate array (referred to as control FPGA) 11, a magnetic random access memory (referred to as MRAM) 12, a refresh chip 13, a non-volatile memory 14 and a baseband processing field programmable gate array (referred to as baseband processing FPGA) 15.

[0049] like Figure 2 As shown, the control field programmable logic gate array 11 is connected to the satellite platform 20, and receives the target data corresponding to the target functional module sent by the satellite platform 20 through, for example, an RS422 (electrical characteristics of a balanced voltage digital interface circuit) bus. The target functional module is a module that undergoes functional upgrade among the multiple functional modules included in the baseband processing field programmable logic gate array 15, and the number of the target functional modules is one or more. The multiple functional modules included in the baseband processing field programmable logic gate array 15 are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other.

[0050] The target data is generated by packaging the target configuration data according to the upload update data packet format and uploaded to the satellite platform 20. The target data includes the target configuration data as well as other parts such as the header, the tail, and the check information, and the target data is uploaded to the satellite platform 20 in the form of a data packet.

[0051] The developer determines the complete configuration data corresponding to the function module before the upgrade and the complete configuration data corresponding to the function module after the upgrade, and determines the updated configuration data corresponding to at least one target function module by comparing the two, and then determines the target configuration data. After determining the target configuration data, the target configuration data is packaged according to the format of the uploaded update data packet to generate the target data. The ground measurement and control station uploads the target data to the satellite platform 20 based on the interaction with the satellite platform 20.

[0052] In the embodiment of the present application, based on the FPGA dynamic partial reconstruction technology, the functional modules of the baseband processing field programmable logic gate array are set as dynamic reconstruction modules by utilizing the characteristics of modifying the functions of the dynamic reconstruction modules in the dynamic area without affecting the logic layout and wiring of other areas. When a functional module needs to be upgraded and modified, only the layout and wiring of the functional module is changed, and the layout and wiring of the remaining functional modules remain unchanged. This greatly reduces the difference in layout and wiring before and after the function upgrade of the baseband processing field programmable logic gate array, and greatly reduces the difference in configuration data of the baseband processing field programmable logic gate array before and after.

[0053] like Figure 1 and Figure 2As shown, the control field programmable logic gate array 11 is connected to the magnetic random access memory 12 and the refresh chip 13. After acquiring the target data corresponding to the target functional module, the control field programmable logic gate array 11 caches the target data in the magnetic random access memory 12, so as to store the target data in the magnetic random access memory 12. The target data cached in the magnetic random access memory 12 is verified, and when the verification is successful, the target configuration data is extracted and sent to the refresh chip 13.

[0054] The refresh chip 13 is connected to the non-volatile memory 14 and the baseband processing field programmable logic gate array 15. The non-volatile memory 14 can be a Flash memory for storing configuration data corresponding to the baseband processing field programmable logic gate array 15. For the refresh chip 13, the refresh chip 13 has a refresh function. After the refresh chip 13 is powered on, the configuration data in the non-volatile memory 14 can be automatically loaded to the baseband processing field programmable logic gate array 15 for operation. The refresh chip 13 regularly refreshes the configuration bits of the baseband processing field programmable logic gate array 15 to reduce the impact of single particles.

[0055] After acquiring the target configuration data, the refresh chip 13 updates the configuration data in the non-volatile memory 14 based on the target configuration data, and after completing the update of the configuration data in the non-volatile memory 14 based on the target configuration data, controls all the configuration data in the non-volatile memory 14 to be loaded into the baseband processing field programmable logic gate array 15. After loading all the configuration data in the non-volatile memory 14, the baseband processing field programmable logic gate array 15 performs data operation to perform on-track update of the target functional module based on the updated configuration data.

[0056] It should be noted that, when the refresh function is disabled, the refresh chip 13 updates the configuration data in the non-volatile memory 14 based on the target configuration data and controls the reloading of the configuration data.

[0057] The above implementation scheme of the present application utilizes the characteristics of FPGA dynamic reconstruction technology to modify the function of the dynamic reconstruction module in the dynamic area without affecting the logic layout and wiring of other areas, and sets the multiple functional modules included in the baseband processing field programmable logic gate array to be dynamic reconstruction modules. It is possible to obtain only the updated configuration data corresponding to the module with functional upgrade, thereby reducing the amount of configuration data uploaded to the satellite platform, thereby shortening the on-orbit update time; and the on-orbit update system provided by the present application supports the refresh chip to continue to enable the refresh function, effectively reducing the impact of single particles in space, and improving the space environment adaptability and reliability of the occultation receiver; since no additional memory is required to store the bitstream file of the dynamic reconstruction module, the hardware overhead is reduced.

[0058] In an optional embodiment of the present application, if Figure 1 and Figure 2 As shown, the control field programmable logic gate array 11 is also used to: before receiving the target data, send a disable refresh instruction to the refresh chip 13; when all the configuration data in the non-volatile memory 14 are successfully loaded into the baseband processing field programmable logic gate array 15, send an enable refresh instruction to the refresh chip 13;

[0059] The refresh prohibition instruction is sent by the control field programmable logic gate array 11 after receiving the control instruction sent by the satellite platform 20, and the control instruction indicates to disable the refresh function.

[0060] Before the satellite platform 20 needs to send target data to the control field programmable logic gate array 11, it first sends a control instruction to the control field programmable logic gate array 11 to disable the refresh function. The control field programmable logic gate array 11 sends a disable refresh instruction to the refresh chip 13 according to the control instruction, and the refresh chip 13 disables the refresh function according to the disable refresh instruction.

[0061] After determining that the refresh chip 13 disables the refresh function, the control FPGA 11 notifies the satellite platform 20 , and the satellite platform 20 sends the target data to the control FPGA 11 , which caches the target data in the magnetic random access memory 12 .

[0062] After obtaining the target configuration data, the refresh chip 13 updates the configuration data in the non-volatile memory 14 based on the target configuration data. After the configuration data in the non-volatile memory 14 is updated, all the configuration data in the non-volatile memory 14 is controlled to be loaded into the baseband processing field programmable logic gate array 15.

[0063] It should be noted that if the refresh function is not disabled, the refresh chip 13 will refresh the baseband processing field programmable logic gate array 15 at regular intervals. Since the first-in first-out queue (FIFO) capacity of the refresh chip 13 is small, it cannot buffer too much data and cannot execute two functions at the same time. At this time, the refresh chip 13 cannot update the configuration data in the non-volatile memory 14 based on the target configuration data.

[0064] The refresh chip 13 is also used to return telemetry information to the control field programmable logic gate array 11, and the control field programmable logic gate array 11 determines whether the baseband processing field programmable logic gate array 15 has successfully loaded all the configuration data in the non-volatile memory 14 based on the telemetry information. In the case of determining that all the configuration data in the non-volatile memory 14 has been successfully loaded into the baseband processing field programmable logic gate array 15, the control field programmable logic gate array 11 sends an enable refresh instruction to the refresh chip 13, and the refresh chip 13 enables the refresh function according to the enable refresh instruction to realize the recovery refresh function and regularly refresh the configuration bits of the baseband processing field programmable logic gate array 15.

[0065] By controlling the refresh chip to disable the refresh function before receiving the target data, and restoring the refresh function after the baseband processing field programmable logic gate array successfully reloads the configuration data, the refresh function can be prevented from affecting the updated configuration data. By restoring the refresh function, the impact of single particles in space can be effectively reduced, thereby improving the adaptability and reliability of the space environment of the occultation receiver.

[0066] In another optional embodiment of the present application, Figure 1 As shown, the control field programmable logic gate array 11 is also used to verify the target data cached in the magnetic random access memory 12, and if the verification is successful, the target configuration data is extracted and sent to the refresh chip 13.

[0067] After acquiring the target data, the control field programmable logic gate array 11 caches the target data in the magnetic random access memory 12, and verifies the target data in the magnetic random access memory 12. If the verification is successful, the target configuration data is extracted from the magnetic random access memory 12, and the target configuration data is sent to the refresh chip 13, so as to send the target configuration data to the refresh chip 13 after the data verification is successful.

[0068] Since the target data is injected from the ground control station to the satellite platform, and the satellite platform forwards the received target data to the control field programmable logic gate array 11, the control field programmable logic gate array 11 can ensure the correctness of the received data by verifying the received data. The target data injected from the ground control station to the satellite platform includes the target configuration data as well as other parts such as the header, the tail, and the verification information. The verification information may include a first verification value. After receiving the target data and caching it, the control field programmable logic gate array 11 verifies the cached target data to obtain a second verification value, and compares the second verification value with the first verification value it carries. If the two are the same, it indicates that the verification is successful.

[0069] After acquiring the target configuration data, the refresh chip 13 is also used to: erase the first configuration data in the non-volatile memory 14 and burn the target configuration data to the non-volatile memory 14 when updating the configuration data in the non-volatile memory 14; wherein the first configuration data is the configuration data before the update that matches the target configuration data.

[0070] After acquiring the target configuration data, the refresh chip 13 determines the first configuration data before the update that is adapted to the target configuration data in the configuration data stored in the non-volatile memory 14, and then erases the first configuration data in the non-volatile memory 14 and burns the target configuration data into the non-volatile memory 14 to update the configuration data, so as to ensure that the latest configuration data is stored in the non-volatile memory 14.

[0071] Among them, the non-volatile memory 14 stores all the configuration data corresponding to the baseband processing field programmable logic gate array 15, and the refresh chip 13 can automatically load the configuration data in the non-volatile memory 14 to the baseband processing field programmable logic gate array 15 for operation; by updating the configuration data stored in the non-volatile memory 14 based on the target configuration data, it can be ensured that the latest configuration data in the non-volatile memory 14 is loaded into the baseband processing field programmable logic gate array 15 for operation, and then the baseband processing field programmable logic gate array 15 can run the latest configuration data to realize the on-orbit update of the functional module.

[0072] Optionally, the refresh chip 13 returns telemetry information to the control field programmable logic gate array 11, which can not only be used to determine whether the baseband processing field programmable logic gate array 15 has successfully loaded all the configuration data in the non-volatile memory 14, but also can be used to determine whether the configuration data in the non-volatile memory 14 has been updated.

[0073] Specifically, the telemetry information is used to provide indication information on whether the current data packet has been updated. The target configuration data includes multiple data packets, where the data packet can be understood as a first data packet, and the first data packet is determined based on the second data packet corresponding to the target data. The target data is uploaded to the satellite platform in the form of a data packet, and the target data includes multiple second data packets. In addition to the configuration data, the second data packet also includes a header, a trailer and other information. When extracting the target configuration data from the target data, it can be regarded as extracting the configuration data from the second data packet to obtain the first data packet. Therefore, the target configuration data includes multiple first data packets, and multiple first data packets are determined based on multiple second data packets.

[0074] The control field programmable logic gate array 11 accumulates the number of updated data packets (first data packets) based on the telemetry information, where the data packets counted are data packets that update the corresponding configuration data in the non-volatile memory 14 with the help of the latest configuration data included therein. When the total number of updated data packets is equal to the predicted total number of packets, it is determined that the configuration data in the non-volatile memory 14 is updated. The predicted total number of packets here is the total number of first data packets corresponding to the target configuration data and the total number of second data packets corresponding to the target data.

[0075] When it is determined that the configuration data in the non-volatile memory 14 has been updated, the control field programmable logic gate array 11 sends a reload instruction to the refresh chip 13, and the reload instruction is used to instruct the baseband processing field programmable logic gate array 15 to reload the configuration data. Among them, the telemetry information can be automatically sent periodically or based on trigger conditions. For the case of periodic sending, for example, the refresh chip 13 sends telemetry information once every certain period of time (such as 5s); for the case of sending based on trigger conditions, the control field programmable logic gate array 11 can send a return telemetry instruction to the refresh chip 13, and the refresh chip 13 will return the telemetry information after receiving the return telemetry instruction.

[0076] For the refresh chip 13, the refresh chip 13 updates the configuration data in the non-volatile memory 14 based on the target configuration data, and returns telemetry information to the control field programmable logic gate array 11. The control field programmable logic gate array 11 accumulates the number of updated data packets according to the telemetry information to determine whether the configuration data in the non-volatile memory 14 has been updated. When it is determined that the configuration data in the non-volatile memory 14 has been updated, a reload instruction is sent to the refresh chip 13.

[0077] The refresh chip 13 receives the reload instruction sent by the control field programmable logic gate array 11 after determining that the configuration data in the non-volatile memory 14 has been updated. According to the reload instruction, all the configuration data in the non-volatile memory 14 are loaded into the baseband processing field programmable logic gate array 15, so as to reload the configuration data in response to the reload instruction, thereby ensuring that the baseband processing field programmable logic gate array 15 runs the latest configuration data, thereby realizing the on-orbit update of the functional module.

[0078] The following is an introduction to the baseband processing field programmable logic gate array, such as Figure 3 As shown, the baseband processing field programmable logic gate array 15 includes at least the following functional modules: a clock synchronization module 151, an analog-to-digital conversion interface module 152, a real-time delay Doppler mapping module 153, a delay Doppler mapping data control module 154, an external memory interface module 155, a data transmission control module 156 and a fast Fourier transform module 157;

[0079] The functional modules included in the baseband processing field programmable logic gate array 15 are respectively arranged in the dynamic reconstruction area of ​​the baseband processing field programmable logic gate array 15.

[0080] like Figure 2 and Figure 3 As shown, the baseband processing field programmable logic gate array 15 is connected to the analog-to-digital conversion sampling chip 30, the positioning baseband processing application specific integrated circuit (Application Specific Integrated Circuit, ASIC) 40, the digital signal processing (Digital Signal Processing, DSP) chip 50 and the satellite platform 20. The main function of the baseband processing field programmable logic gate array 15 is to receive the digital signal provided by the analog-to-digital conversion sampling chip 30 and the clock synchronization pulse sent by the positioning baseband processing application specific integrated circuit 40, and under the control of the digital signal processing chip 50, generate Delay Doppler Mapping (Delay Doppler Mapping, DDM) data in real time, and send the DDM data to the satellite platform 20 through the RS422 bus.

[0081] like Figure 3 As shown, the clock synchronization module 151 of the baseband processing field programmable logic gate array 15 is connected to the positioning baseband processing dedicated integrated circuit 40 through the clock synchronization signal interface, and receives the clock synchronization pulse sent by the positioning baseband processing dedicated integrated circuit 40. The analog-to-digital conversion interface module 152 of the baseband processing field programmable logic gate array 15 is connected to the analog-to-digital conversion sampling chip 30 through the baseband AD (analog-to-digital conversion) interface, and receives the digital signal provided by the analog-to-digital conversion sampling chip 30. The clock synchronization module 151 and the analog-to-digital conversion interface module 152 are connected to the real-time delay Doppler mapping module 153.

[0082] The external memory interface module 155 of the baseband processing field programmable logic gate array 15 is connected to the digital signal processing chip 50 through the external memory interface (EMIF); the external memory interface module 155 is connected to the fast Fourier transform module 157, and the fast Fourier transform module 157 and the external memory interface module 155 are connected to the real-time delay Doppler mapping module 153.

[0083] The real-time delay Doppler mapping module 153 is connected to the delay Doppler mapping data control module 154 , the delay Doppler mapping data control module 154 is connected to the data transmission control module 156 , and the data transmission control module 156 transmits the DDM data to the satellite platform 20 .

[0084] Among them, the external memory interface module 155 receives the parameters sent by the digital signal processing chip 50, including DDM channel enable, carrier numerically controlled oscillator (NCO), code NCO, etc.; the external memory interface module 155 transmits the parameters sent by the digital signal processing chip 50 to the real-time delay Doppler mapping module 153.

[0085] The analog-to-digital conversion interface module 152 obtains the input signal (analog-to-digital conversion sampling digital signal) provided by the analog-to-digital conversion sampling chip 30 ; the clock synchronization module 151 receives the clock synchronization signal sent by the positioning baseband processing dedicated integrated circuit 40 and provides it to the real-time delay Doppler mapping module 153 .

[0086] The real-time delay Doppler mapping module 153 receives the input signal provided by the analog-to-digital conversion interface module 152, receives the clock synchronization signal provided by the clock synchronization module 151, and receives the parameters forwarded by the external memory interface module 155 and provided by the digital signal processing chip 50. The real-time delay Doppler mapping module 153 performs segmented integration on the input signal, and then calls the fast Fourier transform module 157 to perform fast Fourier transform and square calculation on the signal. The obtained calculation result is non-coherently integrated in the real-time delay Doppler mapping module 153 to obtain DDM data and measurement data.

[0087] Among them, the real-time delay Doppler mapping module 153 sends measurement data to the digital signal processing chip 50 through the external memory interface module 155; the digital signal processing chip 50 transmits the enable signal to the fast Fourier transform module 157 through the external memory interface module 155, and the fast Fourier transform module 157 returns the status parameters to the digital signal processing chip 50 through the external memory interface module 155.

[0088] The delay Doppler mapping data control module 154 packages the DDM data, converts the packaged data into serial data and sends it to the data transmission control module 156. When there is a data transmission demand, the data transmission control module 156 enables the transmission channel and sends the DDM data to the satellite platform 20.

[0089] The following describes a process of how to obtain target configuration data, where the target configuration data is determined by comparing the complete configuration data before the update corresponding to the baseband processing field programmable logic gate array with the complete configuration data after the update corresponding to the baseband processing field programmable logic gate array;

[0090] The complete configuration data before updating is generated after obtaining the first netlist design checkpoint file, allocating hardware resources to multiple functional modules and passing the design rule check, the first netlist design checkpoint file includes complete design information associated with the top-level module and multiple functional modules, and the top-level module is used to integrate multiple functional modules; the complete configuration data after updating is generated after obtaining the second netlist design checkpoint file and passing the design rule check, the second netlist design checkpoint file is generated by clearing the original design information of the target functional module for the first netlist design checkpoint file and connecting to the upgraded design information of the target functional module.

[0091] To generate complete configuration data before updating, you need to go through the following operations:

[0092] 1. In the top-level module, all functional modules corresponding to the baseband processing field programmable logic gate array (e.g., 7 functional modules corresponding to the baseband processing field programmable logic gate array) are defined as black boxes, and the top-level module is synthesized using the Vivado development tool. After the synthesis is completed, the netlist design checkpoint (DCP) file corresponding to the top-level module is saved.

[0093] Among them, the top-level module is the highest level of the entire design. It contains the connection methods between various functional modules (such as 7 functional modules) and is responsible for integrating all functional modules together; the netlist DCP file refers to the design checkpoint file containing the synthesized logic netlist information. In FPGA design, the netlist DCP file usually contains design data that has been synthesized but not yet implemented and generated bitstream, which can be used for subsequent layout, timing analysis, simulation and other operations.

[0094] 2. Use the Vivado development tool to perform out-of-context (OOC) synthesis on all functional modules before the baseband processing field programmable logic gate array upgrade and modification. After the synthesis is completed, save the netlist DCP file corresponding to each functional module. If the functional module contains an intellectual property core (IPCore), you need to change the intellectual property core to the global synthesis mode first, and then perform OOC synthesis on the functional module.

[0095] Among them, the intellectual property core is a pre-designed circuit function module, which refers to a modular design unit that can be reused in digital circuit design, similar to the code library in software development.

[0096] 3. Create a new project, import the netlist DCP files corresponding to all functional modules of the baseband processing field programmable logic gate array in the new project, import the netlist DCP file corresponding to the top-level module, determine the hierarchical relationship between the top-level module and other functional modules (such as the 7 functional modules included in the baseband processing field programmable logic gate array listed above), combine the netlist DCP files of the top-level module and other functional modules into a complete design, and add pin files and clock constraint files.

[0097] The specific solution for combining and docking the netlist DCP files of the top-level module and other functional modules into a complete design is as follows: Use Vivado software to open the netlist DCP files corresponding to the top-level module and the netlist DCP files corresponding to other functional modules (such as the 7 functional modules listed above) (a total of 8 netlist DCP files), and then enter the corresponding instructions. Vivado software automatically combines and docks the top-level module and other functional modules into a complete design. At this time, Vivado software can be used to export the complete design into a new netlist DCP file (this new netlist DCP file contains relevant information about the complete design, such as, named NETD1.dcp). It should be noted that the netlist DCP file cannot be directly docked. Vivado software needs to perform relevant operations to complete the combined docking, and then export it to a new netlist DCP file NETD1.dcp. NETD1.dcp is the first netlist design checkpoint file.

[0098] 4. Draw Pblocks (physical module) areas according to the logical resources required by each functional module, add physical constraints to multiple dynamic reconfiguration areas, and import dynamic reconfiguration modules for each dynamic reconfiguration area. Figure 4 As shown, the clock synchronization module is imported into the dynamic reconstruction area 1, the analog-to-digital conversion interface module is imported into the dynamic reconstruction area 2, the real-time delay Doppler mapping module is imported into the dynamic reconstruction area 3, the delay Doppler mapping data control module is imported into the dynamic reconstruction area 4, the external memory interface module is imported into the dynamic reconstruction area 5, the data sending control module is imported into the dynamic reconstruction area 6, and the fast Fourier transform module is imported into the dynamic reconstruction area 7. Figure 4 The part different from the dynamic reconstruction area is the static area.

[0099] Among them, the Pblocks area is used to allocate resources in a specific area of ​​the FPGA to the functional module. The drawn Pblocks area needs to contain all types of resources required by the functional module, and a hardware resource margin of about 15% needs to be left to prevent subsequent layout and routing failures; for some functional modules with large upgrade and modification requirements, a hardware resource margin of about 30% can be left when drawing the Pblocks area to prevent insufficient resources when the subsequent functional modules are updated and modified. In order to improve timing and make layout and routing more flexible, the Pblock area can be selected as "L" type or "T" type, but it should not be too complicated.

[0100] In step 3, the combination and docking result in a complete design. To realize the functions of this complete design, hardware resources need to be allocated, that is, the relevant functions can be realized by allocating the hardware resources of the FPGA chip. Therefore, step 4 is to allocate hardware resources to multiple functional modules, and drawing Pblocks areas is a way to allocate hardware resources.

[0101] As an example, Figure 5A As shown in the figure, it is the hardware resource diagram of FPGA chip. Figure 5B compared to Figure 5A There are 7 more boxes (7 Pblocks areas). These 7 boxes represent 7 dynamic reconstruction areas. The 7 functional modules correspond to these 7 boxes (dynamic reconstruction areas) one by one. For example, the clock synchronization module corresponds to dynamic reconstruction area 1, the analog-to-digital conversion interface module corresponds to dynamic reconstruction area 2, the real-time delay Doppler mapping module corresponds to dynamic reconstruction area 3, the delay Doppler mapping data control module corresponds to dynamic reconstruction area 4, the external memory interface module corresponds to dynamic reconstruction area 5, the data transmission control module corresponds to dynamic reconstruction area 6, and the fast Fourier transform module corresponds to dynamic reconstruction area 7. Each functional module can only use the hardware resources in the corresponding box (dynamic reconstruction area), which is the physical constraint.

[0102] 5. Perform a design rule check (DRC), perform layout and routing after the check is correct, generate a bit stream, and obtain the complete configuration data of the baseband processing field programmable logic gate array before the update, such as CfgD1.rbt.

[0103] Based on the above steps, the process of generating complete configuration data after update is introduced. This process requires the following operations:

[0104] 6. Perform OOC synthesis on the upgraded and modified functional modules separately, and save the corresponding netlist DCP file after the synthesis is completed. If the upgraded and modified functional module contains intellectual property cores, you need to change the intellectual property cores to Global synthesis mode first, and then perform OOC synthesis on the functional module.

[0105] 7. Clear all functional modules that need to be upgraded and modified in the first netlist design checkpoint file, lock the layout and routing of the remaining designs, load the netlist DCP files of the upgraded functional modules and combine them into a new complete design.

[0106] In step 3, the netlist DCP file (NETD1.dcp) containing complete design information before the upgrade and modification is obtained. Use Vivado software to open NETD1.dcp and enter relevant instructions to clear the functional modules that need to be upgraded and modified. After the clearing is completed, add the netlist DCP file corresponding to the upgraded and modified functional modules, and combine and dock the netlist DCP file corresponding to the upgraded and modified functional modules with the cleared design to obtain a new complete design. At this time, a new netlist DCP file can be exported, such as NETD2.dcp, which is the second netlist design checkpoint file.

[0107] As an example, the functional module that needs to be upgraded and modified is the fast Fourier transform module, such as Figure 6 As shown in the figure, after obtaining the complete design determined based on the top-level module and the seven functional modules, the fast Fourier transform module before the upgrade and modification is cleared to obtain the intermediate design corresponding to the top-level module and the six functional modules. After obtaining the netlist DCP file corresponding to the fast Fourier transform module after the upgrade and modification, the netlist DCP file corresponding to the fast Fourier transform module after the upgrade and modification is added to the intermediate design, and the two are recombined and docked to obtain a new complete design corresponding to the top-level module and the seven functional modules.

[0108] 8. Perform design rule check, perform layout and routing after the check is correct, generate bit stream, and obtain the updated complete configuration data of the baseband processing field programmable logic gate array, such as CfgD2.rbt.

[0109] Through the above process, the complete configuration data before and after the update corresponding to the baseband processing field programmable logic gate array can be obtained. The complete configuration data before and after the update can be compared to determine the target configuration data, and the target configuration data is packaged according to the format of the uploaded update data packet to obtain the target data. After determining the target data, the target data is delivered to the ground measurement and control station, which, based on the interaction with the satellite platform, uploads the target data to the satellite platform, and then the satellite platform can send the target data to the control field programmable logic gate array to control the target functional module in the baseband processing field programmable logic gate array for in-orbit update.

[0110] The above introduces the on-orbit update system of the field programmable logic gate array provided in the embodiment of the present application. Based on the FPGA dynamic partial reconstruction technology, the functional modules of the baseband processing field programmable logic gate array are set as dynamic reconstruction modules by utilizing the characteristics of modifying the functions of the dynamic reconstruction modules in the dynamic area without affecting the logic layout and wiring of other areas. When a certain functional module needs to be upgraded and modified, the field programmable logic gate array is controlled to receive the corresponding configuration data, and the original configuration data in the non-volatile memory is modified through the refresh chip, and the latest configuration data is loaded into the baseband processing field programmable logic gate array for on-orbit update of the corresponding functional module. It can be achieved that only the updated configuration data corresponding to the module where the function upgrade occurs is obtained, which reduces the amount of configuration data uploaded to the satellite platform, thereby shortening the on-orbit update time; and after the update is completed, the refresh function of the refresh chip can be used normally, which reduces the risk of single particle impact and improves the space environment adaptability and reliability of the occultation receiver.

[0111] The present application also provides an on-track update method for FPGA used to control a field programmable gate array. Figure 7 As shown, the method includes:

[0112] Step 701, receiving target data corresponding to a target functional module sent by a satellite platform, wherein the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, and the target configuration data is updated configuration data corresponding to the target functional module, and the target functional module is at least one module of a plurality of functional modules included in a baseband processing field programmable logic gate array that undergoes a function upgrade, and the plurality of functional modules are all dynamically reconfigurable modules, and the plurality of functional modules are independent of each other.

[0113] The control field programmable logic gate array communicates with the satellite platform and receives the target data corresponding to the target function module sent by the satellite platform. The target function module is a module in which the function upgrade occurs among the multiple function modules included in the baseband processing field programmable logic gate array, and the number of the target function modules is one or more. The multiple function modules included in the baseband processing field programmable logic gate array are all dynamically reconfigurable modules, and the multiple function modules are independent of each other. The target data is generated by packaging the target configuration data according to the format of the uploaded update data packet, and uploaded to the satellite platform, that is, the target data is uploaded by the ground measurement and control station and forwarded to the control field programmable logic gate array via the satellite platform. The target configuration data is determined by the developer. When determining the target configuration data, it is necessary to obtain the complete configuration data before the update and the complete configuration data after the update corresponding to the baseband processing field programmable logic gate array, and compare the complete configuration data before the update and the complete configuration data after the update to obtain the target configuration data. Then, the target configuration data is packaged according to the format of the uploaded update data packet to obtain the target data.

[0114] Step 702: Cache the target data into a magnetic random access memory.

[0115] After acquiring the target data corresponding to the target functional module, the control field programmable logic gate array caches the target data into a magnetic random access memory connected thereto, so as to store the target data in the magnetic random access memory.

[0116] Step 703: extract the target configuration data from the target data cached in the magnetic random access memory, send the target configuration data to the refresh chip, and have the refresh chip update the configuration data in the non-volatile memory, and load all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array, wherein the baseband processing field programmable logic gate array completes the on-orbit update of the target functional module by running all the loaded configuration data.

[0117] The control field programmable logic gate array extracts the target configuration data from the target data and sends the target configuration data to the refresh chip. The refresh chip is connected to the non-volatile memory and the baseband processing field programmable logic gate array. After obtaining the target configuration data, the refresh chip updates the configuration data in the non-volatile memory based on the target configuration data. After completing the update of the configuration data in the non-volatile memory based on the target configuration data, the control chip loads all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array. After loading all the configuration data in the non-volatile memory, the baseband processing field programmable logic gate array performs data operation to perform on-track update of the target functional module based on the updated configuration data.

[0118] In an embodiment of the present application, based on the FPGA dynamic partial reconstruction technology, the functional modules of the baseband processing field programmable logic gate array are set as dynamic reconstruction modules by utilizing the characteristics of performing functional modifications to the dynamic reconstruction module in the dynamic area without affecting the logic layout and wiring of other areas. When a functional module needs to be upgraded and modified, only the layout and wiring of the functional module is changed, and the layout and wiring of the remaining functional modules remain unchanged. Only the updated configuration data corresponding to the functional module needs to be transmitted, thereby reducing the amount of data transmission.

[0119] The above implementation scheme of the present application, by setting the multiple functional modules included in the baseband processing field programmable logic gate array to be dynamic reconstruction modules, can obtain only the updated configuration data corresponding to the module where the function upgrade occurs, thereby reducing the amount of configuration data uploaded to the satellite platform, thereby shortening the on-orbit update time; and the present application supports the refresh chip to continue to enable the refresh function, effectively reducing the impact of single particles in space, and improving the space environment adaptability and reliability of the occultation receiver; since no additional memory is required to store the bitstream file of the dynamic reconstruction module, the hardware overhead is reduced.

[0120] As an optional embodiment of the present application, controlling the field programmable logic gate array to extract target configuration data from target data and sending the target configuration data to the refresh chip includes: verifying the target data cached in the magnetic random access memory, extracting the target configuration data when the verification is successful, and sending the target configuration data to the refresh chip.

[0121] After the control field programmable logic gate array acquires the target data and caches the target data in the magnetic random access memory, the target data cached in the magnetic random access memory is verified. If the verification is successful, the target configuration data is extracted from the target data and sent to the refresh chip, so as to send the target configuration data to the refresh chip after completing the data verification, thereby ensuring that accurate data is provided to the refresh chip.

[0122] Since the target data is sent by the ground control station and forwarded by the satellite platform to the control field programmable logic gate array, the control field programmable logic gate array can ensure the correctness of the received data by verifying the received target data. The target data that the ground control station injects to the satellite platform contains a first verification value. After receiving the target data and caching it, the control field programmable logic gate array verifies it to obtain a second verification value, and compares the second verification value with the first verification value it carries. If the two are the same, it indicates that the verification is successful.

[0123] For the refresh chip, after receiving the target configuration data, it determines the first configuration data that is adapted to the target configuration data and has not been updated in the configuration data stored in the non-volatile memory, and then erases the first configuration data and burns the target configuration data into the non-volatile memory to update the configuration data, so as to ensure that the latest configuration data is stored in the non-volatile memory, and further ensure that the latest configuration data in the non-volatile memory is loaded into the baseband processing field programmable logic gate array for operation, so as to realize the on-orbit update of the functional modules corresponding to the baseband processing field programmable logic gate array.

[0124] As another optional embodiment of the present application, the method further includes:

[0125] Controlling the field programmable logic gate array to receive a control instruction sent by the satellite platform indicating disabling of a refresh function before receiving the target data sent by the satellite platform;

[0126] Sending a refresh prohibition instruction to the refresh chip according to the control instruction;

[0127] When all configuration data in the non-volatile memory are successfully loaded into the baseband processing field programmable logic gate array, sending a refresh enable instruction to the refresh chip;

[0128] The telemetry information returned by the refresh chip may be used to determine whether the baseband processing field programmable logic gate array has successfully loaded all configuration data in the non-volatile memory.

[0129] After power-on, the refresh chip can automatically load the configuration data in the non-volatile memory to the baseband processing field programmable logic gate array for operation, thereby realizing the timed refresh of the configuration bits of the baseband processing field programmable logic gate array. Before the satellite platform needs to send target data to the control field programmable logic gate array, it first sends a control instruction to the control field programmable logic gate array to instruct to disable the refresh function. The control field programmable logic gate array sends a prohibit refresh instruction to the refresh chip according to the control instruction, so that the refresh chip disables the refresh function.

[0130] After determining that the refresh function is disabled, the control field programmable logic gate array notifies the satellite platform, and the satellite platform can send target data to the control field programmable logic gate array. The control field programmable logic gate array caches the received target data in the magnetic random access memory, verifies the target data cached in the magnetic random access memory, extracts the target configuration data if the verification is successful, and sends the target configuration data to the refresh chip. The refresh chip updates the configuration data in the non-volatile memory based on the target configuration data.

[0131] Among them, the refresh chip can return telemetry information to the control field programmable logic gate array. The telemetry information can be automatically sent periodically or based on trigger conditions. For example, the refresh chip sends telemetry information once every certain period of time (such as 5 seconds), or the control field programmable logic gate array sends a return telemetry instruction to the refresh chip, and the refresh chip returns telemetry information according to the return telemetry instruction. Based on the telemetry information, the control field programmable logic gate array can determine whether the baseband processing field programmable logic gate array has successfully loaded all the configuration data in the non-volatile memory.

[0132] Among them, the telemetry information is also used to provide indication information on whether the current data packet has been updated. The target configuration data includes multiple data packets, where the data packet is a first data packet, and the first data packet is determined based on the second data packet corresponding to the target data. The target data is uploaded to the satellite platform in the form of a data packet, and the target data includes multiple second data packets. In addition to the configuration data, the second data packet also includes a header, a tail, and other information. When extracting the target configuration data from the target data, it can be regarded as extracting the configuration data from the second data packet to obtain the first data packet. Therefore, the target configuration data includes multiple first data packets, and the multiple first data packets are determined based on multiple second data packets.

[0133] The number of data packets (first data packets) that have been updated based on the telemetry information accumulated by the field programmable logic gate array is controlled. The data packets counted here are data packets that update the corresponding configuration data in the non-volatile memory with the help of the latest configuration data included therein. When the total number of data packets that have completed the update is equal to the predicted total number of packets, it is determined that the configuration data in the non-volatile memory has been updated. The predicted total number of packets here is the total number of first data packets corresponding to the target configuration data and the total number of second data packets corresponding to the target data.

[0134] The control field programmable logic gate array sends a reload instruction to the refresh chip when it is determined that the non-volatile memory has completed data update based on the target configuration data. The refresh chip loads all the configuration data in the non-volatile memory to the baseband processing field programmable logic gate array according to the reload instruction, and reloads the configuration data in response to the reload instruction, ensuring that the baseband processing field programmable logic gate array runs the latest configuration data.

[0135] When determining that all configuration data in the non-volatile memory are successfully loaded into the baseband processing field programmable logic gate array, the control field programmable logic gate array sends an enable refresh instruction to the refresh chip. The refresh chip enables the refresh function according to the enable refresh instruction to realize the recovery refresh function and regularly refresh the configuration bits of the baseband processing field programmable logic gate array.

[0136] By disabling the refresh function before receiving the target data and restoring the refresh function after the baseband processing field programmable logic gate array successfully reloads the configuration data, the refresh function can be prevented from affecting the updated configuration data. By restoring the refresh function, the impact of single particles in space can be effectively reduced, and the adaptability and reliability of the space environment of the occultation receiver can be improved. By acquiring telemetry information, the data update status can be monitored and data loading can be performed in time. At the same time, the data loading status can be monitored and the refresh function can be restored in time.

[0137] The above is an introduction to the FPGA on-orbit update method for controlling a field programmable gate array provided in the embodiment of the present application. The following is an introduction to the FPGA on-orbit update method for a field programmable gate array on-orbit update system. The field programmable gate array on-orbit update system includes: a control field programmable gate array, a magnetic random access memory, a refresh chip, a non-volatile memory, and a baseband processing field programmable gate array, such as Figure 8 As shown, the method includes:

[0138] Step 801, control the field programmable logic gate array to receive target data corresponding to the target functional module sent by the satellite platform and provide it to the magnetic random access memory, the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, the target configuration data is the updated configuration data corresponding to the target functional module, the target functional module is at least one module of the multiple functional modules included in the baseband processing field programmable logic gate array that has undergone functional upgrade, the multiple functional modules are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other.

[0139] The control field programmable logic gate array communicates with the satellite platform and receives the target data corresponding to the target functional module sent by the satellite platform. The target functional module is a module in which the function upgrade occurs among the multiple functional modules included in the baseband processing field programmable logic gate array, and the number of the target functional modules is one or more. The multiple functional modules included in the baseband processing field programmable logic gate array are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other. The target data is packaged and generated by the target configuration data according to the uploaded update data packet format, and uploaded to the satellite platform.

[0140] Step 802: The magnetic random access memory receives and caches the target data sent by the control field programmable logic gate array.

[0141] After acquiring the target data, the control field programmable logic gate array sends the target data to the magnetic random access memory connected thereto, and the magnetic random access memory receives and caches the target data, thereby realizing the storage of the target data in the magnetic random access memory.

[0142] Step 803: Control the field programmable logic gate array to extract the target configuration data from the target data cached in the magnetic random access memory, and send the target configuration data to the refresh chip.

[0143] The control field programmable logic gate array is connected to the refresh chip, and the control field programmable logic gate array extracts target configuration data from the target data, and sends the target configuration data to the refresh chip. After the control field programmable logic gate array stores the target data in the magnetic random access memory, the target data cached in the magnetic random access memory is verified. If the verification is successful, the target configuration data is extracted from the target data, and the target configuration data is sent to the refresh chip. The specific verification process can be referred to the introduction in the above embodiment, which will not be further elaborated here.

[0144] Step 804: The refresh chip updates the configuration data in the non-volatile memory based on the target configuration data, and loads all the configuration data in the non-volatile memory to the baseband processing field programmable logic gate array after the update is completed.

[0145] The refresh chip is connected to the non-volatile memory and the baseband processing field programmable logic gate array. After obtaining the target configuration data, the refresh chip updates the configuration data in the non-volatile memory based on the target configuration data. After the update is completed, all the configuration data in the non-volatile memory are loaded into the baseband processing field programmable logic gate array to realize the reloading of the configuration data.

[0146] Step 805: After loading all configuration data, the baseband processing field programmable logic gate array performs data operation and performs on-orbit update on the target functional module.

[0147] After loading all the configuration data in the non-volatile memory, the baseband processing field programmable logic gate array performs data operation to perform in-orbit update of the target functional module based on the updated configuration data.

[0148] In the above implementation scheme, the control field programmable logic gate array receives the target data corresponding to the target functional module that undergoes functional upgrade, extracts the target configuration data from the target data and sends it to the refresh chip. After the refresh chip obtains the target configuration data, it modifies the original configuration data stored and loads the latest configuration data to the baseband processing field programmable logic gate array to ensure the on-orbit update of the functional module.

[0149] As an optional embodiment, the method further includes:

[0150] The control field programmable logic gate array receives a control instruction sent by the satellite platform to instruct to disable a refresh function, wherein the control instruction is sent before the target data is sent;

[0151] The control field programmable logic gate array sends a refresh prohibition instruction to the refresh chip in response to the control instruction;

[0152] The refresh chip disables a refresh function in response to the refresh disable instruction.

[0153] Before sending target data to the control field programmable logic gate array, the satellite platform needs to send a control instruction to the control field programmable logic gate array to instruct to disable the refresh function. The control field programmable logic gate array sends a disable refresh instruction to the refresh chip according to the control instruction. The refresh chip responds to the received disable refresh instruction and disables the refresh function.

[0154] When the refresh function is disabled, the satellite platform provides the target data to the control field programmable logic gate array. After the control field programmable logic gate array verifies the target data and passes the verification, the control field programmable logic gate array extracts the target configuration data from the target data and sends it to the refresh chip. The refresh chip updates the original configuration data in the non-volatile memory based on the target configuration data. After the update is completed, all the configuration data is loaded into the baseband processing field programmable logic gate array. During this period, the refresh function is disabled to avoid affecting the on-orbit update of the target functional module.

[0155] When the refresh chip updates the original configuration data in the non-volatile memory based on the target configuration data, it determines the first configuration data before the update that is adapted to the target configuration data in the configuration data stored in the non-volatile memory, and then erases the first configuration data and burns the target configuration data into the non-volatile memory to achieve data update. The detailed process can be found in the relevant introduction of the aforementioned embodiment, which will not be further elaborated here.

[0156] For the refresh chip, it can return telemetry information to the control field programmable logic gate array. The telemetry information can be automatically sent periodically or based on trigger conditions. For details, please refer to the relevant introduction of the above embodiment. The control field programmable logic gate array can determine whether the baseband processing field programmable logic gate array has successfully loaded all the configuration data in the non-volatile memory based on the telemetry information returned by the refresh chip.

[0157] Among them, the telemetry information can also provide indication information on whether the current data packet has been updated. The target configuration data includes multiple data packets. The field programmable logic gate array is controlled to accumulate the number of data packets that have been updated based on the telemetry information. When the total number of data packets that have been updated is equal to the predicted total number of packets, it is determined that the configuration data in the non-volatile memory has been updated.

[0158] When the control field programmable logic gate array determines that the non-volatile memory has completed the configuration data update, it sends a reload instruction to the refresh chip, and the reload instruction instructs to load all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array. The refresh chip loads all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array according to the reload instruction, and reloads the configuration data in response to the reload instruction, so as to ensure that the baseband processing field programmable logic gate array runs the latest configuration data.

[0159] When the control field programmable logic gate array determines based on the telemetry information that all configuration data in the non-volatile memory is successfully loaded into the baseband processing field programmable logic gate array, the control field programmable logic gate array sends an enable refresh instruction to the refresh chip. The refresh chip enables the refresh function according to the enable refresh instruction to realize the recovery refresh function and regularly refresh the configuration bits of the baseband processing field programmable logic gate array.

[0160] The above introduces the FPGA on-orbit update method applied to the field programmable logic gate array on-orbit update system, which can implement all the steps of the FPGA on-orbit update method applied to control the field programmable logic gate array, and can achieve the same technical effect. The same or similar parts can be referenced to each other and will not be further elaborated here.

[0161] An embodiment of the present application also provides a global satellite navigation system occultation receiver, including the above-mentioned field programmable gate array on-orbit update system. By deploying the field programmable gate array on-orbit update system on the global satellite navigation system occultation receiver, on-orbit update of functional modules of the baseband processing FPGA can be implemented on the global satellite navigation system occultation receiver.

[0162] like Fig. 9 As shown, an embodiment of the present application further provides an electronic device, which may include: a processor (processor) 910, a communication interface (Communications Interface) 920, a memory (memory) 930 and a communication bus 940, wherein the processor 910, the communication interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 can call the logic instructions in the memory 930 to execute the steps of the field programmable logic gate array on-track update method provided in the embodiment of the present application.

[0163] In addition, the logic instructions in the above-mentioned memory 930 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0164] On the other hand, the embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in the on-track updating method of the field programmable logic gate array provided in the above embodiments are implemented. And the same technical effect can be achieved, so it will not be repeated here to avoid repetition.

[0165] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0166] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0167] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0168] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A field programmable logic gate array on-orbit update system, deployed on a global satellite navigation system occultation receiver, characterized in that: include: Control FPGA, Magnetic Random Access Memory, Refresh Chip, Non-Volatile Memory and Baseband Processing FPGA; The control field programmable logic gate array is connected to the magnetic random access memory and the refresh chip, and is used to receive target data corresponding to a target functional module sent by a satellite platform, cache the target data in the magnetic random access memory, extract target configuration data from the target data cached in the magnetic random access memory, and send the target configuration data to the refresh chip, wherein the target configuration data is updated configuration data corresponding to the target functional module, and the target data is generated by packaging the target configuration data according to the above-mentioned update data packet format, and the target functional module is at least one module of the multiple functional modules included in the baseband processing field programmable logic gate array that undergoes functional upgrade, and the multiple functional modules are all dynamically reconfigurable modules, and the multiple functional modules are independent of each other; The refresh chip is connected to the non-volatile memory and the baseband processing field programmable logic gate array, and is used to update the configuration data in the non-volatile memory based on the target configuration data, and load all the configuration data in the non-volatile memory to the baseband processing field programmable logic gate array after the update is completed; The refresh chip is also used to receive a reload instruction sent by the control field programmable logic gate array after the non-volatile memory completes the configuration data update based on the target configuration data, and return telemetry information to the control field programmable logic gate array; According to the reload instruction, all configuration data in the non-volatile memory are loaded into the baseband processing field programmable logic gate array; Wherein, the telemetry information can be used to determine whether the baseband processing field programmable logic gate array has successfully loaded all configuration data in the non-volatile memory; The telemetry information is further used to provide indication information of whether the current data packet has been updated, the target configuration data includes multiple data packets, the control field programmable logic gate array accumulates the number of data packets that have been updated based on the telemetry information, and determines that the configuration data in the non-volatile memory has been updated when the total number of data packets that have been updated is equal to the predicted total number of packets; The baseband processing field programmable logic gate array is used to perform data operation after loading all configuration data and perform on-orbit update of the target functional module.

2. The field programmable gate array on-orbit update system according to claim 1, characterized in that: The control field programmable logic gate array is also used for: Before receiving the target data, sending a refresh prohibition instruction to the refresh chip; When all configuration data in the non-volatile memory are successfully loaded into the baseband processing field programmable logic gate array, sending a refresh enable instruction to the refresh chip; The refresh prohibition instruction is sent by the control field programmable logic gate array after receiving a control instruction sent by the satellite platform, and the control instruction indicates to disable the refresh function.

3. The field programmable gate array on-orbit update system according to claim 1, characterized in that: The control field programmable logic gate array is also used to verify the target data cached in the magnetic random access memory, and if the verification is successful, extract the target configuration data and send the target configuration data to the refresh chip.

4. The field programmable gate array on-orbit update system according to claim 1, characterized in that: The refresh chip is also used to erase the first configuration data in the non-volatile memory and burn the target configuration data into the non-volatile memory; wherein the first configuration data is configuration data before updating that matches the target configuration data.

5. The field programmable gate array on-orbit update system according to claim 1, characterized in that: The baseband processing field programmable logic gate array includes at least the following functional modules: a clock synchronization module, an analog-to-digital conversion interface module, a real-time delay Doppler mapping module, a delay Doppler mapping data control module, an external memory interface module, a data transmission control module and a fast Fourier transform module; The functional modules included in the baseband processing field programmable logic gate array are respectively arranged in the dynamic reconstruction area of ​​the baseband processing field programmable logic gate array.

6. The field programmable gate array on-orbit update system according to claim 1, characterized in that: The target configuration data is determined by comparing the complete configuration data before updating corresponding to the baseband processing field programmable logic gate array and the complete configuration data after updating corresponding to the baseband processing field programmable logic gate array; The complete configuration data before updating is generated after obtaining a first netlist design checkpoint file, allocating hardware resources to a plurality of functional modules, and passing a design rule check, wherein the first netlist design checkpoint file includes complete design information associated with a top-level module and a plurality of functional modules, and the top-level module is used to integrate the plurality of functional modules; The updated complete configuration data is generated after obtaining the second netlist design checkpoint file and passing the design rule check. The second netlist design checkpoint file is generated by clearing the original design information of the target functional module with respect to the first netlist design checkpoint file and connecting to the upgraded design information of the target functional module.

7. A method for updating a field programmable logic gate array on-orbit, applied to control a field programmable logic gate array, characterized in that: The method comprises: Receive target data corresponding to a target functional module sent by a satellite platform, wherein the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, and the target configuration data is updated configuration data corresponding to the target functional module, and the target functional module is at least one module of a plurality of functional modules included in a baseband processing field programmable logic gate array, and the plurality of functional modules are all dynamically reconfigurable modules, and the plurality of functional modules are independent of each other; caching the target data into a magnetic random access memory; Extracting the target configuration data from the target data cached in the magnetic random access memory, sending the target configuration data to a refresh chip, allowing the refresh chip to update the configuration data in the non-volatile memory, and loading all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array; The baseband processing field programmable logic gate array completes the on-orbit update of the target functional module by running all the loaded configuration data; After the non-volatile memory completes configuration data update based on the target configuration data, sending a reload instruction to the refresh chip, the reload instruction instructing to load all configuration data in the non-volatile memory into the baseband processing field programmable logic gate array; Among them, the telemetry information returned by the refresh chip is used to provide indication information on whether the current data packet has been updated, the target configuration data includes multiple data packets, and the control field programmable logic gate array accumulates the number of data packets that have been updated based on the telemetry information. When the total number of data packets that have been updated is equal to the predicted total number of packets, it is determined that the configuration data in the non-volatile memory has been updated.

8. The on-orbit updating method of a field programmable gate array according to claim 7, characterized in that: The sending the target configuration data to the refresh chip includes: Verifying the target data cached in the magnetic random access memory; If the verification is successful, extracting the target configuration data; The target configuration data is sent to the refresh chip.

9. The on-orbit updating method of a field programmable gate array according to claim 7, characterized in that: The method further comprises: Before receiving the target data sent by the satellite platform, receiving a control instruction sent by the satellite platform to instruct to disable a refresh function; Sending a refresh prohibition instruction to the refresh chip according to the control instruction; When all configuration data in the non-volatile memory are successfully loaded into the baseband processing field programmable logic gate array, sending a refresh enable instruction to the refresh chip; The telemetry information returned by the refresh chip may be used to determine whether the baseband processing field programmable logic gate array has successfully loaded all configuration data in the non-volatile memory.

10. A method for updating a field programmable logic gate array on-orbit, applied to a field programmable logic gate array on-orbit updating system, characterized in that: The field programmable logic gate array on-orbit update system includes: a control field programmable logic gate array, a magnetic random access memory, a refresh chip, a non-volatile memory and a baseband processing field programmable logic gate array, and the method includes: The control field programmable logic gate array receives target data corresponding to a target functional module sent by a satellite platform and provides the target data to the magnetic random access memory, wherein the target data is generated by packaging target configuration data according to the above-mentioned update data packet format, and the target configuration data is updated configuration data corresponding to the target functional module, and the target functional module is at least one module of a plurality of functional modules included in the baseband processing field programmable logic gate array that undergoes a function upgrade, and the plurality of functional modules are all dynamically reconfigurable modules, and the plurality of functional modules are independent of each other; The magnetic random access memory receives and caches the target data sent by the control field programmable logic gate array; The control field programmable logic gate array extracts the target configuration data from the target data cached in the magnetic random access memory, and sends the target configuration data to the refresh chip; The refresh chip updates the configuration data in the non-volatile memory based on the target configuration data, and loads all the configuration data in the non-volatile memory into the baseband processing field programmable logic gate array after the update is completed; The baseband processing field programmable logic gate array performs data operation after loading all configuration data, and performs on-orbit update on the target functional module; The control field programmable logic gate array sends a reload instruction to the refresh chip when it is determined that the non-volatile memory has completed the configuration data update based on the target configuration data based on the telemetry information returned by the refresh chip; The telemetry information is used to provide indication information of whether the current data packet has been updated, the target configuration data includes multiple data packets, the control field programmable logic gate array accumulates the number of data packets that have been updated based on the telemetry information, and determines that the configuration data in the non-volatile memory has been updated when the total number of data packets that have been updated is equal to the predicted total number of packets; The reload instruction instructs to load all configuration data in the non-volatile memory into the baseband processing field programmable logic gate array.

11. The on-orbit updating method of a field programmable gate array according to claim 10, characterized in that: The method further comprises: The control field programmable logic gate array receives a control instruction sent by the satellite platform to instruct to disable a refresh function, wherein the control instruction is sent before the target data is sent; The control field programmable logic gate array sends a refresh prohibition instruction to the refresh chip in response to the control instruction; The refresh chip disables a refresh function in response to the refresh disable instruction.

12. The on-orbit updating method of a field programmable gate array according to claim 11, characterized in that: The method further comprises: The control field programmable logic gate array sends an enable refresh instruction to the refresh chip, wherein the enable refresh instruction is sent by the control field programmable logic gate array when it is determined that the baseband processing field programmable logic gate array has successfully loaded all configuration data in the non-volatile memory based on the telemetry information returned by the refresh chip; The refresh chip enables a refresh function in response to the enable refresh instruction.

13. The on-orbit updating method of a field programmable gate array according to claim 10, characterized in that: The step of extracting the target configuration data from the target data cached in the magnetic random access memory and sending the target configuration data to the refresh chip comprises: Verifying the target data cached in the magnetic random access memory; If the verification is successful, extracting the target configuration data; The target configuration data is sent to the refresh chip.

14. A global satellite navigation system occultation receiver, characterized in that: It comprises the field programmable gate array on-orbit update system as claimed in any one of claims 1 to 6.

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