FPGA accelerated programming method and device

Abstract

The present invention relates to the field of FPGA programming technology, and in particular to an FPGA accelerated programming method and device, the method comprising: firstly, dividing a CRAM module in a target FPGA chip into a plurality of CRAM submodules, and binding each CRAM submodule to a respective adjacent IP functional unit; then, based on an application scenario, obtaining the programming logic of the target FPGA chip; and finally, dynamically programming a specified CRAM submodule in the CRAM submodule through a state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit. The above scheme can accelerate programming time in FPGA applications, improve flexibility and programming efficiency, by dividing the CRAM module into a plurality of CRAM submodules and selecting a specified CRAM submodule for programming according to the application scenario.

Description

Technical Field

[0001] The present invention relates to the field of FPGA programming technology, and in particular to an FPGA accelerated programming method and device. Background Art

[0002] During the initialization phase of an FPGA chip (field programmable gate array), it is a standard process to use CRAM (configuration random access memory) for bitstream programming. CRAM is a dedicated memory in the FPGA chip used to store configuration information (i.e., bitstream), which is responsible for storing the bitstream data used to configure the internal logic units of the FPGA chip.

[0003] As the size of FPGA chips continues to increase, the number of components contained in them is also growing dramatically. These components may include logic gates, lookup tables, memory blocks, I / O interfaces, etc. During the programming process, these components need to be configured and tested one by one to ensure that they can correctly implement the intended functions. Therefore, the increase in the size of FPGA chips directly leads to the extension of programming time. Secondly, the bitstream programming of FPGA chips usually programs and tests all components one by one in sequence. Although this sequential programming method ensures high coverage testing, that is, each component is fully verified, it also brings time overhead.

[0004] In the above scheme, it takes a long time to program the entire FPGA chip using CRAM during the initialization phase of the FPGA chip, resulting in low programming efficiency and high cost. Summary of the invention

[0005] In view of this, the present invention provides an FPGA accelerated programming method and device to solve the problem that it takes a long time to program the entire FPGA chip using CRAM during the initialization phase of the FPGA chip, resulting in low programming efficiency and high cost.

[0006] In a first aspect, the present invention provides an FPGA accelerated programming method, the method is applied to a target FPGA chip, the target FPGA chip includes a CRAM module, an IP function unit and a state machine, the method includes:

[0007] Dividing the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules;

[0008] Binding each of the CRAM submodules to the respective adjacent IP functional units;

[0009] Based on the application scenario, the programming logic of the target FPGA chip is obtained; the programming logic indicates the specified IP functional units to be programmed and the programming order of the specified IP functional units;

[0010] According to the programming logic and the binding relationship between the CRAM sub-module and the IP functional unit, a specified CRAM sub-module in the CRAM sub-module is dynamically programmed through the state machine.

[0011] The above scheme divides the CRAM module into multiple CRAM sub-modules, and uses a state machine to independently and dynamically program a specified CRAM sub-module. A specified CRAM sub-module is selected for programming according to the application scenario, or multiple CRAM sub-modules are programmed at the same time to achieve parallel processing. This can speed up the programming time in FPGA applications and improve flexibility. This flexibility enables the system to be quickly adjusted and optimized according to different application scenarios and requirements.

[0012] In an optional implementation, dividing the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules includes:

[0013] The CRAM module in the target FPGA chip is evenly divided to evenly divide the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules; each of the CRAM sub-modules includes its own independent clock and data read and write transmission path.

[0014] In an optional implementation, the acquiring the programming logic of the target FPGA chip based on the application scenario includes:

[0015] Obtaining an application scenario of the target FPGA chip;

[0016] According to the application scenario, obtaining RTL register transfer level code;

[0017] The RTL register transfer level code is subjected to internal circuit analysis to obtain the programming logic of the target FPGA chip.

[0018] In an optional implementation, dynamically programming a specified CRAM submodule in the CRAM submodule by using the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit includes:

[0019] Based on the programming logic, obtaining the designated IP functional units to be programmed and the programming order of the designated IP functional units;

[0020] Based on the binding relationship between the CRAM submodule and the IP functional unit, obtaining a specified CRAM submodule corresponding to the specified IP functional unit;

[0021] Based on the programming sequence, the designated CRAM submodule is dynamically programmed by a state machine.

[0022] In an optional implementation, when dynamically programming a specified CRAM submodule in the CRAM submodule by the state machine, the method further includes:

[0023] Configuring a target clock signal; the target clock signal is used to drive the state machine and the data transmission process;

[0024] The rising edge and the falling edge of the target clock signal are used simultaneously to perform multi-directional shift programming on each designated CRAM submodule in the CRAM submodule through a state machine; the state machine is located in the middle of the FPGA chip.

[0025] The above scheme uses both the rising and falling edges of the clock to trigger the programming operation, which can significantly increase the programming speed. In addition, inputting the bit stream at the center and shifting the bit stream data in four directions, up, down, left, and right, can further speed up data transmission and programming. This design enables the system to complete CRAM programming and configuration in a shorter time.

[0026] In an optional implementation, when dynamically programming a specified CRAM submodule in the CRAM submodule by the state machine, the method further includes:

[0027] If the written data and the read-back data of the state machine are different, an error map is generated;

[0028] According to the error map, defective bits in the specified CRAM submodule are screened out.

[0029] The CRAM submodule in the above scheme can perform self-check write and read operations and generate an error map to skip defective bits. This self-check mechanism can detect and repair errors in the CRAM module in a timely manner to ensure data accuracy and reliability. By skipping defective bits, the yield of the CRAM module can be improved, and the system failure rate and maintenance cost can be reduced.

[0030] In an optional embodiment, the method further includes:

[0031] Determine key IP functional units and key control bits of the key IP functional units;

[0032] Redundant bits are configured for the key control bits, and three-state control processing is performed, so that when there are defects in the bits of the key control bits, they are replaced by redundant bits.

[0033] The above scheme can achieve that when one of the bits is defective, another redundant bit can be replaced by three-state control through redundant bits and three-state control processing, thereby further improving the yield.

[0034] In a second aspect, the present invention provides an FPGA accelerated programming device, which is applied to a target FPGA chip, wherein the target FPGA chip includes a CRAM module, an IP function unit, and a state machine, and the device includes:

[0035] A CRAM partitioning module, used to divide the CRAM module in the target FPGA chip into multiple CRAM sub-modules;

[0036] A functional unit binding module, used to bind each of the CRAM sub-modules to the respective adjacent IP functional units;

[0037] A programming logic acquisition module, used to acquire the programming logic of the target FPGA chip based on the application scenario; the programming logic indicates the specified IP functional units to be programmed and the programming order of the specified IP functional units;

[0038] A dynamic programming module is used to dynamically program a specified CRAM submodule in the CRAM submodule through the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit.

[0039] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute an FPGA accelerated programming method of the first aspect or any corresponding embodiment thereof.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute an FPGA accelerated programming method according to the first aspect or any corresponding embodiment thereof.

[0041] In a fifth aspect, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute an FPGA accelerated programming method according to the first aspect or any corresponding embodiment thereof.

[0042] The technical solution provided by the present invention may include the following beneficial effects:

[0043] The present invention divides a CRAM module into multiple CRAM submodules, and uses a state machine to independently and dynamically program a specified CRAM submodule, selects a specified CRAM submodule for programming according to an application scenario, or programs multiple CRAM submodules at the same time to achieve parallel processing, which can speed up programming time in FPGA applications and improve flexibility. This flexibility enables the system to be quickly adjusted and optimized according to different application scenarios and requirements;

[0044] The present invention uses both the rising and falling edges of the clock to trigger the programming operation, which can significantly increase the programming speed. In addition, the bit stream is input at the center position, and the bit stream data is shifted in four directions, which can further speed up the data transmission and programming speed. This design enables the system to complete the programming and configuration of CRAM in a shorter time.

[0045] The CRAM submodule in the present invention can perform self-checking write and read operations and generate an error map to skip defective bits. This self-checking mechanism can timely detect and repair errors in the CRAM module to ensure the accuracy and reliability of data. By skipping defective bits, the yield of the CRAM module can be improved, and the system failure rate and maintenance cost can be reduced;

[0046] The present invention uses redundant bits and three-state control processing to achieve that when one of the bits is defective, another redundant bit can be replaced by three-state control, thereby further improving the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 is a flowchart of an FPGA accelerated programming method according to an embodiment of the present invention;

[0049] Figure 2 is a flowchart of another FPGA accelerated programming method according to an embodiment of the present invention;

[0050] Figure 3 is a schematic diagram of average partitioning of CRAM modules in a target FPGA chip according to an embodiment of the present invention;

[0051] Figure 4 is a structural block diagram of an FPGA accelerated programming device according to an embodiment of the present invention;

[0052] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0054] According to an embodiment of the present invention, an embodiment of an FPGA accelerated programming method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0055] In this embodiment, a method for accelerating FPGA programming is provided. The method is applied to a target FPGA chip. The target FPGA chip includes a CRAM module, an IP function unit, and a state machine. Figure 1 is a flow chart of an FPGA accelerated programming method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0056] Step S101, dividing the CRAM module in the target FPGA chip into multiple CRAM sub-modules.

[0057] Specifically, dividing the CRAM module in the FPGA chip into multiple sub-modules can more effectively manage and utilize the resources of the CRAM module. Each CRAM sub-module can be independently configured and programmed to adapt to different storage requirements and data access modes, and perform specified programming. This flexibility allows designers to reasonably allocate and use the storage resources of the FPGA chip according to the requirements of specific applications. In addition, dividing the CRAM module into multiple sub-modules can achieve parallel processing, which means that different CRAM sub-modules can perform read and write operations at the same time without interfering with each other. In applications that need to process multiple data streams at the same time or require high-speed data access, system performance can be significantly improved.

[0058] Step S102: Bind each of the CRAM sub-modules to its adjacent IP functional unit.

[0059] Specifically, the IP functional unit refers to the internal programmable logic structure of the target FPGA chip, which is a pre-designed, reusable functional unit in the FPGA chip design, used to implement various digital circuit functions. The IP functional unit includes: DSP digital signal processing unit (used to implement digital signal processing algorithms), CLB basic logic unit (used to implement various complex logic functions) and PLL phase-locked loop (circuit for generating, adjusting or synchronizing clock signals).

[0060] By binding the CRAM sub-module to the adjacent IP functional unit, it is possible to ensure that data has the shortest path and lowest latency when transmitted between the CRAM sub-module and the IP functional unit, which helps reduce unnecessary wiring overhead and potential signal interference, thereby improving the performance of the entire system.

[0061] Step S103, based on the application scenario, obtain the programming logic of the target FPGA chip; the programming logic indicates the specified IP functional unit to be programmed and the programming order of the specified IP functional unit.

[0062] Specifically, this embodiment designs the programming logic of the FPGA chip according to the requirements of the application scenario (including the implementation of a specific algorithm, protocol, controller or interface, etc.), and the programming logic defines how each CRAM submodule in the FPGA chip works and how to communicate with each other. Through this process, the programming logic of the target FPGA chip can be obtained according to a specific application scenario, and it is ensured to have high performance, low power consumption and reliability in actual applications.

[0063] Step S104 , dynamically programming a designated CRAM submodule in the CRAM submodule through the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit.

[0064] Specifically, in FPGA chip design, when it comes to dynamic programming of CRAM submodules, this usually means changing the content or configuration of the CRAM submodule through a state machine while the FPGA chip is running. This dynamic programming capability enables FPGA chips to flexibly implement various data processing and control tasks. The state machine is a commonly used control structure in FPGA chip design, which is used to change its state according to input signals or internal conditions and perform corresponding operations. When the state machine is in a certain state, the CRAM submodule can be read or written according to the programming logic and binding relationship.

[0065] In dynamic programming, the following steps can be included:

[0066] The state machine determines the CRAM submodules and programming contents to be programmed according to the programming logic;

[0067] The state machine sends appropriate instructions to the specified IP functional unit or CRAM submodule controller;

[0068] The designated IP functional unit or CRAM submodule controller performs a programming operation to write data into the designated CRAM submodule bound to the designated IP functional unit, or read data from the designated CRAM submodule;

[0069] After programming is completed, the state machine will move to the next state and wait for the next programming event.

[0070] In summary, the present invention divides a CRAM module into multiple CRAM sub-modules, and uses a state machine to independently and dynamically program a specified CRAM sub-module, selects a specified CRAM sub-module for programming according to an application scenario, or programs multiple CRAM sub-modules at the same time to achieve parallel processing, which can speed up the programming time in FPGA applications and improve flexibility. This flexibility enables the system to be quickly adjusted and optimized according to different application scenarios and requirements.

[0071] In this embodiment, a method for accelerating FPGA programming is provided. The method is applied to a target FPGA chip. The target FPGA chip includes a CRAM module, an IP function unit, and a state machine. Figure 2 FIG. 1 is a flowchart of another FPGA accelerated programming method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0072] Step S201, performing an even division process on the CRAM module in the target FPGA chip to evenly divide the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules; each of the CRAM sub-modules includes its own independent clock and data read and write transmission path.

[0073] For details, see Figure 3 The schematic diagram of the average partitioning of the CRAM modules in the target FPGA chip is shown. Figure 3 The CRAM module of the target FPGA chip is evenly divided into eight CRAM sub-modules (such as CRAM_1, CRAM_2, CRAM_3, CRAM_4, CRAM_5, CRAM_6, CRAM_7, and CRAM_8), and each CRAM sub-module and adjacent IP functional units (such as Figure 3The DSP / CLB and PLL in the CRAM are bound, and an FSM (state machine) is used to independently program each CRAM submodule. Each CRAM submodule has its own independent clock and data read and write transmission path. Dynamic editing can input the RTL register transfer level code according to different application scenarios, analyze the internal circuit through the Synthesizer, and specify different parts of the CRAM submodule through state machine programming. For example, first program the specified IP functional unit (such as Figure 3 The four CRAM submodules in the left half, namely CRAM_1, CRAM_2, CRAM_3 and CRAM_4) and then skip other IP functional units (such as Figure 3 The four CRAM sub-modules in the right half, namely CRAM_5, CRAM_6, CRAM_7 and CRAM_8) are provided for subsequent use to speed up programming and provide flexibility.

[0074] When dividing, this embodiment first determines the total capacity of the CRAM module in the target FPGA chip, and then divides the CRAM module into eight parts as needed, each of which should have equal capacity for easy management and use. This embodiment also allocates an independent clock signal and an independent data read and write transmission path to each CRAM submodule. The independent clock signal will be used to synchronize the read and write operations and data transmission of the CRAM submodule. The independent data read and write transmission path can ensure that each CRAM submodule can exchange data efficiently with the bound IP functional unit.

[0075] Step S202: Bind each of the CRAM sub-modules to its adjacent IP functional unit.

[0076] For details, see Figure 3 In part ①, this embodiment first binds each CRAM submodule to the adjacent IP functional unit, and sets the corresponding data interface and control signal, and determines the data transmission method and protocol between each CRAM part and the IP functional unit according to the application requirements.

[0077] Step S203, based on the application scenario, obtain the programming logic of the target FPGA chip; the programming logic indicates the specified IP functional unit to be programmed and the programming order of the specified IP functional unit.

[0078] Specifically, step S203 includes:

[0079] Get the application scenario of the target FPGA chip;

[0080] According to the application scenario, obtain the RTL register transfer level code;

[0081] The RTL register transfer level code is subjected to internal circuit analysis to obtain the programming logic of the target FPGA chip.

[0082] Specifically, the programming process of the state machine FSM for the CRAM submodule includes reading, writing and updating data. This embodiment first designs the RTL register transfer level code according to different application scenarios. The RTL register transfer level code describes the connection relationship and operation mode between the internal hardware modules of the FPGA chip. After that, the designed RTL register transfer level code is analyzed and synthesized using the Syntherizer synthesizer. During the analysis process, the Syntherizer synthesizer will consider factors such as the division of the CRAM module, the binding with the IP functional unit, and the design of the state machine FSM, and generate the programming logic of the target FPGA chip to ensure that the generated hardware circuit can meet the application requirements.

[0083] Step S204 , dynamically programming a designated CRAM submodule in the CRAM submodule through the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit.

[0084] Specifically, step S204 includes:

[0085] Based on the programming logic, obtaining a designated IP functional unit to be programmed and a programming order of the designated IP functional unit;

[0086] Based on the binding relationship between the CRAM submodule and the IP functional unit, obtaining a specified CRAM submodule corresponding to the specified IP functional unit;

[0087] Based on the programming sequence, the designated CRAM sub-module is dynamically programmed through a state machine.

[0088] Step S205, when dynamically programming a specified CRAM sub-module in the CRAM sub-module through the state machine, the rising edge and the falling edge of the target clock signal are used simultaneously to perform multi-directional shift programming on each specified CRAM sub-module in the CRAM sub-module through the state machine; the state machine is located in the middle position of the FPGA chip.

[0089] Specifically, before performing multi-directional shift programming, this embodiment also needs to configure a target clock signal; the target clock signal is used to drive the state machine and the data transmission process.

[0090] For details, see Figure 3Part ②, this embodiment uses both the rising and falling edges of the target clock signal (double rate DDR, different from the traditional one that only uses the rising edge for transmission), and the state machine is placed in the middle of the FPGA chip, which can simultaneously read and write data to the left and right, and to the up and down data to transfer and shift the bit stream data to speed up the programming timing. Double rate DDR allows data to be transmitted twice in each clock cycle, once on the rising edge of the clock and the other on the falling edge of the clock, which can effectively double the data transmission rate, and the state machine is set in the middle of the FPGA chip to control the read, write, transfer and shift operations of the data. Exemplarily, if each designated CRAM submodule in the CRAM submodule is Figure 3 The four CRAM sub-modules in the left half (ie, CRAM_1, CRAM_2, CRAM_3 and CRAM_4) can be programmed in parallel with multi-directional shifts through the state machine.

[0091] Step S206, when dynamically programming a specified CRAM submodule in the CRAM submodule through the state machine, if the write data and the readback data of the state machine are different, an error map is generated, and defective bits in the specified CRAM submodule are screened out according to the error map.

[0092] For details, see Figure 3 In the third part, in this embodiment, the state machine can perform self-check write and read operations (FSMError map). When the written data and the read-back data are different, an error map is generated to skip the defective bit, thereby improving the yield. A defective bit refers to a memory cell with defects or errors in a CRAM module or a CRAM submodule. CRAM is a special memory that allows fast search based on stored content rather than addresses. However, during the manufacturing process of CRAM, some memory cells may be defective due to various reasons (such as manufacturing errors, material problems, etc.), causing them to be unable to store or read data correctly. These defective memory cells are called defective bits. When the state machine dynamically programs and verifies the specified CRAM submodule, if it is found that the written and read-back data are inconsistent, it may mean that the specified CRAM submodule has a defective bit. In order to deal with this situation, this implementation generates an error map, which records in detail which locations have defects. Based on this error map, these defective memory cells can be screened out to avoid affecting the performance and reliability of the entire CRAM module in subsequent use.

[0093] In this embodiment, a defective bit does not mean that the entire CRAM submodule is defective. A CRAM submodule may contain only a few defective bits, while most other storage cells are working normally. Therefore, by screening and isolating these defective bits, the remaining normally working storage cells can be utilized to the maximum extent, thereby maintaining the performance and reliability of the entire CRAM submodule.

[0094] Step S207, determining the key IP functional unit and the key control bit of the key IP functional unit, configuring redundant bits for the key control bits, and performing tri-state control processing, so that when there is a defect in the bit of the key control bit, it can be replaced by the redundant bit.

[0095] For details, see Figure 3 Part ④, in this embodiment, for key IP functional units (such as PLL functional units), two bits (redundant bits) and three-state control are used to drive the same PLL position. When one of the bits is defective, the other redundant bit can be replaced by three-state control to improve the yield.

[0096] Among them, the redundant bit provides two physically independent bits for the key control bits of the PLL functional unit, namely a main bit and a redundant bit, and these two bits are designed to be able to drive the same position or function of the PLL. The three-state control is used to ensure that at any time, only one bit (main bit or redundant bit) is active and the other is disabled. During the manufacturing process or during system operation, the main bit can be tested or monitored to detect whether there is a defect. If the main bit is found to be defective, the three-state control logic will switch to the redundant bit to replace the main bit to drive the PLL functional unit. In this way, even if the main bit is defective, the redundant bit can be relied on to provide correct control or configuration, and the entire PLL functional unit can still work normally, greatly improving the yield and reliability of the entire system, without the need to discard the entire PLL functional unit or higher-level components due to a small manufacturing defect.

[0097] In summary, the present invention divides a CRAM module into multiple CRAM sub-modules, and uses a state machine to independently and dynamically program a specified CRAM sub-module, selects a specified CRAM sub-module for programming according to an application scenario, or programs multiple CRAM sub-modules at the same time to achieve parallel processing, which can speed up the programming time in FPGA applications and improve flexibility. This flexibility enables the system to be quickly adjusted and optimized according to different application scenarios and requirements.

[0098] The present invention uses both the rising and falling edges of the clock to trigger the programming operation, which can significantly increase the programming speed. In addition, the bit stream is input at the center position, and the bit stream data is shifted in four directions, which can further speed up the data transmission and programming speed. This design enables the system to complete the programming and configuration of CRAM in a shorter time.

[0099] The CRAM submodule in the present invention can perform self-checking write and read operations and generate an error map to skip defective bits. This self-checking mechanism can timely detect and repair errors in the CRAM module to ensure the accuracy and reliability of data. By skipping defective bits, the yield of the CRAM module can be improved, and the system failure rate and maintenance cost can be reduced;

[0100] The present invention uses redundant bits and three-state control processing to achieve that when one of the bits is defective, another redundant bit can be replaced by three-state control, thereby further improving the yield.

[0101] In this embodiment, an FPGA accelerated programming device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0102] This embodiment provides an FPGA accelerated programming device, which is applied to a target FPGA chip. The target FPGA chip includes a CRAM module, an IP function unit, and a state machine. Figure 4 As shown, the device comprises:

[0103] A CRAM partition module 401, used to partition the CRAM module in the target FPGA chip into multiple CRAM sub-modules;

[0104] The function unit binding module 402 is used to bind each of the CRAM sub-modules with the adjacent IP function units;

[0105] The programming logic acquisition module 403 is used to acquire the programming logic of the target FPGA chip based on the application scenario; the programming logic indicates the specified IP functional unit to be programmed and the programming order of the specified IP functional unit;

[0106] The dynamic programming module 404 is used to dynamically program a specified CRAM submodule in the CRAM submodule through the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit.

[0107] In some optional implementations, the CRAM partition module 401 is further configured to:

[0108] The CRAM module in the target FPGA chip is evenly divided into a plurality of CRAM sub-modules; each of the CRAM sub-modules includes its own independent clock and data read and write transmission path.

[0109] In some optional implementations, the programming logic acquisition module 403 is further used to:

[0110] Get the application scenario of the target FPGA chip;

[0111] According to the application scenario, obtain RTL register transfer level code;

[0112] The RTL register transfer level code is subjected to internal circuit analysis to obtain the programming logic of the target FPGA chip.

[0113] In some optional implementations, the dynamic programming module 404 is further used to:

[0114] Based on the programming logic, obtaining a designated IP functional unit to be programmed and a programming order of the designated IP functional unit;

[0115] Based on the binding relationship between the CRAM submodule and the IP functional unit, obtaining a specified CRAM submodule corresponding to the specified IP functional unit;

[0116] Based on the programming sequence, the designated CRAM sub-module is dynamically programmed through a state machine.

[0117] In some optional embodiments, the device is also used for:

[0118] Configure a target clock signal; the target clock signal is used to drive the state machine and the data transmission process;

[0119] The rising edge and the falling edge of the target clock signal are used simultaneously to perform multi-directional shift programming on each designated CRAM submodule in the CRAM submodule through a state machine; the state machine is located in the middle of the FPGA chip.

[0120] In some optional embodiments, the device is also used for:

[0121] If the written data and the read-back data of the state machine are different, an error map is generated;

[0122] According to the error map, defective bits in the specified CRAM submodule are screened out.

[0123] In some optional embodiments, the device is also used for:

[0124] Determine the key IP functional unit and the key control bit of the key IP functional unit;

[0125] A redundant bit is configured for the key control bit, and a three-state control process is performed, so that when a defect exists in the bit of the key control bit, the redundant bit is used to replace it.

[0126] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0127] In this embodiment, an FPGA accelerated programming device is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0128] The embodiment of the present invention also provides a computer device having the above Figure 4 An FPGA accelerated programming device is shown.

[0129] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0130] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0131] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0132] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0133] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0134] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0135] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0136] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0137] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for accelerating FPGA programming, characterized in that: The method is applied to a target FPGA chip, the target FPGA chip includes a CRAM module, an IP function unit and a state machine, and the method includes: Dividing the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules; Binding each of the CRAM submodules to the respective adjacent IP functional units; Based on the application scenario, the programming logic of the target FPGA chip is obtained; the programming logic indicates the specified IP functional units to be programmed and the programming order of the specified IP functional units; According to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit, dynamically programming a specified CRAM submodule in the CRAM submodule through the state machine; When dynamically programming a specified CRAM submodule in the CRAM submodules by the state machine, the method further includes: Configuring a target clock signal; the target clock signal is used to drive the state machine and the data transmission process; The rising edge and the falling edge of the target clock signal are used simultaneously to perform multi-directional shift programming on each designated CRAM submodule in the CRAM submodule through a state machine; the state machine is located in the middle of the FPGA chip.

2. The method according to claim 1, characterized in that The step of dividing the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules comprises: The CRAM module in the target FPGA chip is evenly divided to evenly divide the CRAM module in the target FPGA chip into a plurality of CRAM sub-modules; each of the CRAM sub-modules includes its own independent clock and data read and write transmission path.

3. The method according to claim 1, characterized in that The step of obtaining the programming logic of the target FPGA chip based on the application scenario includes: Obtaining an application scenario of the target FPGA chip; According to the application scenario, obtaining RTL register transfer level code; The RTL register transfer level code is subjected to internal circuit analysis to obtain the programming logic of the target FPGA chip.

4. The method according to claim 1, characterized in that: When dynamically programming a specified CRAM submodule in the CRAM submodules by the state machine, the method further includes: If the written data and the read-back data of the state machine are different, an error map is generated; According to the error map, defective bits in the specified CRAM submodule are screened out.

5. The method according to claim 1, characterized in that The method further comprises: Determine key IP functional units and key control bits of the key IP functional units; Redundant bits are configured for the key control bits, and three-state control processing is performed, so that when there are defects in the bits of the key control bits, they are replaced by redundant bits.

6. An FPGA accelerated programming device, characterized in that: The device is applied to a target FPGA chip, the target FPGA chip includes a CRAM module, an IP function unit and a state machine, and the device includes: A CRAM partitioning module, used to divide the CRAM module in the target FPGA chip into multiple CRAM sub-modules; A functional unit binding module, used to bind each of the CRAM sub-modules to the respective adjacent IP functional units; A programming logic acquisition module, used to acquire the programming logic of the target FPGA chip based on the application scenario; the programming logic indicates the specified IP functional units to be programmed and the programming order of the specified IP functional units; A dynamic programming module, configured to dynamically program a specified CRAM submodule in the CRAM submodule through the state machine according to the programming logic and the binding relationship between the CRAM submodule and the IP functional unit; The dynamic programming module is also used for: When dynamically programming a specified CRAM submodule in the CRAM submodule by the state machine, configuring a target clock signal; the target clock signal is used to drive the state machine and the data transmission process; The rising edge and the falling edge of the target clock signal are used simultaneously to perform multi-directional shift programming on each designated CRAM submodule in the CRAM submodule through a state machine; the state machine is located in the middle of the FPGA chip.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes an FPGA accelerated programming method according to any one of claims 1 to 5 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute an FPGA accelerated programming method according to any one of claims 1 to 5.

9. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute an FPGA accelerated programming method according to any one of claims 1 to 5.

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