Chip watermark protection method, device, equipment and readable storage medium

Abstract

The present invention discloses a chip watermark protection method, device, equipment and readable storage medium, which relates to the field of integrated circuit design technology, including: obtaining target identification information of a core module to be protected in a chip; submitting the target identification information to a watermark management agency; receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information; mapping the watermark sequence to the state machine corresponding to the core module to be protected according to a preset watermark mapping method based on the initial watermark information to obtain the target embedded watermark information; and performing watermark protection on the core module to be protected using the target embedded watermark information. The chip watermark protection method provided by the present invention solves the problems of the difficulty and high cost of traditional chip protection means in determining whether a specific user has illegally obtained an IP core, and will not affect the normal function of the core module to be protected. The implementation method is simple, and the chip protection cost is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a chip watermark protection method, device, equipment and readable storage medium. Background Art

[0002] Integrated circuits are divided into different design units, and IP (Intellectual Property) cores are used to combine these units. The use of IP cores has greatly accelerated the design of digital integrated circuits, and illegal users can significantly reduce R&D costs by using IP. IP cores are usually stored in memory devices in the form of files, and are easily illegally copied, forged, transferred or overused during use.

[0003] Traditional chip protection methods are mainly through non-disclosure agreements or integrated circuit layout copyrights, which are difficult and costly in determining whether a specific user has illegally obtained an IP core.

[0004] In summary, how to effectively solve the problems of difficulty and high cost in determining whether a specific user has illegally obtained an IP core by traditional chip protection means is an issue that technicians in this field urgently need to solve. Summary of the invention

[0005] The purpose of the present invention is to provide a chip watermark protection method, which will not affect the normal function of the core module to be protected, is simple to implement, and greatly reduces the chip protection cost; another purpose of the present invention is to provide a chip watermark protection device, equipment and computer-readable storage medium.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] A chip watermark protection method, comprising:

[0008] Obtain target identification information of the core module to be protected in the chip;

[0009] Submitting the target identification information to a watermark management agency;

[0010] Receiving initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information;

[0011] According to the initial watermark information, a watermark sequence mapping is performed on the state machine corresponding to the core module to be protected in accordance with a preset watermark mapping method to obtain target embedded watermark information;

[0012] The target embedded watermark information is used to perform watermark protection on the core module to be protected.

[0013] In a specific implementation of the present invention, receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information includes:

[0014] The initial watermark information returned by the watermark management agency after the watermark management agency adds a timestamp to the target identification information and performs encryption and hash processing is received.

[0015] In a specific implementation of the present invention, receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information includes:

[0016] Receive initial watermark information of a preset bit length returned by the watermark management agency after encrypting and hashing the target identification information.

[0017] In a specific implementation of the present invention, receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information includes:

[0018] The initial watermark information returned by the watermark management agency after the target identification information is encrypted, hashed and encoded using a Huffman compression coding algorithm is received.

[0019] In a specific implementation of the present invention, receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information includes:

[0020] Receive the initial watermark information returned by the watermark management agency after encrypting, hashing and error-correcting the target identification information.

[0021] In a specific implementation of the present invention, performing watermark sequence mapping on the state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner includes:

[0022] A watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected according to the initial watermark information and in a preset watermark mapping manner.

[0023] In a specific implementation of the present invention, performing watermark sequence mapping on the finite state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner includes:

[0024] The finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding a state to obtain an adjusted finite state machine;

[0025] The adjusted finite state machine is subjected to watermark sequence mapping according to the initial watermark information and the preset watermark mapping method.

[0026] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, including:

[0027] The finite state machine corresponding to the core module to be protected is adjusted by extending the number of output bits, extending the number of input bits and adding states.

[0028] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, including:

[0029] The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits and adding states.

[0030] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, including:

[0031] The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits.

[0032] In a specific implementation of the present invention, performing watermark sequence mapping on the finite state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner includes:

[0033] According to the initial watermark information, a watermark sequence is mapped to the finite state machine corresponding to the core module to be protected in an output direct mapping manner.

[0034] In a specific implementation of the present invention, performing watermark sequence mapping on the finite state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner includes:

[0035] According to the initial watermark information, a watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected in an input-output mapping manner.

[0036] In a specific implementation of the present invention, performing watermark sequence mapping on the finite state machine corresponding to the core module to be protected in an input-output mapping manner according to the initial watermark information includes:

[0037] Randomly selecting a state of a finite state machine corresponding to the core module to be protected to obtain a first state;

[0038] Obtaining the number of original input bits of the finite state machine;

[0039] Determine a first output bit group corresponding to the first state according to the initial watermark information;

[0040] Randomly generate a first input bit group of the original input bit number;

[0041] determining whether the first input bit group is unused in the first state;

[0042] If yes, randomly select the jump state of the first state in the finite state machine to obtain the second state, so as to complete the mapping of the current first output bit group to the watermark sequence of the finite state machine;

[0043] The current second state is determined as a new first state, and the step of determining a first output bit group corresponding to the first state according to the initial watermark information is repeatedly performed until the watermark sequence mapping is completed according to the initial watermark information.

[0044] In a specific implementation manner of the present invention, when it is determined that the first input bit group has been used in the first state, the method further includes:

[0045] Acquire a second input bit group of each associated jump state of the first state in the finite state machine;

[0046] Determine whether there is a second input bit group consistent with the first output bit group in each second input bit group;

[0047] If yes, mapping the current first output bit group to the finite state machine through the associated jump state corresponding to the first state, the first input bit group, the first output bit group, and the second input bit group consistent with the first output bit group, performing a watermark sequence mapping;

[0048] The associated jump state corresponding to the second input bit group consistent with the first output bit group is determined as a new first state, and the step of determining the first output bit group corresponding to the first state according to the initial watermark information is repeated until the watermark sequence mapping is completed according to the initial watermark information.

[0049] In a specific implementation manner of the present invention, when it is determined that there is no second input bit group consistent with the first output bit group in each second input bit group, the method further includes:

[0050] Expanding the finite state machine by adding input bits;

[0051] A new first input bit group obtained by expanding the first input bit group is obtained, and the step of randomly selecting a jump state of the first state in the finite state machine is repeatedly performed.

[0052] In a specific implementation of the present invention, the finite state machine is expanded by adding input bits, including:

[0053] The finite state machine is extended by assigning a first logic value to an input bit of an existing jump in the finite state machine, and assigning a second logic value to an input bit of a watermark jump to be added in the finite state machine.

[0054] In a specific implementation of the present invention, after watermark protection is performed on the core module to be protected by using the target embedded watermark information, the method further includes:

[0055] When a watermark extraction request is received, a target core module is obtained after watermark protection is performed on the core module to be protected;

[0056] The target embedded watermark information is extracted from the target core module.

[0057] In a specific implementation of the present invention, after extracting the target embedded watermark information from the target core module, the method further includes:

[0058] Acquire a watermark detection sequence from the target embedded watermark information;

[0059] Input the watermark detection sequence into the state machine corresponding to the core module to be protected to obtain an output watermark sequence;

[0060] Obtaining the initial watermark information from the watermark management agency;

[0061] Determine a sequence to be compared according to the preset watermark mapping mode, the watermark detection sequence and the output watermark sequence;

[0062] Comparing the sequence to be compared with the initial watermark information to obtain a comparison result;

[0063] A watermark detection result is determined according to the comparison result.

[0064] A chip watermark protection device, comprising:

[0065] An identification information acquisition unit, used to acquire target identification information of a core module to be protected in the chip;

[0066] An identification information submitting unit, used to submit the target identification information to a watermark management agency;

[0067] An initial watermark information receiving unit, used to receive the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information;

[0068] A target embedded watermark information obtaining unit is used to perform watermark sequence mapping on the state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner to obtain target embedded watermark information;

[0069] The watermark protection unit is used to perform watermark protection on the core module to be protected by using the target embedded watermark information.

[0070] A chip watermark protection device, comprising:

[0071] Memory for storing computer programs;

[0072] A processor is used to implement the steps of the chip watermark protection method as described above when executing the computer program.

[0073] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip watermark protection method described above are implemented.

[0074] A computer program product includes a computer program, which implements the steps of the chip watermark protection method as described above when executed by a processor.

[0075] The chip watermark protection method provided by the present invention obtains target identification information of a core module to be protected in a chip; submits the target identification information to a watermark management agency; receives initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information; performs watermark sequence mapping on a state machine corresponding to the core module to be protected in accordance with a preset watermark mapping method based on the initial watermark information to obtain target embedded watermark information; and performs watermark protection on the core module to be protected using the target embedded watermark information.

[0076] It can be seen from the above technical solution that by processing the target identification information of the core module to be protected to obtain the initial watermark information and storing it in the watermark management agency, the watermark management agency is used to manage the legal watermark database, and the authority of the watermark management agency is fully utilized. By encrypting and hashing the target identification information, the embedding overhead can be reduced while ensuring the watermark capacity. By combining the initial watermark information and the characteristics of the state machine corresponding to the core module to be protected, the state machine corresponding to the core module to be protected is mapped to a watermark sequence according to a preset watermark mapping method to obtain the target embedded watermark information, and the target embedded watermark information is embedded in a suitable state without affecting the normal function of the core module to be protected. The implementation method of chip watermark protection is simple, which greatly reduces the chip protection cost.

[0077] Correspondingly, the present invention also provides a chip watermark protection device, equipment and computer-readable storage medium corresponding to the above-mentioned chip watermark protection method, which have the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0079] Figure 1 This is a flowchart of the implementation of the first chip watermark protection method in an embodiment of the present invention;

[0080] Figure 2 This is a structural block diagram of a chip watermark protection system in an embodiment of the present invention;

[0081] Figure 3 A schematic diagram of the structure of a state machine in an embodiment of the present invention;

[0082] Figure 4 It is a structural block diagram of a watermarking state machine in an embodiment of the present invention;

[0083] Figure 5 This is a flowchart of the implementation of the second chip watermark protection method in an embodiment of the present invention;

[0084] Figure 6 It is a schematic diagram of an embedding example of a first type of sequential finite state machine in an output direct mapping mode in an embodiment of the present invention;

[0085] Figure 7 It is a schematic diagram of an embedding example of a second sequential finite state machine in an output direct mapping mode in an embodiment of the present invention;

[0086] Figure 8 It is a schematic diagram of an embedding example of a third sequential finite state machine in an output direct mapping mode in an embodiment of the present invention;

[0087] Fig. 9 It is a schematic diagram of an embedding example of a first sequential finite state machine in an input-output mapping mode in an embodiment of the present invention;

[0088] Fig.10 Schematic diagram of an embedding example of a second sequential finite state machine in an input-output mapping mode in an embodiment of the present invention;

[0089] Fig.11 Schematic diagram of an embedding example of a third sequential finite state machine in an input-output mapping mode in an embodiment of the present invention;

[0090] Fig.12 Schematic diagram of an embedding example of a fourth sequential finite state machine in an input-output mapping mode in an embodiment of the present invention;

[0091] Fig.13 This is a structural block diagram of a chip watermark protection device in an embodiment of the present invention;

[0092] Fig.14 This is a structural block diagram of a chip watermark protection device in an embodiment of the present invention;

[0093] Fig.15 A schematic diagram of the specific structure of a chip watermark protection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0094] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0095] See also Figure 1 , Figure 1 This is a flow chart of the implementation of the first chip watermark protection method in an embodiment of the present invention. The method may include the following steps:

[0096] S101: Obtain target identification information of a core module to be protected in a chip.

[0097] The current mainstream digital integrated circuit development adopts a top-down design method, which divides the integrated circuit into different design units and combines these units with the core modules to be protected (i.e., IP cores) that have been fully tested and verified. When it is necessary to perform watermark protection on the core modules to be protected in the chip, the target identification information of the core modules to be protected in the chip is obtained.

[0098] The target identification information may be any information that can uniquely identify the owner of the chip, such as the name of the owner.

[0099] S102: Submit the target identification information to the watermark management agency.

[0100] See also Figure 2 , Figure 2 This is a structural block diagram of a chip watermark protection system in an embodiment of the present invention. A watermark management agency is pre-set to centrally manage the watermark information of each chip owner. The watermark management agency is used to manage a legal watermark database, and then an authoritative property certificate can be issued by comparing the database. After obtaining the target identification information of the core module to be protected in the chip, the target identification information is submitted to the watermark management agency.

[0101] S103: Receive the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information.

[0102] like Figure 2 As shown, the watermark management agency pre-stores an asymmetric encryption algorithm for encrypting the identification information of the core module to be protected. After receiving the target identification information, the watermark management agency encrypts the target identification information using a preset asymmetric encryption algorithm to obtain ciphertext identification information. After obtaining the ciphertext identification information, the ciphertext identification information is hashed, such as using a one-way hash function to hash the ciphertext identification information to obtain initial watermark information, that is, a brief summary information.

[0103] After obtaining the initial watermark information, the watermark management agency stores the initial watermark information for subsequent verification of products with questionable ownership, that is, by judging whether the output after inputting the detection sequence into the product with questionable ownership is the initial watermark information, and then verifying the ownership. After obtaining the initial watermark information, the watermark management agency returns the initial watermark information to the chip management center, and the chip management center receives the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information. By setting up a watermark management agency to centrally manage the watermark information of each chip owner, it is prevented that infringers search for ghost watermarks (i.e., non-existent watermarks) and regard them as their own watermarks. The watermark management agency encrypts and hashes the target identification information of the core module to be protected to obtain a short summary information, and embeds the short summary information into the chip to reduce the watermark embedding overhead. By encrypting and hashing the target identification information, the infringer cannot find the message with the same hash value corresponding to the original summary through the summary information by using calculation means. Only a fixed bit length is needed to ensure that the watermark has a certain strength, thereby improving security.

[0104] The chip management center may be a processor connected to both the chip to which the core module to be protected belongs and the watermark management mechanism.

[0105] The initial watermark information contains different contents depending on the watermark mapping method. In the output direct mapping method, the initial watermark information only contains the output sequence. In the input-output mapping method, the initial watermark information contains both the input detection sequence and the output sequence.

[0106] In a specific implementation of the present invention, step S103 may include the following steps:

[0107] The receiving watermark management agency stamps the target identification information with a timestamp and performs encryption and hash processing to return the initial watermark information.

[0108] The watermark management agency adds a timestamp when generating the initial watermark information corresponding to the core module to be protected. The chip management center receives the initial watermark information returned by the watermark management agency after adding a timestamp to the target identification information and performing encryption and hashing. Adding a timestamp can prevent infringers from adding their own watermarks in the system, thereby improving the reliability of chip watermark protection.

[0109] In a specific implementation of the present invention, step S103 may include the following steps:

[0110] The receiving watermark management agency encrypts and hashes the target identification information and returns the initial watermark information of the preset bit length.

[0111] The watermark management agency pre-specifies a certain number of bits with sufficient length to distinguish and track different property owners, and receives the initial watermark information of the preset bit length returned by the watermark management agency after encrypting and hashing the target identification information. The property owner can choose to use target identification information of any length to prove its property rights, and finally obtain the initial watermark information of the preset bit length by encrypting and hashing the target identification information, so that only a fixed bit length is needed to ensure that the watermark has a certain strength. It also avoids the risk that different target identification information may vary greatly in length and form and be easily identified.

[0112] It should be noted that the preset bit length can be set and adjusted according to actual conditions, and the embodiment of the present application does not limit this. For example, it can be set to 128 bits.

[0113] In a specific implementation of the present invention, step S103 may include the following steps:

[0114] The receiving watermark management agency encrypts and hashes the target identification information and encodes it using the Huffman compression coding algorithm to return the initial watermark information.

[0115] After the target identification information is encrypted and hashed, it is encoded using the Huffman compression coding algorithm to finally obtain the initial watermark information. The receiving watermark management agency encrypts and hashes the target identification information and encodes it using the Huffman compression coding algorithm to return the initial watermark information. By using the Huffman compression coding algorithm for encoding, the amount of information is further compressed, and the watermark embedding overhead is further reduced.

[0116] In a specific implementation of the present invention, step S103 may include the following steps:

[0117] The receiving watermark management agency encrypts, hashes and performs error correction coding on the target identification information and returns the initial watermark information.

[0118] After the target identification information is encrypted and hashed, error correction coding is performed to finally obtain the initial watermark information. The receiving watermark management agency encrypts, hashes and error-corrects the target identification information and returns the initial watermark information. By adopting error correction coding, the fault tolerance of digital watermark information is improved, and the watermark's ability to resist local removal attacks is improved. When part of the watermark information of the state machine is lost or damaged, the watermark information may also be recognized through other parts of the information.

[0119] S104: Perform watermark sequence mapping on the state machine corresponding to the core module to be protected according to the initial watermark information and a preset watermark mapping method to obtain target embedded watermark information.

[0120] After receiving the initial watermark information, the watermark sequence mapping is performed on the state machine corresponding to the core module to be protected according to the initial watermark information and in accordance with a preset watermark mapping method to obtain the target embedded watermark information.

[0121] The target embedded watermark information contains both the input detection sequence and the output sequence.

[0122] See also Figure 3 , Figure 3 The figure is a schematic diagram of the structure of a state machine in an embodiment of the present invention. Data paths and control logic are two main components in digital integrated circuits. Finite state machines are a basic sequential circuit commonly used in digital circuit control logic. Most designs contain finite state machines to control the actions of data paths. Finite state machines are mainly used to describe system behavior and state transitions. They consist of a set of states and transitions between states, which are usually triggered by input signals and clocks. When specific conditions are met, the state machine will switch from the current state to the next state and update the output accordingly. Figure 3 The functional input refers to the original input information that the core module to be protected needs to input in order to realize its function.

[0123] Finite state machines are divided into two types according to whether their state transitions are fully specified. One is the fully specified type, which means that a unique output sequence can be generated for any input sequence. The other is the incompletely specified type, which means that there is at least one set of input sequences that either has no specified output or no specified target state, that is, there is an unspecified target state or jump relationship.

[0124] See also Figure 4 , Figure 4 The block diagram is a structural diagram of a watermarked state machine in an embodiment of the present invention. If a certain input sequence of a finite state machine does not specify a target state or output, it is called a free input sequence. Similarly, if a certain output sequence of a finite state machine can only be generated by an unspecified input sequence, it is called a free output sequence. The state machine watermark information is added using the free input and output sequences of the incompletely specified finite state machine. If the finite state machine is fully specified or does not have enough free inputs, it is impossible to directly add a watermark to it. At this time, additional free inputs can be added to convert the original finite state machine into a finite state machine with enough free inputs and outputs to add a watermark. Figure 4 The function input corresponding to the external input and the watermark input corresponding to the detection sequence are selected through the multiplexer (MUX). The state machine to be watermarked is obtained through watermark enabling. After the output watermark sequence is obtained, it is used for subsequent watermark detection.

[0125] S105: Perform watermark protection on the core module to be protected using the target embedded watermark information.

[0126] After obtaining the target embedded watermark information, the target embedded watermark information is embedded into a suitable state, and the target embedded watermark information is used to perform watermark protection on the core module to be protected. This will not affect the normal function of the core module to be protected, and the implementation method of chip watermark protection is simple, which greatly reduces the chip protection cost.

[0127] The beneficial effect of the present invention is that the target identification information of the core module to be protected is processed to obtain the initial watermark information, which is stored in the watermark management agency, and the watermark management agency is used to manage the legal watermark database, thereby making full use of the authority of the watermark management agency. By encrypting and hashing the target identification information, the embedding overhead can be reduced while ensuring the watermark capacity. By combining the initial watermark information and the characteristics of the state machine corresponding to the core module to be protected, the state machine corresponding to the core module to be protected is mapped to a watermark sequence according to a preset watermark mapping method to obtain the target embedded watermark information, and the target embedded watermark information is embedded in a suitable state without affecting the normal function of the core module to be protected. The implementation method of chip watermark protection is simple, which greatly reduces the chip protection cost.

[0128] It should be noted that, based on the above embodiment, the embodiment of the present invention also provides corresponding improved solutions. In the subsequent embodiments, the same steps or corresponding steps as those in the above embodiment can be referenced to each other, and the corresponding beneficial effects can also be referenced to each other, which will not be repeated one by one in the following improved embodiments.

[0129] See also Figure 5 , Figure 5 This is a flow chart of the implementation of the second chip watermark protection method in an embodiment of the present invention. The method may include the following steps:

[0130] S501: Obtain target identification information of a core module to be protected in a chip.

[0131] S502: Submit the target identification information to the watermark management agency.

[0132] S503: Receive the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information.

[0133] S504: Perform watermark sequence mapping on the finite state machine corresponding to the core module to be protected according to the initial watermark information and a preset watermark mapping method to obtain target embedded watermark information.

[0134] After receiving the initial watermark information, the finite-state machine (FSM) corresponding to the protected core module is mapped to a watermark sequence according to the preset watermark mapping method based on the initial watermark information to obtain the target embedded watermark information, making full use of the flexibility and scalability of the finite state machine.

[0135] S505: Perform watermark protection on the core module to be protected using the target embedded watermark information.

[0136] S506: When a watermark extraction request is received, a target core module after watermark protection is completed on the core module to be protected is obtained.

[0137] After the core module to be protected is watermarked using the target embedded watermark information, when the ownership of the core module to be protected needs to be verified, a watermark extraction request is sent to the chip management center. When the chip management center receives the watermark extraction request, it obtains the target core module after the watermark protection of the core module to be protected is completed.

[0138] S507: Extracting target embedded watermark information from the target core module.

[0139] After the target core module is obtained, the target embedded watermark information is extracted from the target core module, which facilitates the subsequent property rights verification of the target core module.

[0140] S508: Obtain a watermark detection sequence from the target embedded watermark information.

[0141] The target embedded watermark information includes both an input detection sequence and an output sequence. After the target embedded watermark information is extracted, the watermark detection sequence is obtained from the target embedded watermark information, that is, the input detection sequence is obtained.

[0142] S509: Input the watermark detection sequence into the state machine corresponding to the core module to be protected to obtain an output watermark sequence.

[0143] After the watermark detection sequence is obtained, the watermark detection sequence is input into the state machine corresponding to the core module to be protected to obtain an output watermark sequence.

[0144] S510: Obtain initial watermark information from a watermark management agency.

[0145] After obtaining the output watermark sequence, the initial watermark information is obtained from the watermark management agency.

[0146] S511: Determine a sequence to be compared according to a preset watermark mapping method, a watermark detection sequence and an output watermark sequence.

[0147] After the output watermark sequence is obtained, the sequence to be compared is determined according to the watermark detection sequence and the output watermark sequence according to the preset watermark mapping mode. When the preset watermark mapping mode is the output direct mapping mode, the output watermark sequence is determined as the sequence to be compared; when the preset watermark mapping mode is the input-output mapping mode, the sequence obtained by concatenating the watermark detection sequence and the output watermark sequence is determined as the sequence to be compared.

[0148] S512: Compare the sequence to be compared with the initial watermark information to obtain a comparison result.

[0149] After the sequence to be compared is determined, the sequence to be compared is compared with the initial watermark information, that is, the sequence to be compared is compared with the initial watermark information for consistency to obtain a comparison result.

[0150] S513: Determine the watermark detection result according to the comparison result.

[0151] After the comparison result is obtained, the watermark detection result is determined according to the comparison result. That is, by comparing the sequence to be compared with the initial watermark information for consistency, when it is determined that the sequence to be compared is consistent with the initial watermark information, it means that the property rights verification of the target core module has passed, and when it is determined that the sequence to be compared is inconsistent with the initial watermark information, it means that the property rights verification of the target core module has failed, and then the ownership is determined according to the watermark detection result.

[0152] In a specific implementation of the present invention, performing watermark sequence mapping on a finite state machine corresponding to a core module to be protected according to the initial watermark information in a preset watermark mapping manner may include the following steps:

[0153] Step 1: adjusting the finite state machine corresponding to the core module to be protected by expanding the number of output bits, expanding the number of input bits, and adding at least one of the states to obtain an adjusted finite state machine;

[0154] Step 2: Map the watermark sequence to the adjusted finite state machine according to the initial watermark information and the preset watermark mapping method.

[0155] For the convenience of description, the above two steps can be combined for explanation.

[0156] When the finite state machine corresponding to the core module to be protected is mapped to a watermark sequence, the finite state machine corresponding to the core module to be protected is adjusted by expanding the number of output bits, expanding the number of input bits, and adding at least one of the states to obtain an adjusted finite state machine, and the adjusted finite state machine is mapped to a watermark sequence according to the preset watermark mapping method based on the initial watermark information. By adjusting the finite state machine corresponding to the core module to be protected by expanding the number of output bits, expanding the number of input bits, and adding at least one of the states, the adjusted finite state machine has enough free input and output information of the required watermark size to be embedded.

[0157] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, which may include the following steps:

[0158] The finite state machine corresponding to the core module to be protected is adjusted by extending the number of output bits, extending the number of input bits and adding states.

[0159] When mapping the watermark sequence to the finite state machine corresponding to the core module to be protected, the finite state machine corresponding to the core module to be protected is adjusted by expanding the number of output bits, expanding the number of input bits, and adding states. The finite state machine is adjusted by expanding the number of output bits, expanding the number of input bits, and adding states, so that it is convenient to use the adjusted state machine to embed watermark information into the core module to be protected.

[0160] See also Figure 6 , Figure 6 FIG. 1 is a schematic diagram of an embedding example of the first sequential finite state machine under the output direct mapping mode in an embodiment of the present invention. Figure 6 It is the original finite state machine, including three states from S0 to S2, and the input and output are one bit wide. Since all combinations of all inputs are considered in all states (there is a single input), Figure 6 is a fully specified state machine.

[0161] See also Figure 7 , Figure 7 Schematic diagram of an embedding example of a second sequential finite state machine in an output direct mapping mode in an embodiment of the present invention. Figure 7 It is a method to add a 0010 sequence watermark to the finite state machine. Figure 7A new state S3 is added to add watermarks. Since the original finite state machine is fully specified, access to this state must be achieved through the addition of new inputs. The value of the free input needs to be set in order to generate the required watermark sequence. The start of the watermark can be selected from any state. For example, if the S0 state is selected as the starting point of the watermark and a new input is added, 0 is added before all original inputs and outputs. There are two free inputs 10 and 11 in states S0~S2. In the new state S3, there are four free inputs to choose from 00, 01, 10 and 11. The free input 10 of the S0 state and the free input 10 of the S3 state are selected to generate watermarks, and the outputs are 00 and 10 respectively. That is, when 10 is input, the first state jump is made from S0 to S3, and the output value is 00. When 10 is input again, the second state jump is made from S3 to S0, and the output value is 10. Therefore, when in the S0 state, when the sequence 10 and 10 are sequentially input to the finite state machine, the required output sequence 00 and 10 will be generated, realizing the signature sequence of 0010.

[0162] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, which may include the following steps:

[0163] The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits and adding states.

[0164] When mapping the watermark sequence to the finite state machine corresponding to the core module to be protected, the finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits and adding states. By only adjusting the finite state machine by expanding the number of input bits and adding states, the efficiency of watermark information generation is improved.

[0165] See also Figure 8 , Figure 8 Schematic diagram of an embedding example of a third sequential finite state machine in an output direct mapping mode in an embodiment of the present invention. Figure 8 is Figure 6 Another way to implement the 0010 signature sequence. Figure 8 Only one state and one input are added without adding any new outputs. The generated signature sequence is Figure 7The method is the same but more efficient. For example, starting from the S0 state, when the input is 10, the finite state machine jumps from S0 to S3 and outputs 0. Then, in the S3 state, the input 10 jumps to S1 and outputs 0. Then, in the S1 state, the input 10 jumps to S0 and outputs 1. Finally, in the S0 state, the input 11 jumps back to S1 and outputs 0. Therefore, in the S0 state, when the sequence 10, 10, 10, 11 is sequentially input to the finite state machine, the required output sequence 0, 0, 1, 0 will be generated, thereby realizing the signature sequence of 0010. By inputting Figure 6 Adding a new state S3 and an input bit to the state transition diagram in , adds a total of 10 free input configurations, so there are multiple methods to choose from for generating a 4-bit signature.

[0166] In a specific implementation of the present invention, the finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, which may include the following steps:

[0167] The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits.

[0168] When the finite state machine corresponding to the core module to be protected is mapped to the watermark sequence, the finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits. When there is an input that has been used in the original finite state machine, but the output is different, the finite state machine corresponding to the core module to be protected can be adjusted by expanding the number of input bits, so that the watermark information can be embedded in the core module to be protected using the adjusted state machine.

[0169] See also Fig. 9 , Fig. 9 Schematic diagram of the embedding example of the first sequential finite state machine under the input-output mapping mode in the embodiment of the present invention. Assume that the watermark sequence to be embedded (i.e., the original watermark sequence) is {0011 0110 1001 1100}, Fig. 9 This is the original design before any watermark jumps are added. When checking state S0, it is found that input 00 is not used, so a new jump is added and the next state is randomly selected.

[0170] See also Fig.10 , Fig.10 This is a schematic diagram of an embedding example of the second sequential finite state machine in the input-output mapping mode in the embodiment of the present invention. For example, if the next state selected by input 00 from state S0 is S1, and input 01 in state S1 is not used, a new jump is added to randomly select the next state.

[0171] See also Fig.11 , Fig.11This is a schematic diagram of an embedding example of the third sequential finite state machine in the input-output mapping mode in the embodiment of the present invention. For example, if the next state selected from state S0 input 01 is S2, the original state machine output can be reused, and the signature sequence in state S2 completely overlaps with the existing jump pair 10 / 01, so this jump can be used to enter the next state S3.

[0172] See also Fig.12 , Fig.12 This is a schematic diagram of an embedding example of the fourth sequential finite state machine under the input-output mapping method in an embodiment of the present invention. After jumping into the next state S3, the input 11 in S3 has been used, and the output is inconsistent with the output required to generate the watermark, so an extra input bit is added to the entire design, 1X / 10 is changed to 1X0 / 10, and the new jump is 111 / 00, and the next state is randomly determined. Fig.12 Set to S0. After increasing the input bits, the original watermark sequence becomes {00111 01110 10X01 11100}. Fig.12 Only the complete input bits and output bits after adding extra input bits when jumping from S3 state to S4 state and from S3 state to S0 state are given. Other jumps will also have corresponding increase in input bits. Fig.12 Not shown one by one.

[0173] In a specific implementation of the present invention, performing watermark sequence mapping on a finite state machine corresponding to a core module to be protected according to the initial watermark information in a preset watermark mapping manner may include the following steps:

[0174] According to the initial watermark information, the finite state machine corresponding to the core module to be protected is mapped into a watermark sequence in an output direct mapping manner.

[0175] When watermark sequence mapping is performed on the state machine corresponding to the core module to be protected according to the initial watermark information, the watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected according to the output direct mapping method according to the initial watermark information. The watermark sequence mapping is performed by output direct mapping method, which is simple and low-cost.

[0176] Figure 6 , Figure 7 , Figure 8 The process of mapping the watermark sequence to the finite state machine corresponding to the core module to be protected in accordance with the output direct mapping method is shown.

[0177] In a specific implementation of the present invention, watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner, including:

[0178] According to the initial watermark information, the watermark sequence is mapped to the finite state machine corresponding to the core module to be protected in an input-output mapping manner.

[0179] When the watermark sequence mapping is performed on the state machine corresponding to the core module to be protected according to the initial watermark information, the watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected according to the input-output mapping method according to the initial watermark information. The watermark sequence mapping is performed by the input-output mapping method, which increases the mapping flexibility and can well find overlapping jumps, thereby reducing the overhead.

[0180] Fig. 9 , Fig.10 , Fig.11 , Fig.12 The process of watermark sequence mapping for the finite state machine corresponding to the core module to be protected according to the input-output mapping method is shown.

[0181] In a specific implementation of the present invention, performing watermark sequence mapping on a finite state machine corresponding to a core module to be protected in an input-output mapping manner according to the initial watermark information may include the following steps:

[0182] Step 1: Randomly select the state of the finite state machine corresponding to the core module to be protected to obtain the first state;

[0183] Step 2: Get the original input bit number of the finite state machine;

[0184] Step 3: Determine a first output bit group corresponding to the first state according to the initial watermark information;

[0185] Step 4: Determine the first input bit group of the original input bit number according to the initial watermark information;

[0186] Step 5: Determine whether the first input bit group is unused in the first state, if so, execute step 6, if not, execute step 7;

[0187] Step 6: randomly select the jump state of the first state in the finite state machine to obtain the second state, so as to complete the mapping of the current first output bit group to the watermark sequence of the finite state machine; determine the current second state as the new first state, and return to execute step 3 until the watermark sequence mapping is determined to be completed according to the initial watermark information;

[0188] Step 7: Obtain the second input bit group of each associated jump state of the first state in the finite state machine;

[0189] Step 8: Determine whether there is a second input bit group that is consistent with the first output bit group in each second input bit group, if yes, execute step 9, if no, execute step 11;

[0190] Step nine: mapping the current first output bit group to a watermark sequence of the finite state machine through the associated jump state corresponding to the first state, the first input bit group, the first output bit group, and the second input bit group consistent with the first output bit group;

[0191] Step 10: determining the associated jump state corresponding to the second input bit group consistent with the first output bit group as the new first state, and returning to execute step 3 until the watermark sequence mapping is determined to be completed according to the initial watermark information;

[0192] Step 11: Expand the finite state machine by adding input bits, obtain a new first input bit group obtained by expanding the first input bit group, and return to execute step 6.

[0193] For the convenience of description, the above eleven steps can be combined for explanation.

[0194] When the finite state machine corresponding to the core module to be protected is mapped to a watermark sequence according to the input-output mapping method based on the initial watermark information, the state of the finite state machine corresponding to the core module to be protected is randomly selected to obtain the first state, and the original input bit number of the finite state machine is obtained, such as Fig. 9 As shown, the original input bit number of the finite state machine is two, and the first output bit group corresponding to the first state is determined according to the initial watermark information. For example, according to {00110110 1001 1100}, the first output bit group corresponding to the first state is determined to be 11. The first input bit group of the original input bit number is determined according to the initial watermark information. For example, according to {0011 0110 1001 1100}, the first input bit group of the original input bit number is determined to be 00. It is determined whether the first input bit group is not used in the first state, that is, it is determined whether 00 is not used in the S0 state. When it is determined that the first input bit group is not used in the first state, the jump state of the first state in the finite state machine is randomly selected to obtain the second state, as shown in FIG. Fig.10 As shown, the currently selected second state is S1, so as to complete the mapping of the current first output bit group to the watermark sequence of the finite state machine, that is, the mapping of the watermark sequence of 11 to the finite state machine is completed. The current second state is determined as the new first state, and based on the newly determined first state, the first output bit group corresponding to the first state is determined according to the initial watermark information, until the watermark sequence mapping is completed according to the initial watermark information.

[0195] When it is determined that the first input bit group has been used in the first state, the second input bit group of each associated jump state of the first state in the finite state machine is obtained, such as Fig.11As shown, the current first input bit group is 10, and the current first state is S2, which shows that 10 has been used. It is determined whether there is a second input bit group consistent with the first output bit group in each second input bit group. When it is determined that there is a second input bit group consistent with the first output bit group in each second input bit group, the current first output bit group is mapped to the finite state machine through the first state, the first input bit group, the first output bit group, and the associated jump state corresponding to the second input bit group consistent with the first output bit group. The associated jump state corresponding to the second input bit group consistent with the first output bit group is determined as the new first state, and the first output bit group corresponding to the new first state is determined according to the initial watermark information until the watermark sequence mapping is completed according to the initial watermark information.

[0196] When it is determined that there is no second input bit group consistent with the first output bit group in each second input bit group, the finite state machine is expanded by adding input bits to obtain a new first input bit group obtained by expanding the first input bit group, and the jump state of the first state in the finite state machine is randomly selected to obtain the second state, thereby completing the mapping of the current first output bit group to the watermark sequence of the finite state machine. The watermark sequence mapping is performed by input-output mapping, which increases the mapping flexibility.

[0197] In a specific implementation of the present invention, the finite state machine is expanded by adding input bits, which may include the following steps:

[0198] The finite state machine is extended by assigning a first logic value to an input bit of an existing jump in the finite state machine, and assigning a second logic value to an input bit of a watermark jump to be added in the finite state machine.

[0199] When the finite state machine is extended by adding input bits, the finite state machine is extended by assigning a first logic value to the input bits of the existing jumps in the finite state machine, and assigning a second logic value to the input bits of the watermark jump to be added in the finite state machine. For example, it can be set to assign a logic value of 0 to all existing jumps, and assign a logic value of 1 to the watermark jump to be added. The finite state machine is extended by assigning different logic values ​​to the input bits of the existing jumps in the finite state machine and the watermark jump to be added, thereby avoiding the overlap of the expanded input bit groups corresponding to the same state.

[0200] Corresponding to the above method embodiment, the present invention further provides a chip watermark protection device. The chip watermark protection device described below and the chip watermark protection method described above can be referenced to each other.

[0201] See also Fig.13 , Fig.13 This is a structural block diagram of a chip watermark protection device in an embodiment of the present invention. The device may include:

[0202] The identification information acquisition unit 11 is used to acquire the target identification information of the core module to be protected in the chip;

[0203] The identification information submitting unit 12 is used to submit the target identification information to the watermark management agency;

[0204] The initial watermark information receiving unit 13 is used to receive the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information;

[0205] The target embedded watermark information obtaining unit 14 is used to perform watermark sequence mapping on the state machine corresponding to the core module to be protected according to the initial watermark information in accordance with a preset watermark mapping method to obtain the target embedded watermark information;

[0206] The watermark protection unit 15 is used to perform watermark protection on the core module to be protected by using the target embedded watermark information.

[0207] It can be seen from the above technical solution that by processing the target identification information of the core module to be protected to obtain the initial watermark information and storing it in the watermark management agency, the watermark management agency is used to manage the legal watermark database, and the authority of the watermark management agency is fully utilized. By encrypting and hashing the target identification information, the embedding overhead can be reduced while ensuring the watermark capacity. By combining the initial watermark information and the characteristics of the state machine corresponding to the core module to be protected, the state machine corresponding to the core module to be protected is mapped to a watermark sequence according to a preset watermark mapping method to obtain the target embedded watermark information, and the target embedded watermark information is embedded in a suitable state without affecting the normal function of the core module to be protected. The implementation method of chip watermark protection is simple, which greatly reduces the chip protection cost.

[0208] In a specific implementation of the present invention, the initial watermark information receiving unit 13 is specifically a unit for receiving the initial watermark information returned after the watermark management agency adds a timestamp to the target identification information and performs encryption and hash processing.

[0209] In a specific implementation of the present invention, the initial watermark information receiving unit 13 is specifically a unit for receiving the initial watermark information of a preset bit length returned by the watermark management agency after encrypting and hashing the target identification information.

[0210] In a specific implementation of the present invention, the initial watermark information receiving unit 13 is specifically a unit for receiving the initial watermark information returned after the watermark management agency encrypts and hashes the target identification information and encodes it using the Huffman compression coding algorithm.

[0211] In a specific implementation of the present invention, the initial watermark information receiving unit 13 is specifically a unit for receiving the initial watermark information returned by the watermark management agency after the watermark management agency encrypts, hashes and performs error correction coding on the target identification information.

[0212] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 is specifically a unit that performs watermark sequence mapping on the finite state machine corresponding to the core module to be protected according to the initial watermark information and a preset watermark mapping method.

[0213] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 includes:

[0214] A state machine adjustment subunit, used to adjust the finite state machine corresponding to the core module to be protected by at least one of expanding the number of output bits, expanding the number of input bits, and adding states, to obtain an adjusted finite state machine;

[0215] The first watermark sequence mapping subunit is used to perform watermark sequence mapping on the adjusted finite state machine according to the initial watermark information and a preset watermark mapping method.

[0216] In a specific implementation of the present invention, the state machine adjustment subunit is specifically a unit that adjusts the finite state machine corresponding to the core module to be protected by expanding the number of output bits, expanding the number of input bits and adding states.

[0217] In a specific implementation of the present invention, the state machine adjustment subunit is specifically a unit that adjusts the finite state machine corresponding to the core module to be protected by expanding the number of input bits and adding states.

[0218] In a specific implementation of the present invention, the state machine adjustment subunit is specifically a unit that adjusts the finite state machine corresponding to the core module to be protected by expanding the number of input bits.

[0219] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 is specifically a unit that performs watermark sequence mapping on the finite state machine corresponding to the core module to be protected in an output direct mapping manner according to the initial watermark information.

[0220] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 is specifically a unit that performs watermark sequence mapping on the finite state machine corresponding to the core module to be protected in an input-output mapping manner according to the initial watermark information.

[0221] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 includes:

[0222] A state selection subunit, used for randomly selecting a state of a finite state machine corresponding to the core module to be protected to obtain a first state;

[0223] A bit number acquisition subunit, used for acquiring the original input bit number of the finite state machine;

[0224] A first output bit group determining subunit, configured to determine a first output bit group corresponding to a first state according to the initial watermark information;

[0225] A first input bit group generating subunit, used for determining a first input bit group of original input bit numbers according to the initial watermark information;

[0226] A first judging subunit, used for judging whether the first input bit group is unused in the first state;

[0227] A jump state selection subunit, for randomly selecting a jump state of the first state in the finite state machine to obtain a second state when it is determined that the first input bit group is not used in the first state, so as to complete mapping the current first output bit group to the watermark sequence of the finite state machine;

[0228] The first repetitive execution subunit is used to determine the current second state as a new first state, and repeatedly execute the step of determining the first output bit group corresponding to the first state according to the initial watermark information until the watermark sequence mapping is completed according to the initial watermark information.

[0229] In a specific implementation of the present invention, the target embedded watermark information obtaining unit 14 may further include:

[0230] A second input bit group acquisition submodule, for acquiring second input bit groups of each associated jump state of the first state in the finite state machine when it is determined that the first input bit group has been used in the first state;

[0231] A second judging subunit is used to judge whether there is a second input bit group consistent with the first output bit group in each second input bit group;

[0232] a second watermark sequence mapping subunit, configured to, when determining that there is a second input bit group consistent with the first output bit group among the second input bit groups, map the current first output bit group to the finite state machine through an associated jump state corresponding to the first state, the first input bit group, the first output bit group, and the second input bit group consistent with the first output bit group;

[0233] The first repetitive execution subunit is used to determine the associated jump state corresponding to the second input bit group consistent with the first output bit group as a new first state, and repeatedly execute the step of determining the first output bit group corresponding to the first state according to the initial watermark information until the watermark sequence mapping is completed according to the initial watermark information.

[0234] In a specific embodiment of the present invention, the device may further include:

[0235] A state machine extension unit, configured to extend the finite state machine by adding input bits when it is determined that there is no second input bit group consistent with the first output bit group in each second input bit group;

[0236] The repetitive execution unit is used to obtain a new first input bit group obtained by expanding the first input bit group, and repeatedly execute the step of randomly selecting a jump state of the first state in the finite state machine.

[0237] In a specific embodiment of the present invention, the state machine expansion unit is specifically a unit that expands the finite state machine by assigning a first logic value to an input bit of an existing jump in the finite state machine, and assigning a second logic value to an input bit of a watermark jump to be added in the finite state machine.

[0238] In a specific embodiment of the present invention, the device may further include:

[0239] A target core module acquisition unit is used to, after watermark protection is performed on the core module to be protected using the target embedded watermark information, when a watermark extraction request is received, acquire the target core module after the watermark protection is completed on the core module to be protected;

[0240] The target embedded watermark information extraction unit is used to extract the target embedded watermark information from the target core module.

[0241] In a specific embodiment of the present invention, the device may further include:

[0242] A watermark detection sequence acquisition unit, used to acquire a watermark detection sequence from the target embedded watermark information after extracting the target embedded watermark information from the target core module;

[0243] An output watermark sequence obtaining unit is used to input the watermark detection sequence into the state machine corresponding to the core module to be protected to obtain an output watermark sequence;

[0244] An initial watermark information acquisition unit, used to acquire initial watermark information from a watermark management agency;

[0245] A to-be-compared sequence determination unit, configured to determine a to-be-compared sequence according to a preset watermark mapping method based on a watermark detection sequence and an output watermark sequence;

[0246] A comparison result obtaining unit, used for comparing the sequence to be compared with the initial watermark information to obtain a comparison result;

[0247] The watermark detection result determination unit is used to determine the watermark detection result according to the comparison result.

[0248] Corresponding to the above method embodiment, see Fig.14 , Fig.14 This is a schematic diagram of a chip watermark protection device provided by the present invention, and the device may include:

[0249] A memory 332, for storing computer programs;

[0250] The processor 322 is used to implement the steps of the chip watermark protection method of the above method embodiment when executing the computer program.

[0251] For details, please refer to Fig.15 , Fig.15 A schematic diagram of the specific structure of a chip watermark protection device provided in this embodiment, which may have relatively large differences due to different configurations or performances, may include a processor (central processing units, CPU) 322 (for example, one or more processors) and a memory 332, and the memory 332 stores one or more computer programs 342 or data 344. Among them, the memory 332 may be a temporary storage or a permanent storage. The program stored in the memory 332 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the data processing device. Furthermore, the processor 322 may be configured to communicate with the memory 332, and execute a series of instruction operations in the memory 332 on the chip watermark protection device 301.

[0252] The chip watermark protection 301 may further include one or more power supplies 326 , one or more wired or wireless network interfaces 350 , one or more input and output interfaces 358 , and / or one or more operating systems 341 .

[0253] The steps in the chip watermark protection method described above can be implemented by the structure of the chip watermark protection device.

[0254] Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0255] Obtain target identification information of a core module to be protected in the chip; submit the target identification information to a watermark management agency; receive initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information; perform watermark sequence mapping on the state machine corresponding to the core module to be protected according to a preset watermark mapping method based on the initial watermark information to obtain target embedded watermark information; and perform watermark protection on the core module to be protected using the target embedded watermark information.

[0256] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0257] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0258] Corresponding to the above method embodiments, the present invention further provides a computer program product, including a computer program, which implements the steps of the above chip watermark protection method when executed by a processor.

[0259] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the devices, equipment and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0260] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A chip watermark protection method, characterized in that: include: Obtain target identification information of the core module to be protected in the chip; Submitting the target identification information to a watermark management agency; Receiving initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information; The finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding a state to obtain an adjusted finite state machine; According to the initial watermark information, the adjusted finite state machine is mapped into a watermark sequence in accordance with a preset watermark mapping method to obtain target embedded watermark information; Using the target embedded watermark information to perform watermark protection on the core module to be protected; The finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding a state, including: The finite state machine corresponding to the core module to be protected is adjusted by extending the number of output bits, extending the number of input bits and adding states; wherein the finite state machine is a fully specified state machine; When a watermark extraction request is received, a target core module is obtained after watermark protection is performed on the core module to be protected; Extracting the target embedded watermark information from the target core module; Acquire a watermark detection sequence from the target embedded watermark information; Input the watermark detection sequence into the state machine corresponding to the core module to be protected to obtain an output watermark sequence; Obtaining the initial watermark information from the watermark management agency; Determining a sequence to be compared according to the preset watermark mapping mode and the watermark detection sequence and the output watermark sequence; wherein, when the preset watermark mapping mode is an output direct mapping mode, the output watermark sequence is determined as the sequence to be compared; and when the preset watermark mapping mode is an input-output mapping mode, a sequence obtained by concatenating the watermark detection sequence and the output watermark sequence is determined as the sequence to be compared; Comparing the sequence to be compared with the initial watermark information to obtain a comparison result; Determine a watermark detection result according to the comparison result; Determine the ownership of the property according to the watermark detection result; when it is determined that the sequence to be compared is consistent with the initial watermark information, it is determined that the property verification of the target core module has passed; when it is determined that the sequence to be compared is inconsistent with the initial watermark information, it is determined that the property verification of the target core module has failed; The watermark sequence mapping is performed on the finite state machine corresponding to the core module to be protected according to the initial watermark information in a preset watermark mapping manner, including: Randomly selecting a state of a finite state machine corresponding to the core module to be protected to obtain a first state; Obtaining the number of original input bits of the finite state machine; Determine a first output bit group corresponding to the first state according to the initial watermark information; Determine a first input bit group of the original input bit number according to the initial watermark information; determining whether the first input bit group is unused in the first state; If yes, randomly select the jump state of the first state in the finite state machine to obtain the second state, so as to complete the mapping of the current first output bit group to the watermark sequence of the finite state machine; Determine the current second state as a new first state, and repeat the step of determining a first output bit group corresponding to the first state according to the initial watermark information, until the watermark sequence mapping is completed according to the initial watermark information; When it is determined that the first input bit group has been used in the first state, obtaining a second input bit group of each associated jump state of the first state in the finite state machine; Determine whether there is a second input bit group consistent with the first output bit group in each second input bit group; If yes, mapping the current first output bit group to the finite state machine through the associated jump state corresponding to the first state, the first input bit group, the first output bit group, and the second input bit group consistent with the first output bit group, performing a watermark sequence mapping; The associated jump state corresponding to the second input bit group consistent with the first output bit group is determined as a new first state, and the step of determining the first output bit group corresponding to the first state according to the initial watermark information is repeated until the watermark sequence mapping is completed according to the initial watermark information.

2. The chip watermark protection method according to claim 1, characterized in that: Receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information, including: The initial watermark information returned by the watermark management agency after the watermark management agency adds a timestamp to the target identification information and performs encryption and hash processing is received.

3. The chip watermark protection method according to claim 1, characterized in that: Receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information, including: Receive initial watermark information of a preset bit length returned by the watermark management agency after encrypting and hashing the target identification information.

4. The chip watermark protection method according to claim 1, characterized in that: Receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information, including: The initial watermark information returned by the watermark management agency after the target identification information is encrypted, hashed and encoded using a Huffman compression coding algorithm is received.

5. The chip watermark protection method according to claim 1, characterized in that: Receiving the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information, including: Receive the initial watermark information returned by the watermark management agency after encrypting, hashing and error-correcting the target identification information.

6. The chip watermark protection method according to claim 1, characterized in that: The finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding a state, including: The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits and adding states.

7. The chip watermark protection method according to claim 1, characterized in that: The finite state machine corresponding to the core module to be protected is adjusted by at least one of expanding the number of output bits, expanding the number of input bits, and adding a state, including: The finite state machine corresponding to the core module to be protected is adjusted by expanding the number of input bits.

8. The chip watermark protection method according to claim 1, characterized in that: When it is determined that there is no second input bit group consistent with the first output bit group in the second input bit groups, the method further includes: Expanding the finite state machine by adding input bits; A new first input bit group obtained by expanding the first input bit group is obtained, and the step of randomly selecting a jump state of the first state in the finite state machine is repeatedly performed.

9. The chip watermark protection method according to claim 8, characterized in that: The finite state machine is extended by adding input bits, including: The finite state machine is extended by assigning a first logic value to an input bit of an existing jump in the finite state machine and assigning a second logic value to an input bit of a watermark jump to be added in the finite state machine.

10. A chip watermark protection device, characterized in that: include: An identification information acquisition unit, used to acquire target identification information of a core module to be protected in the chip; An identification information submitting unit, used to submit the target identification information to a watermark management agency; An initial watermark information receiving unit, used to receive the initial watermark information returned by the watermark management agency after encrypting and hashing the target identification information; The target embedded watermark information obtaining unit is used for the target embedded watermark information obtaining unit to include: The state machine adjustment subunit is used to adjust the finite state machine corresponding to the core module to be protected by at least one of the following methods: expanding the number of output bits, expanding the number of input bits, and adding states, to obtain an adjusted finite state machine; adjusting the finite state machine corresponding to the core module to be protected by at least one of the following methods: adjusting the finite state machine corresponding to the core module to be protected by expanding the number of output bits, expanding the number of input bits, and adding states; wherein the finite state machine is a fully specified state machine A first watermark sequence mapping subunit is used to perform watermark sequence mapping on the adjusted finite state machine according to the initial watermark information in accordance with a preset watermark mapping method to obtain target embedded watermark information; A watermark protection unit, used for performing watermark protection on the core module to be protected by using the target embedded watermark information; A target core module acquisition unit is used to, after watermark protection is performed on the core module to be protected using the target embedded watermark information, when a watermark extraction request is received, acquire the target core module after the watermark protection is completed on the core module to be protected; A target embedded watermark information extraction unit is used to extract the target embedded watermark information from the target core module; A watermark detection sequence acquisition unit, used to acquire a watermark detection sequence from the target embedded watermark information after extracting the target embedded watermark information from the target core module; An output watermark sequence obtaining unit is used to input the watermark detection sequence into the state machine corresponding to the core module to be protected to obtain an output watermark sequence; An initial watermark information acquisition unit, used to acquire initial watermark information from a watermark management agency; A to-be-compared sequence determination unit is used to determine the to-be-compared sequence according to the watermark detection sequence and the output watermark sequence according to the preset watermark mapping mode; wherein, when the preset watermark mapping mode is the output direct mapping mode, the output watermark sequence is determined as the to-be-compared sequence; and when the preset watermark mapping mode is the input-output mapping mode, the sequence obtained by concatenating the watermark detection sequence and the output watermark sequence is determined as the to-be-compared sequence; A comparison result obtaining unit, used for comparing the sequence to be compared with the initial watermark information to obtain a comparison result; The watermark detection result determination unit is used to determine the watermark detection result according to the comparison result; determine the ownership according to the watermark detection result; wherein, when it is determined that the sequence to be compared is consistent with the initial watermark information, it is determined that the target core module ownership verification has passed; when it is determined that the sequence to be compared is inconsistent with the initial watermark information, it is determined that the target core module ownership verification has failed; Wherein, the target embedded watermark information obtaining unit includes: A state selection subunit, used for randomly selecting a state of a finite state machine corresponding to the core module to be protected to obtain a first state; A bit number acquisition subunit, used for acquiring the original input bit number of the finite state machine; A first output bit group determining subunit, configured to determine a first output bit group corresponding to a first state according to the initial watermark information; A first input bit group generating subunit, used for determining a first input bit group of original input bit numbers according to the initial watermark information; A first judging subunit, used for judging whether the first input bit group is unused in the first state; A jump state selection subunit, for randomly selecting a jump state of the first state in the finite state machine to obtain a second state when it is determined that the first input bit group is not used in the first state, so as to complete mapping the current first output bit group to the watermark sequence of the finite state machine; a first repetitive execution subunit, configured to determine the current second state as a new first state, and repeatedly execute the step of determining a first output bit group corresponding to the first state according to the initial watermark information, until the watermark sequence mapping is completed according to the initial watermark information; A second input bit group acquisition submodule, for acquiring second input bit groups of each associated jump state of the first state in the finite state machine when it is determined that the first input bit group has been used in the first state; A second judging subunit is used to judge whether there is a second input bit group consistent with the first output bit group in each second input bit group; a second watermark sequence mapping subunit, configured to, when determining that there is a second input bit group consistent with the first output bit group among the second input bit groups, map the current first output bit group to the finite state machine through an associated jump state corresponding to the first state, the first input bit group, the first output bit group, and the second input bit group consistent with the first output bit group; The first repetitive execution subunit is used to determine the associated jump state corresponding to the second input bit group consistent with the first output bit group as a new first state, and repeatedly execute the step of determining the first output bit group corresponding to the first state according to the initial watermark information until the watermark sequence mapping is completed according to the initial watermark information.

11. A chip watermark protection device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the chip watermark protection method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip watermark protection method according to any one of claims 1 to 9 are implemented.

13. A computer program product, characterized in that It comprises a computer program, which, when executed by a processor, implements the steps of the chip watermark protection method as claimed in any one of claims 1 to 9.

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