A kind of reverse polarity light emitting diode and preparation method thereof

Abstract

The present invention discloses a reverse polarity light emitting diode and a preparation method thereof. The light emitting diode comprises a substrate, a bonding layer, a mirror reflection layer, a p-type semiconductor layer, a multi-quantum well layer and an n-type semiconductor layer, and also comprises a MESA hole penetrating the mirror reflection layer, the p-type semiconductor layer and the multi-quantum well layer; and also comprises a p-electrode and an n-electrode arranged in the MESA hole. In the reverse polarity light emitting diode of the present invention, the n-electrode can be made on one side of the p-type semiconductor layer, and the n-ohmic contact is omitted, so that the light emitting surface has no light shielding and light absorption layer, thereby effectively improving the bottleneck problem of product brightness and current expansion under high current of red light reverse polarity products, and at the same time, the product ESD capability and product heat dissipation can also be improved.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diodes, and in particular to a reverse polarity light emitting diode and a preparation method thereof. Background Art

[0002] Conventional structure reverse polarity RS LED chips for red light indoor and outdoor display are currently facing current expansion and brightness bottlenecks, and the application end has higher and higher requirements for product brightness; at the same time, RS chips can be used in automotive lighting products, which have high requirements for RS chip heat dissipation, high current resistance, ESD and brightness. Therefore, how to improve the brightness and current expansion of red light indoor and outdoor reverse polarity RS chip products is very important for the future development of red light gallium arsenide series vertical structure LED chips in the market application.

[0003] The structure of the existing red light reverse polarity RS chip is as follows Figure 1 As shown, the main solution is to make an electrode on one side of the n-type semiconductor layer to achieve better current expansion, but the electrode itself has certain shading problems, which affects the brightness of the product. At the same time, the light-emitting diode of this solution includes an ohmic contact layer, which has a strong light absorption effect and will also affect the luminous brightness of the product. Summary of the invention

[0004] The present invention provides a reverse polarity light emitting diode and a preparation method thereof, which are used to solve the technical problem that the brightness of existing light emitting devices is difficult to meet the existing market demand.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0006] A reverse polarity light emitting diode comprises a substrate, a bonding layer, a mirror reflection layer, a p-type semiconductor layer, a multi-quantum well layer and an n-type semiconductor layer which are sequentially stacked from bottom to top;

[0007] It also includes a MESA hole opened inside the reverse polarity light emitting diode, wherein the MESA hole continuously penetrates the mirror reflection layer, the p-type semiconductor layer and the multi-quantum well layer, and one end of the MESA hole is connected to the surface of the n-type semiconductor layer, and the other end is connected to the bonding layer;

[0008] It also includes a p-electrode and an n-electrode. The n-electrode is arranged in the MESA hole, and one end is connected to the surface of the n-type semiconductor layer and the other end is connected to the surface of the bonding layer; the p-electrode is connected to the surface of the p-type semiconductor layer.

[0009] The design idea of ​​the above technical solution is that, by improving the structure of the light-emitting diode, the present application designs a MESA hole that penetrates part of the structural layer inside the light-emitting diode, and accommodates the n-electrode through the MESA hole. The n-electrode directly forms an ohmic contact with the N-type AlGaInP layer through the MESA hole, thereby realizing the technical concept of making the n-electrode in the p-type semiconductor layer, avoiding the blocking of the light-emitting surface by the n-electrode, thereby improving the luminous brightness of the light-emitting device; at the same time, due to the design of the MESA hole, the lateral current expansion capability and current expansion uniformity of the chip are increased, so the ESD capability of the product is improved; at the same time, because the p and n electrodes are both on one side, the heat is dissipated through the metal bonding layer and the Si substrate, so the heat dissipation capacity of the chip is also improved.

[0010] As a further preferred embodiment of the above technical solution, the mirror reflection layer is arranged on the surface of the p-type semiconductor layer and the surface of the MESA hole; the mirror reflection layer includes a coating reflection layer and a dielectric layer stacked from bottom to top; the coating reflection layer is an Au / AuZn / Au layer; and a conductive hole is opened in the dielectric layer.

[0011] As a further preferred embodiment of the above technical solution, a PV protection layer is provided between the bonding layer and the mirror reflection layer, and the PV protection layer does not cover the surface of the MESA hole.

[0012] As a further preferred embodiment of the above technical solution, the bonding layer includes Ti, Pt and Au film layers arranged in sequence from bottom to top.

[0013] As a further preferred embodiment of the above technical solution, a MESA2 pattern is provided on the surface of the n-type semiconductor layer.

[0014] Based on the same technical concept, the present invention also provides a method for preparing the reverse polarity light emitting diode described in the above technical solution, comprising the following steps:

[0015] (1) A buffer layer, an etching stop layer, an n-ohmic contact layer, an n-type semiconductor layer, a multi-quantum well layer and a p-type semiconductor layer are sequentially grown on a GaAs substrate;

[0016] (2) Photolithography is performed on the surface of the p-type semiconductor layer to obtain a MESA1 pattern area, the MESA1 pattern area is etched to the n-type semiconductor layer and the surface of the n-type semiconductor layer is exposed to obtain a MESA hole, and then a mirror reflection layer and a PV insulation layer are sequentially formed on one side of the p-type semiconductor layer; and a photolithography process is used on the surface of the PV insulation layer to define an n-electrode pattern area in the MESA hole, and the n-electrode pattern area is plated and annealed to obtain an n-electrode;

[0017] (3) forming an Au film layer on the n-electrode side, and sequentially forming a Ti / Pt / Au film layer on the substrate side, laminating and bonding the Au film layer and the Ti / Pt / Au film layer, and removing the GaAs substrate, the growth buffer layer, the etching stop layer and the n-ohmic contact layer, and exposing the n-type semiconductor layer;

[0018] (4) photolithography is performed on the surface of the n-type semiconductor layer to obtain a MESA2 pattern area, etching the portion outside the MESA2 pattern area to obtain a MESA2 pattern, and roughening the surface of the n-type semiconductor layer to obtain an intermediate product;

[0019] (5) The intermediate product is subjected to photolithography to obtain a p-electrode pattern, and then oxygen plasma is used for gluing, and then the n-type semiconductor layer, the multi-quantum well layer and the p-type semiconductor layer are corroded to obtain a p-electrode coating area; coating and annealing are performed on the p-electrode coating area to obtain the p-electrode, thereby completing the preparation of the reverse polarity light-emitting diode.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The reverse polarity light emitting diode optoelectronic device of the present invention opens MESA holes in the p-type semiconductor layer and the multi-quantum well layer, so that the n-electrode can be manufactured on one side of the p-type semiconductor layer, and the GaAs light absorbing layer of the n-ohmic contact can be omitted, so that the light emitting surface has no light shielding and light absorbing layer, thereby effectively improving the bottleneck problem of product brightness and current expansion under high current of the red light reverse polarity product, and at the same time, the product ESD capability and product heat dissipation can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a schematic diagram of the structure of a reverse polarity light emitting diode in the prior art.

[0024] Figure 2 It is a schematic structural diagram of the reverse polarity light emitting diode of Example 1.

[0025] Legend:

[0026] S01, PV passivation layer; S02, n-electrode; S03, n-electrode ohmic contact layer; S04, n-type semiconductor layer; S05, multi-quantum well layer; S06, p-type semiconductor layer; S07, dielectric layer; S08, coating reflective layer; S09, p-face bonding layer; S10, substrate bonding layer; S11, substrate; S12, back gold layer; 1, n-electrode; 2, PV passivation layer; 3, n-type semiconductor layer; 4, multi-quantum well layer; 5, p-type semiconductor layer; 6, p-electrode; 7, dielectric layer; 8, coating reflective layer; 9, PV insulation layer; 10, p-face bonding layer; 11, substrate bonding layer; 12, substrate; 13, back gold layer; 14, MESA hole; 15, MESA2 pattern. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively and meticulously below in conjunction with the accompanying drawings and preferred embodiments of the present invention, but the protection scope of the present invention is not limited to the following specific embodiments.

[0028] Unless otherwise defined, all professional terms used below have the same meanings as those generally understood by those skilled in the art. The professional terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the scope of protection of the present invention.

[0029] Unless otherwise specified, various raw materials, reagents, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0030] The reverse polarity light emitting diode of this embodiment has a structural schematic diagram as shown in FIG. Figure 2 As shown, it includes a back gold layer 13, a substrate 12 (silicon wafer), a bonding layer (including a p-side bonding layer 10 and a substrate bonding layer 11), a mirror reflection layer (including a dielectric layer 7 and a coating reflection layer 8, wherein the dielectric layer 7 can be selected from SiO2, Al2O3, SiO2 / TiO2 stacked layers, etc., and the SiO2 layer is selected in this embodiment), a p-type semiconductor layer 5, a multi-quantum well layer 4, an n-type semiconductor layer 3 (with a MESA2 pattern 15 on the surface) and a PV passivation layer 2 (Si3N4, Al2O3, SiO2, etc. can be selected, and Si3N4 is selected in this embodiment).

[0031] Among them, a trapezoidal MESA hole 14 is opened inside the reverse polarity light-emitting diode, and the MESA hole 14 continuously penetrates the mirror reflection layer, the p-type semiconductor layer 5 and the multi-quantum well layer 4, and one end is connected to the surface of the n-type semiconductor layer 3, and the other end is connected to the bonding layer; the n-electrode 1 includes an Au / AuGe layer (Au / AuGeNi / Au, Au / AuGeNi / Au / Pt / Au, Ni / Au / AuGe layer, etc. can also be selected) from bottom to top, with a thickness of 0.1~0.3μm (0.2μm is selected in this embodiment), which is arranged in the MESA hole 14, and one end is connected to the surface of the n-type semiconductor layer 3, and the other end is connected to the surface of the bonding layer; the p-electrode 6 includes a Ti / Au layer (Au layer, Ni / Au layer, Ti / Pt / Au layer, Cr / Au layer, etc. can also be selected) from bottom to top, with a thickness of 1~4μm (3μm is selected in this embodiment), and is connected to the surface of the p-type semiconductor layer 5. The mirror reflection layer is arranged on the surface of the p-type semiconductor layer 5 and the surface of the MESA hole 14; the mirror reflection layer includes a coating reflection layer 8 (optionally Au / AuZn / Au, Au / AuBe / Au, ITO, etc., Au / AuZn / Au layer is selected in this embodiment) and a dielectric layer 7 (optionally SiO2, Al2O3, SiO2 / TiO2 stacking, etc., SiO2 layer is selected in this embodiment) stacked from bottom to top, with thicknesses of 0.3~0.5μm and 0.1~0.5μm (a combination of 0.4μm and 0.3μm is selected in this embodiment), and a conductive hole is opened in the dielectric layer 7. A PV insulation layer 9 is arranged between the bonding layer and the mirror reflection layer, and the PV insulation layer 9 is made of SiO2 (Al2O3 can also be selected). 3） , with a thickness of 0.5~1μm (0.7μm is selected in this embodiment), and the PV insulation layer 9 does not cover the surface of the MESA hole 14. The bonding layer includes a p-side bonding layer 10 and a substrate bonding layer 11. The p-side bonding layer 10 includes an Au layer with a thickness of 0.3~1μm (0.6μm is selected in this embodiment). The substrate bonding layer 11 includes Ti, Pt and Au film layers arranged from bottom to top, with a thickness of 0.3~1μm (0.6μm is selected in this embodiment). The back gold layer 13 is a Ti / Au film layer (Au, NiAu, Ti / Pt / Au, Ti / Ni / Au, etc. can also be selected), and the film layer thickness is 0.1~0.5μm (0.3μm is selected in this embodiment).

[0032] The method for preparing the reverse polarity light emitting diode of this embodiment comprises the following steps:

[0033] (1) A GaAs buffer layer, a GaInP etching stop layer, an n-ohmic contact layer (GaAs), an n-type semiconductor layer 3 (AlGaInP extension layer), an AlGaInP / GaInP multi-quantum well layer 4 and a p-type semiconductor layer 5 (GaP layer, doped with manganese) are sequentially grown on a GaAs substrate using a metal organic vapor chemical deposition method (MOCVD). After the above growth is completed, the surface is cleaned using a mixture of hydrogen peroxide, ammonia and water, and a mixture of sulfuric acid, hydrogen peroxide and water;

[0034] (2) A positive photoresist is used to photolithograph the surface of the p-type semiconductor layer 5 to obtain a MESA1 pattern, and then an ICP plasma etcher is used to perform plasma etching on the MESA1 pattern area, etching from the p-type semiconductor layer 5 to the n-type semiconductor layer 3, and exposing the surface of the n-type semiconductor layer 3 to form a MESA hole 14; then a photoresist stripping solution is used to remove the photoresist in the pattern area.

[0035] (3) A dielectric layer 7 is deposited on one side of the surface of the p-type semiconductor layer 5 by using a PECVD method; after deposition, the epitaxial wafer is annealed in an annealing furnace at a temperature of 400-500° C. (450° C. is selected in this embodiment) and for a time of 10-20 min (15 min is selected in this embodiment).

[0036] (4) Conductive holes are photolithographically formed on the dielectric layer 7 using a positive photoresist, and then plasma is applied after the photolithography. Then, the conductive hole photolithographic pattern is etched using a BOE solution (NH4F:HF=7:1) to obtain conductive holes on the dielectric layer 7, and then the photoresist is removed using a degumming solution;

[0037] (5) A Au / AuZn / Au coating reflective layer 8 is coated on the dielectric layer 7 using a vacuum coating machine, and then annealed in an annealing furnace at a temperature of 460 to 500° C. (480° C. is selected in this embodiment) for 10 to 20 minutes (15 minutes is selected in this embodiment) to form a mirror reflective layer that can conduct electricity through the conductive holes;

[0038] (6) A PV insulating layer 9 is deposited on the surface of the mirror reflection layer by using PECVD; a PV2 pattern area is obtained by photolithography using a positive photoresist on the surface of the PV insulating layer 9, and an oxygen plasma is used for gluing. Then, a BOE solution (NH4F:HF=7:1) or an ICP plasma etching method is used to etch the PV2 pattern area to remove the PV insulating layer 9 in the MESA hole 14, and then a photoresist remover is used to remove the photoresist in the PV2 pattern area.

[0039] (7) A negative photoresist is used to photolithograph the surface of the PV insulating layer 9 in the MESA hole 14 to obtain an n-electrode pattern, and then an oxygen plasma is used for coating. A vacuum coating machine is used to coat an Au / AuGe film layer on the n-electrode pattern chip with the photoresist. After coating, a blue film is used to peel off and remove the glue to obtain an n-electrode 1, and then an annealing furnace is used to anneal the n-electrode 1 at an annealing temperature of 290-310°C (300°C is selected in this embodiment) to form an ohmic contact between the n-electrode 1 and the n-type semiconductor layer 3.

[0040] (8) Continue to use a vacuum coating machine to coat an Au film layer on one side of the surface of the n-electrode 1 to obtain a p-side bonding layer 10, and use a vacuum coating machine to coat a Ti / Pt / Au film on the surface of the substrate 12 to obtain a substrate bonding layer 11; bond the p-side bonding layer 10 and the substrate bonding layer 11 together, and use a wafer bonding machine to perform high-temperature and high-pressure bonding, wherein the bonding temperature is 300-400°C (350°C is selected in this embodiment), and the bonding pressure is 5000-15000kg (10000kg is selected in this embodiment).

[0041] (9) Use a mixture of ammonia and hydrogen peroxide to clean and remove the GaAs substrate and GaAs buffer layer; then use hydrochloric acid solution to clean and remove the GaInP etching stop layer to expose the GaAs ohmic contact layer; then use a mixture of phosphoric acid, hydrogen peroxide and water to remove the GaAs ohmic contact layer to expose the n-type semiconductor layer 3.

[0042] (10) A positive photoresist is used to photolithographically obtain a MESA2 pattern area on the surface of the n-type semiconductor layer 3, and then an ICP plasma etcher is used to plasma-etch the non-pattern area, and then a photoresist stripping solution is used to remove the photoresist in the MESA2 pattern area to obtain a MESA2 pattern 15;

[0043] (11) The chip surface patterned by MESA2 is subjected to photolithography using a positive photoresist to obtain a roughened pattern, the n-type semiconductor layer 3 is roughened using a roughening liquid, and after roughening, the photoresist in the pattern area is removed using a photoresist removal liquid;

[0044] (12) On the roughened chip, a negative photoresist is used for photolithography to obtain a p-electrode pattern area, and then oxygen plasma is used for coating. Then, a BOE solution (NH4F:HF=7:1) is used to etch the n-type semiconductor layer 3, the multi-quantum well layer 4 and the p-type semiconductor layer 5 in the p-electrode pattern area to obtain a p-electrode coating area; a Ti / Au layer is coated on the p-electrode coating area with the photoresist using a vacuum coating machine, and after coating, a blue film is used for stripping and de-coating to obtain a p-electrode 6;

[0045] (13) After the p-electrode 6 is completed, a PV passivation layer 2 is deposited on the chip surface using PECVD, and then a positive photoresist is used for photolithography to obtain the PV1 pattern area, and oxygen plasma is used for gluing, and then a BOE solution (NH4F:HF=7:1) is used to etch the PV1 pattern area to remove the PV passivation layer 2 on the electrode surface. After etching, a photoresist stripping solution is used to remove the photoresist in the pattern area;

[0046] (14) grinding and thinning the substrate 12 with a grinder to 100-150 μm (130 μm is selected in this embodiment); cleaning the thinned substrate 12 with an organic solution, and then coating a Ti / Au film on the surface of the substrate with a vacuum coating machine, and then annealing the back gold with an annealing furnace at a temperature of 150-250° C. (200° C. is selected in this embodiment) to obtain a back gold layer 13;

[0047] (15) Use a laser scriber to perform laser scribe on the front side with a scribe depth of 30 to 50 μm. After the front side scribe is completed, use a tester to test the optoelectronic parameters. After the chip is tested, use a laser scriber to perform laser scribe on the back side with a scribe depth of 20 to 70 μm. After the back side is scribe, use a splitter to split the chip into single chips. Thus, the reverse polarity light emitting diode of this embodiment is obtained.

[0048] Performance tests were conducted on the reverse polarity light emitting diode of this embodiment and the existing commercially available light emitting diode mentioned in the background art. The results are shown in Table 1.

[0049] Table 1. Comparison of performance parameters of Example 1 and existing products

[0050]

[0051] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above embodiments. For those skilled in the art, improvements and changes obtained without departing from the technical concept of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A reverse polarity light emitting diode, characterized in that: It comprises a substrate (12), a bonding layer, a mirror reflection layer, a p-type semiconductor layer (5), a multi-quantum well layer (4) and an n-type semiconductor layer (3) which are stacked in sequence from bottom to top; It also includes a MESA hole (14) opened inside the reverse polarity light-emitting diode, the MESA hole (14) continuously penetrating the mirror reflection layer, the p-type semiconductor layer (5) and the multi-quantum well layer (4), and one end of the MESA hole is connected to the surface of the n-type semiconductor layer (3), and the other end is connected to the bonding layer; the cross-section of the MESA hole is trapezoidal, and the length of the upper bottom surface of the trapezoid is less than the length of the lower bottom surface; It also comprises a p-electrode (6) and an n-electrode (1), wherein the n-electrode (1) is arranged in the MESA hole (14) and has one end connected to the surface of the n-type semiconductor layer (3) and one end connected to the surface of the bonding layer; and the p-electrode (6) is connected to the surface of the p-type semiconductor layer (5).

2. The reverse polarity light emitting diode according to claim 1, characterized in that: The mirror reflection layer is arranged on the surface of the p-type semiconductor layer (5) and the surface of the MESA hole (14); the mirror reflection layer comprises a coating reflection layer (8) and a dielectric layer (7) which are stacked from bottom to top; the coating reflection layer (8) is an Au / AuZn / Au layer; and a conductive hole is opened in the dielectric layer (7).

3. The reverse polarity light emitting diode according to claim 1, characterized in that: A PV insulation layer (9) is provided between the bonding layer and the mirror reflection layer, and the PV insulation layer (9) does not cover the surface of the MESA hole (14).

4. The reverse polarity light emitting diode according to any one of claims 1 to 3, characterized in that: The bonding layer includes Ti, Pt and Au film layers arranged in sequence from bottom to top.

5. The reverse polarity light emitting diode according to any one of claims 1 to 3, characterized in that: The A MESA2 pattern (15) is provided on the surface of the semiconductor layer.

6. A method for preparing a reverse polarity light emitting diode according to any one of claims 1 to 5, characterized in that: The following steps are involved: (1) sequentially growing a buffer layer, an etching stop layer, an n-ohmic contact layer, an n-type semiconductor layer (3), a multi-quantum well layer (4) and a p-type semiconductor layer (5) on a GaAs substrate; (2) Photolithography is performed on the surface of the p-type semiconductor layer (5) to obtain a MESA1 pattern area, the MESA1 pattern area is etched until the n-type semiconductor layer (3) is etched and the surface of the n-type semiconductor layer (3) is exposed to obtain a MESA hole (14), and then a mirror reflection layer and a PV insulation layer (9) are sequentially formed on one side of the p-type semiconductor layer (5); and a photolithography process is used on the surface of the PV insulation layer (9) to define an n-electrode pattern area in the MESA hole (14), and the n-electrode pattern area is plated and annealed to obtain an n-electrode (1); (3) forming a p-face bonding layer (10) on one side of the n-electrode (1) and a substrate bonding layer (11) on one side of the substrate (12), laminating and bonding the p-face bonding layer (10) and the substrate bonding layer (11), removing the GaAs substrate, the growth buffer layer, the etching stop layer and the n-ohmic contact layer, and exposing the n-type semiconductor layer (3); (4) photolithography is performed on the surface of the n-type semiconductor layer (3) to obtain a MESA2 pattern area, etching the portion outside the MESA2 pattern area to obtain a MESA2 pattern (15), and roughening the surface of the n-type semiconductor layer (3) to obtain an intermediate product; (5) The intermediate product is subjected to photolithography to obtain a p-electrode pattern, and then oxygen plasma is used for gluing, and then the n-type semiconductor layer (3), the multi-quantum well layer (4) and the p-type semiconductor layer (5) are corroded to obtain a p-electrode coating area; the p-electrode coating area is subjected to coating and annealing to obtain the p-electrode (6), thereby completing the preparation of the reverse polarity light-emitting diode.

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