Chip packaging structure and chip packaging method

Abstract

The embodiment of the present application provides a chip packaging structure and a chip packaging method, wherein the chip packaging structure includes: a frame substrate; a solder pad is provided on one side surface of the frame substrate; a glass substrate is provided on one side of the frame substrate; a via hole extending in the thickness direction is provided in the glass substrate, and a conductive column is filled in the via hole; one end of the conductive column is exposed from the surface of the glass substrate and is connected to a conductive ball, and the conductive ball is connected to the corresponding solder pad on the frame substrate; a circuit element group is formed on the surface of the glass substrate away from the frame substrate; the circuit element group has a first electrode and a second electrode; the other end of the conductive column is exposed from the surface of the glass substrate and is electrically connected to the second electrode; the first electrode is connected to the corresponding solder pad of the frame substrate through a conductive wire. The embodiment of the present application arranges a conductive ball on the glass substrate and fixes it on the frame substrate by welding, which is relatively firm and can solve the problem that the copper wire on the surface of the glass substrate is easily separated from the glass substrate in the traditional solution.

Description

Technical Field

[0001] The present application relates to chip packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] Compared with traditional silicon-based chip packaging technology, the glass-based IPD (Integrated Passive Device) integration technology combines glass substrate and RF circuit design, breaking through the original silicon-based RF device concept. It can realize the development of a series of RF devices such as high-Q inductors, microstrip filters, antennas, transformers, etc. It has outstanding advantages such as excellent high-frequency electrical properties, strong mechanical stability, low cost, high performance, and easy three-dimensional integration.

[0003] However, since the surface of the glass substrate is relatively smooth and its adhesion to commonly used metals is poor, the glass substrate and the metal traces on its surface will be delaminated, causing the metal traces to curl or even fall off, thus leading to chip failure. Summary of the invention

[0004] In order to solve one of the above-mentioned technical defects, a chip packaging structure and a chip packaging method are provided in an embodiment of the present application.

[0005] According to a first aspect of an embodiment of the present application, a chip packaging structure is provided, including:

[0006] A frame substrate; a solder pad is provided on one side surface of the frame substrate;

[0007] A glass base is arranged on one side of the frame substrate; a via hole extending in the thickness direction is arranged in the glass base, and a conductive column is filled in the via hole; one end of the conductive column is exposed from the surface of the glass base and is connected to a conductive ball, and the conductive ball is connected to a corresponding pad on the frame substrate;

[0008] A circuit element group is formed on the surface of the glass substrate away from the frame substrate; the circuit element group has a first electrode and a second electrode; the other end of the conductive column is exposed from the surface of the glass substrate and is electrically connected to the second electrode; the first electrode is connected to the corresponding pad of the frame substrate through a conductive wire.

[0009] According to a second aspect of an embodiment of the present application, a chip packaging method is provided, comprising:

[0010] A via hole is opened in the glass substrate and a conductive column is formed in the via hole;

[0011] A circuit element group is formed on one side of the glass substrate, wherein a second electrode in the circuit element group is electrically connected to one end of the conductive column;

[0012] forming a conductive ball at the other end of the conductive column;

[0013] soldering the conductive balls to corresponding pads of the frame substrate;

[0014] The first electrodes of the circuit element group are connected to corresponding pads of the frame substrate through conductive wires.

[0015] The technical solution provided in the embodiment of the present application is that a via hole extending in the thickness direction is provided in the glass base, and a conductive column is filled in the via hole; one end of the conductive column is exposed from the surface of the glass base and is connected to a conductive ball, and the conductive ball is connected to the corresponding pad on the frame substrate. The conductive ball is fixed to the frame substrate by welding, which is relatively firm and can solve the problem that the copper wire on the surface of the glass base is easily separated from the glass base in the traditional solution, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0019] Figure 3 A flowchart of a chip packaging method provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a structure of forming a circuit element group on a glass substrate in a chip packaging method provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of a structure for bonding a temporary carrier board to a circuit element group in a chip packaging method provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of etching a glass-based conductive layer in the chip packaging method provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of a structure in which a conductive ball is formed at the end of a conductive pillar in a chip packaging method provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of a structure in which a temporary carrier is removed in a chip packaging method provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the structure of welding the conductive balls to the frame substrate in the chip packaging method provided in an embodiment of the present application;

[0026] Fig.10 A schematic diagram of the structure of filling insulating glue between a glass substrate and a frame substrate in the chip packaging method provided in an embodiment of the present application.

[0027] Reference numerals:

[0028] 1-Frame substrate;

[0029] 2-glass base; 21-conductive pillar; 22-conductive ball; 23-conductive layer;

[0030] 31-upper electrode plate; 32-lower electrode plate; 33-insulating layer; 34-metal wiring layer; 35-first electrode plate; 36-metal hole; 37-second electrode plate;

[0031] 4- Insulation material;

[0032] 5-Insulation glue;

[0033] 6- Conductive wire;

[0034] 7- Temporary carrier board. DETAILED DESCRIPTION

[0035] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0036] like Figure 1 and Figure 2 As shown, this embodiment provides a chip packaging structure, including: a frame substrate 1, a glass substrate 2 and a circuit element group. Among them, a plurality of pads and metal traces are provided on one side surface of the frame substrate 1. The frame substrate 1 can be a printed circuit board.

[0037] The glass base 2 is arranged on one side of the frame substrate 1 and connected to the frame substrate 1, and a circuit element group is formed on the other side of the glass base 2. A via hole extending in the thickness direction is arranged in the glass base 2, and a conductive column 21 is filled in the via hole. One end of the conductive column 21 is exposed from the surface of the glass base 2 and is connected to a conductive ball 22, and the conductive ball 22 is connected to the corresponding pad on the frame substrate 1. The conductive ball 22 can be a copper ball, a tin ball, etc., and is connected to the corresponding pad on the frame substrate 1 through a reflow soldering process.

[0038] The circuit element group is formed on the surface of the glass substrate 2 away from the frame substrate 1, and the circuit element group has a first electrode and a second electrode. The circuit element group can be a capacitor, an inductor, a diode, a triode, a field effect transistor and other components. This embodiment takes a capacitor as an example for description, and the first electrode serves as one lead-out terminal of the capacitor, and the second electrode serves as the second lead-out terminal of the capacitor.

[0039] The other end of the conductive pillar 21 is also exposed on the surface of the glass substrate 2 and electrically connected to the second electrode, and the first electrode is connected to the corresponding pad of the frame substrate 1 through the conductive wire 6. The first electrode of the circuit element group uses the conductive wire 6 to lead the electrical signal to the frame substrate 1 through the frame wire bonding process, and the second electrode leads the electrical signal to the frame substrate 1 through the conductive pillar 21 and the conductive ball 22 of the glass substrate 2.

[0040] The technical solution provided in this embodiment is that a via hole extending along the thickness direction is provided in the glass base, and a conductive column is filled in the via hole; one end of the conductive column is exposed from the surface of the glass base and is connected to a conductive ball, and the conductive ball is connected to the corresponding pad on the frame substrate. The conductive ball is fixed to the frame substrate by welding, which is relatively firm and can solve the problem that the copper wire on the surface of the glass base is easily separated from the glass base in the traditional solution, thereby improving reliability.

[0041] In the traditional silicon-based bump process, multiple solder balls are formed on the chip electrodes and connected to the frame substrate by reflow soldering. The pads of the frame substrate need to be set one-to-one according to the position of the chip electrodes, and once the chip electrodes change, the frame substrate needs to be redesigned and manufactured. Moreover, when there are many chip electrodes, the wiring design is more difficult, and if the wiring is dense, there is a possibility of signal interference.

[0042] In the present application, a circuit element group is provided on the other side of the glass substrate, the second electrode of the circuit element group is connected to the other end of the conductive column, and the first electrode of the circuit element group is connected to the corresponding pad of the frame substrate through a conductive wire. The position of the pad connected to the first electrode can be flexibly adjusted and is not limited to the corresponding position of the chip, thereby reducing the difficulty of design and wiring, and improving the problem of signal interference, thereby improving the accuracy and reliability of the device. Moreover, the inductance and radio frequency effect can be adjusted by adjusting the wire density, height, and shape, which has high flexibility.

[0043] In addition, the process of forming via holes on the glass substrate 2 is relatively simple and low in cost. Moreover, as an insulating material, the dielectric constant of glass is only about 1 / 3 of that of silicon material, and the loss factor is 2-3 orders of magnitude lower than that of silicon material, which greatly reduces the substrate loss and parasitic effects, thereby ensuring the integrity of the transmission signal and meeting the application under microwave and radio frequency conditions.

[0044] In the above scheme, a via hole is first formed on the glass substrate 2, and then a conductive column 21 is formed in the via hole by electroplating. The conductive column 21 can be a copper column. The conductive ball 22 can be a copper ball or a tin ball. The conductive wire 6 can be a gold wire, a copper wire or an aluminum wire.

[0045] On the basis of the above technical solution, an insulating glue 5 is filled between the glass base 2 and the frame substrate 1 to cover the ends of the conductive pillars 22 and the conductive balls 23. The insulating glue 5 further bonds the glass base 2 and the frame substrate 1 together, further improving the firmness of the connection between the two. The insulating glue 5 can be a resin glue.

[0046] For the above circuit element assembly, this embodiment provides a specific implementation method, such as Figure 2 As shown, the circuit element group includes: an upper plate 31 and a lower plate 32, an insulating layer 33 is provided between the upper plate 31 and the lower plate 32, and the upper plate 31, the lower plate 32 and the insulating layer 33 constitute a capacitor.

[0047] The lower electrode plate 32 is connected to the top of the conductive column 21 as the second electrode of the circuit element assembly.

[0048] A metal wiring layer 34 is formed on the side of the upper electrode plate 31 facing away from the lower electrode plate 32 (i.e., the upper surface of the upper electrode plate 31), and a first electrode plate 35 is formed on the metal wiring layer 34. The metal wiring layer 34 is electrically connected to the upper first electrode plate 35 and the lower upper electrode plate 31 through conductive metals. Specifically, one formation method is: growing insulating material 4 layer by layer on the upper surface of the glass substrate 2, punching holes when growing to a preset thickness, forming the lower electrode plate 32, and then continuing to grow insulating material 4, and then forming insulating layer 33, upper electrode plate 31, metal hole 36, metal wiring layer 34, metal hole 36, and first electrode plate 35 in sequence. Finally, a window is opened on the upper surface of the first electrode plate 35 to expose the first electrode plate 35 for subsequent wiring. The first electrode plate 35 is connected to the frame substrate 1 as a first electrode through a conductive wire 6. The insulating material 4 can be polyimide.

[0049] In the above scheme, the signal of the upper plate 31 in the circuit element group is led out from the top through the conductive wire, and the signal of the lower plate 32 is led out from the bottom through the conductive column.

[0050] This embodiment also provides another implementation method, such as Figure 1 As shown, in Figure 2On the basis of the circuit element group, the circuit element group also includes: a second electrode plate 37, which is arranged side by side with the first electrode plate 35. The second electrode plate 37 is electrically connected to the lower electrode plate 32, and the second electrode plate 37 is connected to the corresponding pad of the frame substrate 1 through the conductive wire 6. The signal equivalent to the lower electrode plate 32 is led out from the lower conductive column on the one hand, and from the upper conductive wire on the other hand. This solution can be set according to the needs of the chip circuit, which can meet the requirements of leading out signals from the top and the bottom, and has high flexibility.

[0051] A metal wiring layer 34 is further provided below the second electrode plate 37 , and is connected to the lower electrode plate 32 via the metal wiring layer 34 .

[0052] Specifically, in the process of forming the circuit element group, the insulating material 4 is grown layer by layer on the upper surface of the glass substrate 2, and then the insulating layer 33, the upper electrode plate 31, the metal hole 36, the metal wiring layer 34, the metal hole 36, the first electrode plate 35, and the second electrode plate 37 are formed in sequence. Finally, a window is opened on the upper surface of the first electrode plate 35 to expose the first electrode plate 35, and a window is opened on the upper surface of the second electrode plate 37 to expose the second electrode plate 37, which is convenient for subsequent wiring. The first electrode plate 35 is connected to the frame substrate 1 through the conductive wire 6 as the first electrode, and the second electrode plate 35 is connected to the frame substrate 1 through the conductive wire 6.

[0053] On the basis of the above technical solution, this embodiment also provides a chip packaging method, such as Figure 3 As shown, the method includes:

[0054] Step 101: Open a via hole in a glass substrate and form a conductive column in the via hole.

[0055] like Figure 4 As shown, a via hole is formed by etching on the glass substrate 2, and a conductive column 21 is formed in the via hole by an electroplating process.

[0056] Step 102: forming a circuit element group on one side of the glass substrate, wherein a second electrode in the circuit element group is electrically connected to one end of the conductive column.

[0057] A circuit element group is formed on one side surface of the glass substrate 2 , and the circuit element group includes a first electrode and a second electrode, wherein the second electrode is electrically connected to one end of the conductive column 21 .

[0058] In the above steps, while the conductive pillars 21 are formed, a conductive layer 23 is also formed on the surface of the glass substrate 2. Then, the conductive layer 23 needs to be exposed, developed, and etched, leaving the area corresponding to the position of the conductive pillars 21 and removing the rest of the conductive layer. Figure 6 shown.

[0059] Furthermore, before etching the conductive layer 23, the circuit element group is bonded to the temporary carrier 7 on the side away from the glass substrate 2, such as Figure 5 The temporary carrier 7 is used to protect the exposed first electrode plate 35 and the second electrode plate 37 to avoid the influence of the subsequent process. The temporary carrier 7 can be made of glass, organic plastic, silicon base, etc.

[0060] Step 103 is performed after the conductive layer 23 is etched.

[0061] Step 103: forming a conductive ball at the other end of the conductive column.

[0062] A conductive ball 22 is formed at the bottom end of the conductive pillar 21. Figure 7 The conductive ball 22 is formed by a plating reflow process and can be a metal tin ball.

[0063] Then, the temporary carrier 7 is removed by a debonding process, such as Figure 8 shown.

[0064] Step 104 : soldering the conductive balls to corresponding solder pads of the frame substrate.

[0065] like Fig. 9 As shown, the conductive balls 22 are soldered to the corresponding pads of the frame substrate 1 by a reflow process.

[0066] Furthermore, an insulating glue 5 is filled between the glass base 2 and the frame substrate 1, so that the insulating glue 5 covers the end of the conductive column 21 and the conductive ball 22, so that the glass base 2 and the frame substrate 1 are tightly combined. Fig.10 shown.

[0067] Step 105 : Connect the first electrodes of the circuit element group to corresponding pads of the frame substrate through conductive wires.

[0068] like Figure 1 or Figure 2 As shown, a wire bonding step is performed to lead out a signal, and the first electrode of the circuit element group is connected to the corresponding pad of the frame substrate 1 through the conductive wire 6. Figure 1 , and the second electrode plate of the circuit element group is also connected to the corresponding pad of the frame substrate 1 through the conductive wire 6.

[0069] In the above steps, forming a circuit element group on one side of the glass substrate 2 includes: forming a lower electrode plate 32 on one side of the glass substrate 2, and the lower electrode plate 32 is electrically connected to the conductive column 21 as a second electrode. Then, an insulating layer 33, an upper electrode plate 31 and a first electrode plate 35 are sequentially formed on the lower electrode plate 32, and the upper electrode plate 31 is electrically connected to the first electrode plate 35 through a metal hole, and the first electrode plate 35 is used as a first electrode.

[0070] Another solution is to form a second electrode plate 37 while forming the first electrode plate 35. The second electrode plate 37 is electrically connected to the lower electrode 32. In step 105, the second electrode plate 37 is also connected to the corresponding pad of the frame substrate 1 through the conductive wire 6.

[0071] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0073] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0074] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0075] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip packaging method, characterized in that: include: A via hole is opened in the glass substrate and a conductive column is formed in the via hole; A circuit element group is formed on one side of the glass substrate, wherein a second electrode in the circuit element group is electrically connected to one end of the conductive column; Bonding the circuit component group to a temporary carrier on a side facing away from the glass substrate; forming a conductive ball at the other end of the conductive column; Remove the temporary carrier plate; soldering the conductive balls to corresponding pads of the frame substrate; connecting the first electrodes of the circuit element group to corresponding pads of the frame substrate through conductive wires; Insulating glue is filled between the glass base and the frame substrate so that the insulating glue covers the ends of the conductive pillars and the conductive balls, so as to bond the glass base and the frame substrate.

2. The chip packaging method according to claim 1, characterized in that: forming a conductive pillar in the via hole, including: Forming a conductive column in the via hole of the glass substrate through an electroplating process, and forming a conductive layer on the surface of the glass substrate; Before forming a conductive ball at the other end of the conductive column, the method further comprises: The conductive layer is etched to leave the area corresponding to the position of the conductive column and remove the rest of the conductive layer.

3. The chip packaging method according to claim 1, characterized in that: The circuit element group formed on one side of the glass substrate includes: A lower electrode plate is formed on one side of the glass substrate, and the lower electrode plate is electrically connected to the conductive column as a second electrode; An insulating layer, an upper electrode plate and a first electrode plate are sequentially formed on the lower electrode plate. The upper electrode plate is electrically connected to the first electrode plate, and the first electrode plate serves as a first electrode.

4. The chip packaging method according to claim 3, characterized in that: While forming the first electrode plate, a second electrode plate is also formed, and the second electrode plate is electrically connected to the lower electrode; Afterwards, the method further includes: connecting the second electrode plate to the corresponding pad of the frame substrate through a conductive wire.

5. A chip packaging structure manufactured by the method according to any one of claims 1 to 4, characterized in that: include: A frame substrate; a solder pad is provided on one side surface of the frame substrate; A glass base is arranged on one side of the frame substrate; a via hole extending in the thickness direction is arranged in the glass base, and a conductive column is filled in the via hole; one end of the conductive column is exposed from the surface of the glass base and is connected to a conductive ball, and the conductive ball is connected to a corresponding pad on the frame substrate; A circuit element group is formed on the surface of the glass substrate away from the frame substrate; the circuit element group has a first electrode and a second electrode; the other end of the conductive column is exposed from the surface of the glass substrate and is electrically connected to the second electrode; the first electrode is connected to a corresponding pad of the frame substrate through a conductive wire; The insulating glue is filled between the glass base and the frame substrate, covers the end of the conductive column and the conductive ball, and is used to bond the glass base and the frame substrate.

6. The chip packaging structure according to claim 5, characterized in that: The circuit element group comprises: an upper electrode plate and a lower electrode plate, an insulating layer is provided between the upper electrode plate and the lower electrode plate; the lower electrode plate serves as a second electrode; A first electrode plate is formed on one side of the upper electrode plate away from the lower electrode plate; the first electrode plate is electrically connected to the upper electrode plate and serves as a first electrode.

7. The chip packaging structure according to claim 6, characterized in that: The circuit element group also includes: The second electrode plate is arranged side by side with the first electrode plate; the second electrode plate is electrically connected to the lower electrode plate, and the second electrode plate is connected to the corresponding pad of the frame substrate through a conductive wire.

8. The chip packaging structure according to any one of claims 5 to 7, characterized in that: The conductive pillars are copper pillars, and the conductive balls are tin balls.

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