Junction field effect transistor controlled RC-IGBT device and preparation method thereof

Abstract

The present invention provides a junction field effect transistor controlled RC-IGBT device and a preparation method thereof, wherein the device comprises: a metal collector, a collector region, an N-type drift region, a P-well, an N-type carrier blocking layer, a P-type base region, an N-type emitter region and a metal emitter stacked in sequence; a main control gate structure extending from the P-type base region to the N-type drift region; an emitter gate structure extending from the P-type base region to the N-type drift region; a secondary control gate structure, comprising a gate dielectric layer and a P-type JFET gate electrode extending from the P-type base region to the N-type carrier blocking layer; an N-type channel region, arranged between two adjacent P-type JFET gate electrodes, and an N-type channel region connecting the N-type carrier blocking layer and the metal emitter. The present invention effectively reduces hole injection during diode operation by introducing a junction field effect transistor (JFET) in a diode to optimize diode performance while maintaining IGBT characteristics, without causing any reduction in IGBT characteristics.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a junction field effect transistor controlled RC-IGBT device and a preparation method thereof. Background Art

[0002] The IGBT device structure was proposed in the early 1980s. After more than 30 years of development, its performance and reliability have been greatly improved, and its application range has been greatly expanded. It is currently widely used in switching frequencies below 30kHz and is one of the mainstream fully controlled power semiconductor devices. In the past 10 years, IGBT devices have mainly developed towards higher cell density, larger wafer size, thinner chip thickness and higher operating junction temperature. At present, the performance has approached its theoretical limit. An important subsequent development trend of IGBT devices is to develop towards multi-functional integration, such as: integrating current and temperature sensors inside the chip to improve the current utilization of a single chip and improve the timeliness of protection, etc., integrating IGBT and freewheeling diodes on-chip to further reduce the cost of power devices and increase power density. The latter is the reverse-conducting IGBT. The concept of the BL-RC-IGBT (Super Body Layer-RC-IGBT) structure is to introduce a hole storage layer (shallow N layer) to accumulate a large number of hole carriers in the drift region during the on-state. Compared with the traditional RC-IGBT structure, this method inserts a hole storage layer inside the P-body region. This structure has the effect of accumulating hole carriers from the collector side. In addition, it will enhance the injection of electron carriers from the device surface. Therefore, compared with traditional RC-IGBT devices, the internal structure of SBL-RC-IGBT can accumulate more carriers (electrons and holes), and the trade-off relationship of Von-Eoff is further optimized.

[0003] RC-IGBT has a smaller overall size than using separate IGBT and diode chips. To reduce the loss of RC-IGBT, the loss of both IGBT and diode components should be minimized. However, the methods to reduce the loss in each component are not always compatible. For example, in IGBT, carrier accumulation reduces the on-resistance. The n-barrier layer in the super body layer (SBL) structure acts as a barrier to holes, resulting in carrier accumulation. However, in the diode, the increased carrier accumulation leads to higher reverse recovery charge and switching losses. Therefore, a lifetime suppressor is usually introduced to achieve a balance between the diode forward voltage and switching losses. However, this lifetime control technology increases the on-resistance of the IGBT. Therefore, it is a challenging task to control the diode performance while maintaining the characteristics of the IGBT.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a junction field effect transistor controlled RC-IGBT device and a preparation method thereof, so as to solve the problem in the prior art that it is difficult to balance and improve the performance of IGBT and diode.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a junction field effect transistor controlled RC-IGBT device, the RC-IGBT device comprising: a metal collector; a collector region, comprising a P-type collector region and an N-type collector region arranged in parallel on the metal collector; an N-type drift region, located on the collector region; a P-well, located on the N-type drift region; an N-type carrier blocking layer, located on the P-well; a P-type base region, located on the N-type carrier blocking layer; an N-type emitter region, arranged in the P-type base region; a metal emitter, arranged on the P-type base region and connected to the N-type emitter region; a main control gate structure, comprising a first gate dielectric layer and a first gate electrode, wherein the main control gate structure extends from the P-type base region to the N-type drift region, and the N-type emitter region is arranged on the side of the main control gate structure ; an emission gate structure, comprising a second gate dielectric layer and a second gate electrode, wherein the emission gate structure extends from the P-type base region to the N-type drift region; an auxiliary control gate structure, wherein the auxiliary control gate structure comprises a gate dielectric layer and a P-type JFET gate electrode extending from the P-type base region to the N-type carrier blocking layer, wherein the gate dielectric layer exposes one side of the P-type JFET gate electrode; an N-type channel region, wherein both sides of the N-type channel region are connected to the exposed sides of two adjacent P-type JFET gate electrodes, and both ends are connected to the N-type carrier blocking layer and the metal emitter; the first gate electrode of the main control gate structure is connected to the main gate drive of the device, the second gate electrode of the emission gate structure is connected to the metal emitter of the device, and the P-type JFET gate electrode of the auxiliary control gate structure is connected to the auxiliary gate drive of the device.

[0007] Optionally, during diode operation of the junction field effect transistor controlled RC-IGBT device, a negative voltage is applied to the auxiliary control gate structure, so that the N-type channel region has a high conductivity, the N-type carrier blocking layer is short-circuited with the metal emitter through the N-type channel region, and the potential barrier of the N-type carrier blocking layer is maintained, thereby preventing forward bias at the interface between the P-type base region and the N-type carrier blocking layer, and suppressing hole injection from the P-type base region to the P-well.

[0008] Optionally, during the operation of the junction field effect transistor controlled RC-IGBT device, a positive voltage is applied to the main control gate structure so that the IGBT device operates normally, and a positive voltage is applied to the auxiliary control gate structure to generate a larger depletion region in the N-type channel region, so that the N-type channel region is in a low conductance state, and the conductive channel between the N-type carrier blocking layer and the metal emitter is pinched off, thereby keeping the threshold voltage, on-characteristics and off-characteristics of the IGBT device unchanged.

[0009] Optionally, the auxiliary control gate structure is disposed between the main control gate structure and the emission gate structure, and is disposed above the N-type collector region.

[0010] Optionally, the junction field effect transistor controlled RC-IGBT device further includes an N-type buffer layer, and the N-type buffer layer is located between the collector region and the N-type drift region.

[0011] Optionally, the main control gate structure has a depth of 5 microns to 10 microns and a width of 1 micron to 3 microns, and the emission gate structure has a depth of 5 microns to 10 microns and a width of 1 micron to 3 microns.

[0012] Optionally, the depth of the P well is 3.5 microns to 9 microns, and the doping concentration is 5×10 15 cm -3 ~2×10 18 cm -3 The depth of the N-type carrier blocking layer is 2 microns to 6 microns, and the doping concentration is 4×10 15 cm -3 ~6×10 18 cm -3 The depth of the P-type base region is 1.5 microns to 4 microns, and the doping concentration is 1×10 16 cm -3 ~4×10 17 cm -3 .

[0013] Optionally, the depth of the auxiliary control gate structure is 1.5 microns to 5.5 microns, the width is 0.5 microns to 2 microns, and the doping concentration of the P-type JFET gate electrode is 1×10 15 cm -3 ~2×10 18 cm -3 .

[0014] Optionally, the N-type channel region has a depth of 1.5 micrometers to 4 micrometers, a width of 0.5 micrometers to 2 micrometers, and a doping concentration of 1×10 15 cm -3 ~2×10 18 cm -3 .

[0015] The present invention also provides a method for preparing a junction field effect transistor controlled RC-IGBT device, the preparation method comprising the steps of: providing a substrate, the substrate comprising an N-type buffer layer, an N-type drift region, a P-well, an N-type carrier blocking layer and a P-type base region stacked in sequence; forming a main control gate structure and an emission gate structure in the substrate, the main control gate structure comprising a first gate dielectric layer and a first gate electrode, wherein the main control gate structure extends from the P-type base region to the N-type drift region, the emission gate structure comprising a second gate dielectric layer and a second gate electrode, wherein the emission gate structure extends from the P-type base region to the N-type drift region; forming a secondary control gate structure in the substrate, the secondary control gate structure comprising a third gate dielectric layer extending from the P-type base region to the N-type carrier blocking layer and a P-type JFET gate electrode, the third gate dielectric layer exposing one side of the P-type JFET gate electrode, Wherein, the auxiliary control gate structure extends from the P-type base region to the N-type carrier blocking layer; an N-type emitter region is formed in the P-type base region, and the N-type emitter region is arranged on the side of the main control gate structure; an N-type channel region is formed in the substrate, and the N-type channel region is arranged between two adjacent auxiliary control gate structures; a metal emitter is formed on the substrate, the metal emitter is connected to the N-type emitter region, and the N-type channel region connects the N-type carrier blocking layer and the metal emitter; a collector region is formed on the back side of the substrate, and the collector region includes a P-type collector region and an N-type collector region arranged in parallel; a metal collector is formed on the surface of the collector region; the first gate electrode of the main control gate structure is connected to the main gate drive of the device, the second gate electrode of the emitter gate structure is connected to the metal emitter of the device, and the P-type JFET gate electrode of the auxiliary control gate structure is connected to the auxiliary gate drive of the device.

[0016] As described above, the junction field effect transistor controlled RC-IGBT device and the preparation method thereof of the present invention have the following beneficial effects:

[0017] During the operation of the diode, the present invention applies a zero negative voltage to the auxiliary control gate structure, so that the N-type channel region has a high conductivity, the N-type carrier blocking layer is short-circuited with the metal emitter through the N-type channel region, and the potential barrier of the N-type carrier blocking layer is maintained, thereby preventing the forward bias at the interface of the P-type base region and the N-type carrier blocking layer, and inhibiting the hole injection from the P-type base region to the P-well. Due to the lower resistivity of the N-type carrier blocking layer and the N-type channel region and the lower concentration of the P-well, the hole injection efficiency is lowered, so that the accumulated hole density on the anode side of the diode is reduced, and the balance between the forward voltage and switching loss of the diode can be achieved without the introduction of the lifetime control technology.

[0018] During the operation of the IGBT device, a positive voltage is applied to the main control gate structure, so that the IGBT device works normally. A positive voltage is applied to the auxiliary control gate structure to generate a larger depletion region in the N-type channel region, so that the N-type channel region is in a low conductivity state, and the conductive channel between the N-type carrier blocking layer and the metal emitter is pinched off, so that the threshold voltage, on-characteristics and off-characteristics of the IGBT device remain unchanged.

[0019] The present invention optimizes the diode performance while maintaining the IGBT characteristics by introducing a junction field effect transistor (JFET) into the diode, thereby effectively reducing the hole injection during the operation of the diode without causing any degradation of the IGBT characteristics. The new IGBT structure of the present invention can optimize the trade-off between the reverse recovery characteristics and the conduction characteristics of the fast recovery diode without affecting the IGBT characteristics, while having lower loss and higher efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0021] Figure 1 to Figure 7 It is a schematic structural diagram showing the steps of the method for preparing a junction field effect transistor controlled RC-IGBT device according to an embodiment of the present invention, wherein: Figure 7 Shown is a schematic structural diagram of a junction field effect transistor controlled RC-IGBT device according to an embodiment of the present invention.

[0022] Component number description

[0023] 11 N-type buffer layer

[0024] 12 N-type drift region

[0025] 13 P-well

[0026] 14 N-type carrier blocking layer

[0027] 15 P-type base region

[0028] 16 N-type emitter area

[0029] 17 Main control gate structure

[0030] 171 first gate dielectric layer

[0031] 172 first gate electrode

[0032] 18 Emitting gate structure

[0033] 181 Second gate dielectric layer

[0034] 182 second gate electrode

[0035] 19. Auxiliary control gate structure

[0036] 191 Third gate dielectric layer

[0037] 192 P-type JFET gate electrode

[0038] 20 N-type channel region

[0039] 21 Metal emitter

[0040] 22 P-type collector region

[0041] 23 N-type collector region

[0042] 24 Metal Collector DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0045] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0046] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0047] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0048] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0049] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] like Figure 7As shown, this embodiment provides a junction field effect transistor controlled RC-IGBT device, the RC-IGBT device comprising: a metal collector 24; a collector region, comprising a P-type collector region 22 and an N-type collector region 23 arranged in parallel on the metal collector 24; an N-type drift region 12, located on the collector region; a P-well 13, located on the N-type drift region 12; an N-type carrier blocking layer 14, located on the P-well 13; a P-type base region 15, located on the N-type carrier blocking layer 14; an N-type emitter region 16, set The main control gate structure 17 includes a first gate dielectric layer 171 and a first gate electrode 172, wherein the main control gate structure 17 extends from the P-type base region 15 to the N-type drift region 12, and the N-type emitter region 16 is arranged on the side of the main control gate structure 17; an emitter gate structure 18 includes a second gate dielectric layer 181 and a second gate electrode 182, wherein the emitter The gate structure 18 extends from the P-type base region 15 to the N-type drift region 12; the auxiliary control gate structure 19, the auxiliary control gate structure 19 includes a third gate dielectric layer 191 and a P-type JFET gate electrode 192 extending from the P-type base region 15 to the N-type carrier blocking layer 14, the third gate dielectric layer 191 exposes one side of the P-type JFET gate electrode 192; the N-type channel region 20, the two sides of the N-type channel region 20 are connected to the exposed sides of the two adjacent P-type JFET gate electrodes 192, and the N-type channel region 20 is connected to the exposed sides of the two adjacent P-type JFET gate electrodes 192. The region 20 and the P-type JFET gate electrodes 192 on both sides thereof form a junction field effect transistor (JFET); the two ends of the N-type channel region 20 are connected to the N-type carrier blocking layer 14 and the metal emitter 21; the first gate electrode 172 of the main control gate structure 17 is connected to the main gate drive of the device, the second gate electrode 182 of the emitter gate structure 18 is connected to the metal emitter 21 of the device, and the P-type JFET gate electrode 192 of the auxiliary control gate structure 19 is connected to the auxiliary gate drive of the device.

[0051] In one embodiment, the junction field effect transistor controlled RC-IGBT device further includes an N-type buffer layer 11 , and the N-type buffer layer 11 is located between the collector region and the N-type drift region 12 .

[0052] In one embodiment, the substrate used in the junction field effect transistor controlled RC-IGBT device can be silicon, silicon germanium, germanium, silicon carbide, III-V compounds, etc. In one embodiment, the substrate is selected as silicon, that is, the main material of the collector region, N-type buffer layer 11, N-type drift region 12, P well 13, N-type carrier blocking layer 14 and P-type base region 15 is selected as silicon, and different ions (such as phosphorus, boron, etc.) can be doped into silicon and set to a suitable concentration to achieve the corresponding function.

[0053] In one embodiment, during the diode operation of the junction field effect transistor controlled RC-IGBT device, a negative voltage is applied to the P-type JFET gate electrode 192 of the auxiliary control gate structure 19, the depletion region is narrowed, the N-type channel region 20 has a high conductivity, the N-type carrier blocking layer 14 is short-circuited with the metal emitter 21 through the N-type channel region 20, and the potential barrier of the N-type carrier blocking layer 14 is maintained, thereby preventing the forward bias at the interface between the P-type base region 15 and the N-type carrier blocking layer 14, and inhibiting the hole injection from the P-type base region 15 to the P-well 13. In this embodiment, due to the lower resistivity of the N-type carrier blocking layer 14 and the N-type channel region 20 and the lower concentration of the P-well 13, the hole injection efficiency is lowered, so that the accumulated hole density on the anode side of the diode is reduced, and the balance between the forward voltage and switching loss of the diode can be achieved without the introduction of the lifetime control technology.

[0054] In one embodiment, during the operation of the junction field effect transistor controlled RC-IGBT device, a positive voltage is applied to the main control gate structure 17, so that the IGBT device operates normally, and a positive voltage is applied to the auxiliary control gate structure 19 to generate a larger depletion region, so that the N-type channel region 20 is in a low conductivity state, and the conductive channel between the N-type carrier blocking layer 14 and the metal emitter 21 is pinched off, so that the threshold voltage, on-characteristics and off-characteristics of the IGBT device remain unchanged.

[0055] In one embodiment, the auxiliary control gate structure 19 is disposed between the main control gate structure 17 and the emission gate structure 18 , and is disposed above the N-type collector region 23 .

[0056] In one embodiment, the N-type channel region 20 has a depth of 1.5 microns to 4 microns, such as 2 microns, 3 microns, etc., a width of 0.5 microns to 2 microns, such as 1 micron, 1.5 microns, etc., and a doping concentration of 1×10 15 cm -3 ~2×10 18 cm -3 , for example, 1×10 17 cm -3 , 1×10 18 cm -3 Etc., so as to control the performance of the N-type channel region 20 within a better range.

[0057] In one embodiment, the first gate dielectric layer 171, the second gate dielectric layer 181 and the third gate dielectric layer 191 may be, for example, silicon dioxide, silicon oxynitride, high-K dielectric, etc., and the first gate electrode 172, the second gate electrode 182 and the P-type JFET gate electrode 192 may be, for example, doped polysilicon, metal, etc.

[0058] In one embodiment, the main control gate structure 17 and the emitter gate structure 18 extend into the N-type drift region 12 to a depth of, for example, 1 to 3 microns, etc., to reduce the on-resistance of the IGBT device. In a specific example, the main control gate structure 17 has a depth of 5 to 10 microns and a width of 1 to 3 microns, and the emitter gate structure 18 has a depth of 5 to 10 microns and a width of 1 to 3 microns.

[0059] In one embodiment, the auxiliary control gate structure 19 can stay on the top surface of the N-type carrier blocking layer 14, or extend into the N-type carrier blocking layer 14 to a certain depth to pinch off. In a specific example, the depth of the auxiliary control gate structure 19 is 1.5 microns to 5.5 microns, such as 3 microns, 4 microns, 5 microns, etc., and the width is 0.5 microns to 2 microns, such as 1 micron, 1.5 microns, etc. The doping concentration of the P-type JFET gate electrode is 1×10 15 cm -3 ~2×10 18 cm -3 , for example, 5×10 16 cm -3 , 1×10 17 cm -3 The doping concentration of the N-type channel region can be set according to the doping concentration of the N-type channel region to effectively control the conduction and shutdown of the N-type channel region.

[0060] In one embodiment, the depth of the P-well 13 is 3.5 microns to 9 microns, for example, 5 microns, 7 microns, 8 microns, etc., and the doping concentration is 5×10 15 cm -3 ~2×10 18 cm -3 , for example, 1×10 17 cm -3 , 1×10 18 cm -3 The depth of the N-type carrier blocking layer 14 is 2 microns to 6 microns, for example, 4 microns, 5 microns, etc., and the doping concentration is 4×10 15 cm -3 ~6×10 18 cm -3 , for example, 6×10 17 cm -3, 5×10 18 cm -3 The depth of the P-type base region 15 is 1.5 microns to 4 microns, for example, 2 microns, 3 microns, 4 microns, etc., and the doping concentration is 1×10 16 cm -3 ~4×10 17 cm -3 , for example, 5×10 16 cm -3 , 1×10 17 cm -3 wait.

[0061] like Figure 1 to Figure 7 As shown, this embodiment also provides a method for preparing a junction field effect transistor controlled RC-IGBT device, the preparation method comprising the following steps:

[0062] like Figure 1 As shown, firstly, step 1) is performed to provide a substrate, wherein the substrate includes an N-type buffer layer 11, an N-type drift region 12, a P-well 13, an N-type carrier blocking layer 14 and a P-type base region 15 stacked in sequence.

[0063] In one embodiment, the material of the substrate can be silicon, silicon germanium, germanium, silicon carbide, III-V compounds, etc. The depth of the P well 13 is 3.5 microns to 9 microns, for example, 5 microns, 7 microns, 8 microns, etc., and the doping concentration is 5×10 15 cm -3 ~2×10 18 cm -3 , for example, 1×10 17 cm -3 , 1×10 18 cm -3 The depth of the N-type carrier blocking layer 14 is 2 microns to 6 microns, for example, 4 microns, 5 microns, etc., and the doping concentration is 4×10 15 cm -3 ~6×10 18 cm -3 , for example, 6×10 17 cm -3 , 5×10 18 cm -3 The depth of the P-type base region 15 is 1.5 microns to 4 microns, for example, 2 microns, 3 microns, 4 microns, etc., and the doping concentration is 1×10 16 cm -3 ~4×10 17 cm -3 , for example, 5×10 16 cm -3 , 1×10 17 cm -3wait.

[0064] like Figure 2 As shown, step 2 is then performed to form a main control gate structure 17 and an emission gate structure 18 in the substrate, the main control gate structure 17 including a first gate dielectric layer 171 and a first gate electrode 172, wherein the main control gate structure 17 extends from the P-type base region 15 to the N-type drift region 12, and the emission gate structure 18 includes a second gate dielectric layer 181 and a second gate electrode 182, wherein the emission gate structure 18 extends from the P-type base region 15 to the N-type drift region 12; an auxiliary control gate structure 19 is formed in the substrate, the auxiliary control gate structure 19 including a third gate dielectric layer 191 and a P-type JFET gate electrode 192 extending from the P-type base region 15 to the N-type carrier blocking layer 14.

[0065] In one embodiment, the first gate dielectric layer 171, the second gate dielectric layer 181 and the third gate dielectric layer 191 may be, for example, silicon dioxide, silicon oxynitride, high-K dielectric, etc., and the first gate electrode 172 and the second gate electrode 182 may be, for example, doped polysilicon, metal, etc. The P-type JFET gate electrode 192 may be, for example, P-type doped silicon, etc.

[0066] In one embodiment, the auxiliary control gate structure 19 can stay on the top surface of the N-type carrier blocking layer 14, or extend into the N-type carrier blocking layer 14 to a certain depth to pinch off. In a specific example, the depth of the auxiliary control gate structure 19 is 1.5 microns to 5.5 microns, such as 3 microns, 4 microns, 5 microns, etc., and the width is 0.5 microns to 2 microns, such as 1 micron, 1.5 microns, etc. The doping concentration of the P-type JFET gate electrode is 1×10 15 cm -3 ~2×10 18 cm -3 , for example, 5×10 16 cm -3 , 1×10 17 cm -3 The doping concentration of the N-type channel region can be set according to the doping concentration of the N-type channel region to effectively control the conduction and shutdown of the N-type channel region.

[0067] In one embodiment, the main control gate structure 17 and the emitter gate structure 18 extend into the N-type drift region 12 to a depth of, for example, 1 to 3 microns, etc., to reduce the on-resistance of the IGBT device. In a specific example, the main control gate structure 17 has a depth of 5 to 10 microns and a width of 1 to 3 microns, and the emitter gate structure 18 has a depth of 5 to 10 microns and a width of 1 to 3 microns.

[0068] In one embodiment, the auxiliary control gate structure 19 extends into the N-type carrier blocking layer 14 to a depth of, for example, 0.5 to 2 microns, so as to improve the pinch-off effect of the auxiliary control gate structure 19 on the N-type channel region 20 under negative pressure conditions. In a specific example, the auxiliary control gate structure 19 has a depth of 1.5 microns to 5.5 microns, for example, 3 microns, 4 microns, 5 microns, etc., and a width of 0.5 microns to 2 microns, for example, 1 micron, 1.5 microns, etc.

[0069] like Figure 3 As shown, step 3 is then performed to form an N-type emitter region 16 in the P-type base region 15 , and the N-type emitter region 16 is disposed on the side of the main control gate structure 17 .

[0070] like Figure 4 As shown, step 4 is then performed to form an N-type channel region 20 in the substrate. The N-type channel region 20 is disposed between two adjacent control gate structures 19 .

[0071] In one embodiment, the two sides of the N-type channel region 20 are closely connected to the auxiliary control gate structure 19, and the two ends are closely connected to the N-type carrier blocking layer 14 and the metal emitter 21, so that during the operation of the diode, the N-type channel region 20 has a high conductivity, and during the operation of the IGBT device, the N-type channel region 20 is pinched off by the auxiliary control gate structure 19, so that the threshold voltage, conduction characteristics and turn-off characteristics of the IGBT device remain unchanged. In one embodiment, the depth of the N-type channel region 20 is 1.5 microns to 4 microns, such as 2 microns, 3 microns, etc., the width is 0.5 microns to 2 microns, such as 1 micron, 1.5 microns, etc., and the doping concentration is 1×10 15 cm -3 ~2×10 18 cm -3 , for example, 1×10 17 cm -3 , 1×10 18 cm -3 Etc., so as to control the performance of the N-type channel region 20 within a better range.

[0072] like Figure 5 As shown, step 5 is then performed to form a metal emitter 21 on the substrate, wherein the metal emitter 21 is connected to the N-type emitter region 16 , and the N-type channel region 20 is connected to the N-type carrier blocking layer 14 and the metal emitter 21 .

[0073] like Figure 6 As shown, step 6 is then performed to form a collector region on the back side of the substrate, wherein the collector region includes a P-type collector region 22 and an N-type collector region 23 arranged in parallel.

[0074] like Figure 7 As shown, step 7) is finally performed to form a metal collector 24 on the surface of the collector region; wherein the first gate electrode 172 of the main control gate structure 17 is connected to the main gate drive of the device, the second gate electrode 182 of the emitter gate structure 18 is connected to the metal emitter 21 of the device, and the P-type JFET gate electrode 192 of the auxiliary control gate structure 19 is connected to the auxiliary gate drive of the device.

[0075] As described above, the junction field effect transistor controlled RC-IGBT device and the preparation method thereof of the present invention have the following beneficial effects:

[0076] During the operation of the diode, the present invention applies a zero negative voltage to the auxiliary control gate structure, so that the N-type channel region has a high conductivity, the N-type carrier blocking layer is short-circuited with the metal emitter through the N-type channel region, and the potential barrier of the N-type carrier blocking layer is maintained, thereby preventing the forward bias at the interface of the P-type base region and the N-type carrier blocking layer, and inhibiting the hole injection from the P-type base region to the P-well. Due to the lower resistivity of the N-type carrier blocking layer and the N-type channel region and the lower concentration of the P-well, the hole injection efficiency is lowered, so that the accumulated hole density on the anode side of the diode is reduced, and the balance between the forward voltage and switching loss of the diode can be achieved without the introduction of the lifetime control technology.

[0077] During the operation of the IGBT device, a positive voltage is applied to the main control gate structure, so that the IGBT device works normally. A positive voltage is applied to the auxiliary control gate structure to generate a larger depletion region in the N-type channel region, so that the N-type channel region is in a low conductivity state, and the conductive channel between the N-type carrier blocking layer and the metal emitter is pinched off, so that the threshold voltage, on-characteristics and off-characteristics of the IGBT device remain unchanged.

[0078] The present invention optimizes the diode performance while maintaining the IGBT characteristics by introducing a junction field effect transistor (JFET) into the diode, thereby effectively reducing the hole injection during the operation of the diode without causing any degradation of the IGBT characteristics. The new IGBT structure of the present invention can optimize the trade-off between the reverse recovery characteristics and the conduction characteristics of the fast recovery diode without affecting the IGBT characteristics, while having lower loss and higher efficiency.

[0079] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A junction field effect transistor controlled RC-IGBT device, characterized in that: The RC-IGBT device comprises: Metal collector; A collector region, comprising a P-type collector region and an N-type collector region arranged in parallel on the metal collector electrode; An N-type drift region, located on the collector region; A P well, located on the N-type drift region; An N-type carrier blocking layer, located on the P-well; A P-type base region, located on the N-type carrier blocking layer; An N-type emitter region is disposed in the P-type base region; A metal emitter, disposed on the P-type base region and connected to the N-type emitter region; A main control gate structure, the main control gate structure extending from the P-type base region to the N-type drift region, the N-type emitter region being disposed on a side of the main control gate structure; An emission gate structure, the emission gate structure extending from the P-type base region into the N-type drift region; A secondary control gate structure, the secondary control gate structure includes a gate dielectric layer and a P-type JFET gate electrode extending from the P-type base region to the N-type carrier blocking layer, the gate dielectric layer exposes one side of the P-type JFET gate electrode; an N-type channel region, the two sides of the N-type channel region are connected to the exposed sides of two adjacent P-type JFET gate electrodes, and the two ends are connected to the N-type carrier blocking layer and the metal emitter; The main control gate structure is connected to the main gate drive of the device, the emission gate structure is connected to the metal emitter of the device, and the auxiliary control gate structure is connected to the auxiliary gate drive of the device; The auxiliary control gate structure is disposed between the main control gate structure and the emission gate structure, and is disposed above the N-type collector region.

2. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: During diode operation of the junction field effect transistor controlled RC-IGBT device, a negative voltage is applied to the auxiliary control gate structure, so that the N-type channel region has a high conductivity, the N-type carrier blocking layer is short-circuited with the metal emitter through the N-type channel region, and the potential barrier of the N-type carrier blocking layer is maintained, thereby preventing forward bias at the interface between the P-type base region and the N-type carrier blocking layer, and suppressing hole injection from the P-type base region to the P well.

3. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: During the operation of the IGBT device of the junction field effect transistor controlled RC-IGBT device, a negative voltage is applied to the main control gate structure to enable the IGBT device to operate normally, and a positive voltage is applied to the auxiliary control gate structure to generate a larger depletion region in the N-type channel region, so that the N-type channel region is in a low conductance state, and the conductive channel between the N-type carrier blocking layer and the metal emitter is pinched off, thereby keeping the threshold voltage, on-characteristics and off-characteristics of the IGBT device unchanged.

4. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: The junction field effect transistor controlled RC-IGBT device further includes an N-type buffer layer, and the N-type buffer layer is located between the collector region and the N-type drift region.

5. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: The main control gate structure has a depth of 5 micrometers to 10 micrometers and a width of 1 micrometer to 3 micrometers, and the emission gate structure has a depth of 5 micrometers to 10 micrometers and a width of 1 micrometer to 3 micrometers.

6. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: The depth of the P well is 3.5 microns to 9 microns, and the doping concentration is 5×10 15 cm -3 ~2×10 18 cm -3 The depth of the N-type carrier blocking layer is 2 microns to 6 microns, and the doping concentration is 4×10 15 cm -3 ~6×10 18 cm -3 The depth of the P-type base region is 1.5 microns to 4 microns, and the doping concentration is 1×10 16 cm -3 ~4×10 17 cm -3 .

7. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: The depth of the auxiliary control gate structure is 1.5 microns to 5.5 microns, the width is 0.5 microns to 2 microns, and the doping concentration of the P-type JFET gate electrode is 1×10 15 cm -3 ~2×10 18 cm -3 .

8. The junction field effect transistor controlled RC-IGBT device according to claim 1, characterized in that: The N-type channel region has a depth of 1.5 microns to 4 microns, a width of 0.5 microns to 2 microns, and a doping concentration of 1×10 15 cm -3 ~2×10 18 cm -3 .

9. A method for preparing a junction field effect transistor controlled RC-IGBT device according to any one of claims 1 to 8, characterized in that: The preparation method comprises the steps of: Providing a substrate, the substrate comprising an N-type buffer layer, an N-type drift region, a P-well, an N-type carrier blocking layer and a P-type base region stacked in sequence; A main control gate structure and an emission gate structure are formed in the substrate, wherein the main control gate structure comprises a first gate dielectric layer and a first gate electrode, wherein the main control gate structure extends from the P-type base region to the N-type drift region, and wherein the emission gate structure extends from the P-type base region to the N-type drift region; forming a secondary control gate structure in the substrate, the secondary control gate structure comprising a gate dielectric layer extending from the P-type base region to the N-type carrier blocking layer and a P-type JFET gate electrode, the gate dielectric layer exposing one side of the P-type JFET gate electrode, wherein the secondary control gate structure extends from the P-type base region to the N-type carrier blocking layer; forming an N-type emitter region in the P-type base region, wherein the N-type emitter region is disposed on a side of the main control gate structure; forming an N-type channel region in the substrate, wherein the N-type channel region is disposed between two adjacent control gate structures; A metal emitter is formed on the substrate, wherein the metal emitter is connected to the N-type emitter region, and the N-type channel region is connected to the N-type carrier blocking layer and the metal emitter; forming a collector region on the back side of the substrate, wherein the collector region comprises a P-type collector region and an N-type collector region arranged in parallel; forming a metal collector on the surface of the collector region; The main control gate structure is connected to the main gate drive of the device, the emission gate structure is connected to the metal emitter of the device, and the auxiliary control gate structure is connected to the auxiliary gate drive of the device; The auxiliary control gate structure is disposed between the main control gate structure and the emission gate structure, and is disposed above the N-type collector region.

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