Filter bare chips, filters, RF circuit board components and electronic devices

Abstract

The present application provides a filter bare chip, a filter, a radio frequency circuit board assembly and an electronic device, which relates to the technical field of electronic products, can reduce the size of the filter, and is conducive to installation in a small-volume electronic device. Among them, the filter bare chip includes a first substrate, a first metal layer, a first piezoelectric layer, a second metal layer, a first cavity, a third metal layer, a second piezoelectric layer and a fourth metal layer arranged in sequence. The first metal layer includes a first electrode, the second metal layer includes a second electrode, and the overlapping part of the first electrode, the first piezoelectric layer and the second electrode forms a first transducer body. The third metal layer includes a third electrode, the fourth metal layer includes a fourth electrode, and the overlapping part of the third electrode, the second piezoelectric layer and the fourth electrode forms a second transducer body. At least part of the first transducer body, at least part of the first cavity and at least part of the second transducer body are arranged to overlap. The filter bare chip provided in the present application is used for signal selection.

Description

Technical Field

[0001] The present application relates to the technical field of electronic products, and in particular to a filter bare chip, a filter, a radio frequency circuit board assembly and an electronic device. Background Art

[0002] In electronic products, some circuits use filters to suppress useless signals and pass useful signals to achieve signal selection. For example, RF circuits use filters to select the target frequency transmission signal or the target frequency reception signal.

[0003] The size of the filter affects the space occupied by the circuit in the electronic device. The larger the size of the filter, the larger the area occupied on the circuit board, which is not conducive to installation in electronic devices with limited space. In the prior art, in order to achieve certain filtering effects, such as to achieve extremely narrow-band (bandwidth below 1M) filtering effects, the filter is usually formed by connecting multiple resonators in series and / or in parallel, resulting in a larger filter size and a larger area occupied on the circuit board, which is not conducive to installation in small-volume electronic devices such as smart watches, smart bracelets, Bluetooth headsets, and smart electronic tags. Summary of the invention

[0004] The present application provides a filter bare chip, a filter, a radio frequency circuit board assembly and an electronic device, which can reduce the size of the filter and facilitate installation in a small-volume electronic device.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a filter bare chip is provided, the filter bare chip comprising a first substrate, a first metal layer, a second metal layer, a first piezoelectric layer, a third metal layer, a fourth metal layer, a second piezoelectric layer and a first cavity. The first metal layer is arranged on the first substrate, and the first metal layer comprises a first electrode. The second metal layer is arranged on the side of the first metal layer facing away from the first substrate, and the second metal layer comprises a second electrode. At least part of the first piezoelectric layer is arranged between the first metal layer and the second metal layer, and the first electrode, the first piezoelectric layer and the second electrode overlap to form a first transducer body. The third metal layer is arranged on the side of the second metal layer facing away from the first metal layer, and the third metal layer comprises a third electrode. The fourth metal layer is arranged on the side of the third metal layer facing away from the second metal layer, and the fourth metal layer comprises a fourth electrode. At least part of the second piezoelectric layer is arranged between the third metal layer and the fourth metal layer, and the third electrode, the second piezoelectric layer and the fourth electrode overlap to form a second transducer body. The first cavity is arranged between the second metal layer and the third metal layer, and at least part of the first transducer body, at least part of the first cavity and at least part of the second transducer body overlap.

[0007] In this way, the first transducer body and the second transducer body can form two resonators, which are stacked up and down, which is conducive to reducing the occupied area of ​​the filter on the circuit board and reducing the size. In addition, the first transducer body is also used as the substrate of the second transducer body, and the second transducer body is also used as the top cover of the first transducer body. The first cavity is used as both the top reflection cavity of the first transducer body and the bottom reflection cavity of the second transducer body. Therefore, the structural complexity of the filter bare chip can be simplified and the material cost of the filter bare chip can be reduced.

[0008] Optionally, the height of the portion of the first cavity between the first transducer body and the second transducer body is greater than or equal to 500nm and less than or equal to 10μm. Specifically, the height of the portion of the first cavity can be selected to be 500nm, 600nm, 800nm, 1um, 2um, 4um, 6um, 8um or 10um. In this way, the height of the first cavity is moderate, which can prevent the first cavity from disappearing when the second transducer body vibrates relative to the first transducer body, thereby effectively reflecting the energy of the first transducer body and the second transducer body to prevent energy loss, and at the same time is conducive to the thinning of the thickness of the filter bare chip.

[0009] Optionally, the first substrate is made of sapphire or silicon carbide.

[0010] Optionally, a first mirror reflection structure is provided on a side of the fourth metal layer facing away from the second piezoelectric layer, and at least a portion of the first mirror reflection structure overlaps at least a portion of the second transducer body. The first cavity, the second transducer body and the first mirror reflection structure form an FBAR. The first mirror reflection structure, as a top reflection structure of the second transducer body, can reduce the energy loss of the second transducer body. Moreover, this layout is reasonable and the material cost is low.

[0011] Optionally, the filter bare chip further includes an annular side wall and a top cover. The annular side wall is arranged on the side of the second piezoelectric layer that is opposite to the first substrate, the axial direction of the annular side wall is consistent with the thickness direction of the second piezoelectric layer, and the end of the annular side wall that is opposite to the second piezoelectric layer forms a first opening. The top cover is arranged on the side of the annular side wall that is opposite to the second piezoelectric layer, and the top cover covers the first opening, and the top cover and the annular side wall form a second cavity, and the second cavity forms the above-mentioned first mirror reflection structure. This structure is simple and has low cost.

[0012] Optionally, the first substrate, the first transducer body and the first cavity form a HBAR. This structure is simple and has a reasonable layout.

[0013] Optionally, the first mirror reflection structure is a Bragg mirror reflection structure. In this way, the physical area in the filter bare chip accounts for a larger proportion, which can ensure the structural strength and stability.

[0014] Optionally, a second mirror reflection structure is provided between the first substrate and the first transducer body, and at least a portion of the second mirror reflection structure overlaps at least a portion of the first transducer body. The second mirror reflection structure, the first transducer body and the first cavity form an FBAR. The second mirror reflection structure, as a bottom reflection structure of the first transducer body, can reduce the bottom energy loss of the first transducer body. This structure is simple and has a reasonable layout.

[0015] Optionally, the surface of the first substrate substrate facing the first transducer body is the first surface, and the surface of the first substrate substrate facing away from the first transducer body is the second surface. Based on this, the first substrate substrate is provided with a third cavity, and the third cavity is recessed from the first surface to the second surface. The third cavity forms the above-mentioned second mirror reflection structure. This structure is simple and has low cost.

[0016] Optionally, the second mirror reflection structure is a Bragg mirror reflection structure. In this way, the physical area in the filter bare chip accounts for a larger proportion, which can ensure the structural strength and stability.

[0017] Optionally, a second substrate is provided on a side of the fourth metal layer facing away from the second piezoelectric layer, and at least a portion of the second substrate overlaps at least a portion of the second transducer body. In this way, the first cavity, the second transducer body and the second substrate form HBAR.

[0018] Optionally, the second metal layer further includes a first connection area, and the first connection area is spaced apart from the second electrode. A first metallized via is provided in the first piezoelectric layer, and the first metallized via is electrically connected between the first electrode and the first connection area. In this way, the first electrode can be led out to the second metal layer, which is convenient for further connection and has better appearance performance.

[0019] Optionally, the fourth metal layer further includes a third connection area and a fourth connection area, and the third connection area, the fourth connection area, and the fourth electrode are arranged at intervals. A third metallized via and a fourth metallized via are arranged in the second piezoelectric layer, the third metallized via is electrically connected between the second electrode and the third connection area, and the fourth metallized via is electrically connected between the first connection area and the fourth connection area. Thus, the first electrode and the second electrode are led out to the fourth metal layer, so that the first electrode and the second electrode are further led out to the upper end of the filter bare chip, which can ensure the appearance performance.

[0020] Optionally, the fourth metal layer further includes a second connection area. The second connection area is spaced apart from the fourth electrode. A second metallized via is provided in the second piezoelectric layer, and the second metallized via is electrically connected between the third electrode and the second connection area. Thus, the third electrode is led to the fourth metal layer, so that the third electrode and the fourth electrode are further led to the upper end, which can ensure the appearance performance.

[0021] Optionally, a through hole is provided in the second piezoelectric layer, one end of the through hole is opened on the surface of the second piezoelectric layer facing away from the first cavity, and the other end of the through hole is opened on the surface of the second piezoelectric layer facing the first cavity and is connected to the first cavity. The etching liquid can be poured into the first cavity area by means of the through hole, and the first cavity can be obtained by etching the sacrificial layer. This method is simple and easy to operate.

[0022] Optionally, the first piezoelectric layer and the second piezoelectric layer include piezoelectric materials, and the piezoelectric material includes at least one of aluminum nitride, scandium-doped aluminum nitride, lithium niobate, and lithium tantalate.

[0023] In a second aspect, a filter is further provided, the filter comprising a packaging substrate, a packaging material, and a filter bare chip as described in any of the above technical solutions. The filter bare chip is arranged on the packaging substrate, and the first transducer body of the filter bare chip is electrically connected to the second transducer body. The packaging material is arranged on the packaging substrate and covers the filter bare chip.

[0024] Since the filter provided in the present application includes a filter bare chip as described in any of the above technical solutions, and the filter bare chip is arranged on a packaging substrate, the area occupied by the filter bare chip on the packaging substrate can be reduced, the size of the packaging substrate can be reduced, and the size of the filter can be reduced.

[0025] In a third aspect, a radio frequency circuit board assembly is also provided, which includes a circuit board and a radio frequency circuit. The radio frequency circuit is arranged on the circuit board, and the radio frequency circuit includes the filter described in the above technical solution.

[0026] Since the RF circuit board assembly provided in the present application includes the filter described in the above technical solution, and the filter is arranged on the circuit board, the area occupied by the filter on the circuit board can be reduced, the size of the circuit board can be reduced, and thus the size of the RF circuit board assembly can be reduced.

[0027] In a fourth aspect, an electronic device is also provided, the electronic device comprising an antenna and a radio frequency circuit board assembly as described in the above technical solution. The radio frequency circuit board assembly is electrically connected to the antenna.

[0028] Since the electronic device provided in the present application includes the radio frequency circuit board assembly as described in the above technical solution, the radio frequency circuit board assembly is small in size and occupies less space in the electronic device, which is conducive to miniaturization of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A communication principle diagram of an electronic device provided for some embodiments of the present application;

[0030] Figure 2 A structural block diagram of a wake-up receiver provided in some embodiments of the present application;

[0031] Figure 3 A circuit diagram of a radio frequency filter provided in some embodiments of the present application;

[0032] Figure 4 A resonance waveform diagram of HBAR provided in some embodiments of the present application;

[0033] Figure 5 A resonance waveform diagram of a BPF provided in some embodiments of the present application;

[0034] Figure 6 for Figure 3 The filtering principle diagram of the RF filter shown;

[0035] Figure 7 A circuit diagram of a radio frequency filter provided in some other embodiments of the present application;

[0036] Figure 8 A schematic diagram of a cross-sectional structure of a radio frequency filter provided in some embodiments of the present application;

[0037] Fig. 9 for Figure 8 The schematic diagram of the structure of the HBAR bare chip in the RF filter shown;

[0038] Fig.10 for Figure 8 The schematic diagram of the structure of the FBAR bare chip in the RF filter shown;

[0039] Fig.11 for Figure 8 A top view of the radio frequency filter shown;

[0040] Fig.12 A schematic diagram of a cross-sectional structure of a filter provided in some other embodiments of the present application;

[0041] Fig.13 for Fig.12 A schematic diagram of a cross-sectional structure of a filter bare chip in the filter shown;

[0042] Fig.14 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0043] Fig.15 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0044] Fig.16 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0045] Fig.17 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0046] Fig.18 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0047] Fig.19 A schematic diagram of the cross-sectional structure of a filter bare chip provided in some other embodiments of the present application;

[0048] Fig. 20 A flowchart of a method for processing a filter provided in some embodiments of the present application. DETAILED DESCRIPTION

[0049] In the embodiments of the present application, the terms "first", "second", "third", "fourth", "fifth", and "sixth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third", "fourth", "fifth", and "sixth" may explicitly or implicitly include one or more of the features.

[0050] In the embodiments of the present application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0051] The present application provides an electronic device, which is a type of electronic device that includes a filter, and the electronic device includes but is not limited to mobile phones, tablet computers, laptop computers, smart TVs, cars, smart electronic tags, Bluetooth headsets, and wearable devices such as smart watches and smart bracelets.

[0052] The electronic device may include an antenna and a radio frequency circuit board assembly, wherein the radio frequency circuit board assembly is electrically connected to the antenna. The radio frequency circuit board assembly may generate a radio frequency transmission signal and transmit it to the antenna to transmit the signal with the help of the antenna. Alternatively, the radio frequency circuit board assembly may process the radio frequency signal from the antenna to receive the radio frequency signal.

[0053] The radio frequency circuit board assembly may include a circuit board and a radio frequency circuit disposed on the circuit board. Based on this, the filter in the electronic device may be applied to the radio frequency circuit, and the radio frequency circuit uses the filter to suppress useless signals and pass useful signals to achieve frequency selection of the radio frequency signal.

[0054] In other embodiments, the filter may also be applied to other circuits in electronic devices. This embodiment and the following embodiments are illustrative examples of the filter being applied to a radio frequency circuit in an electronic device, which cannot be considered as a special limitation to the present application.

[0055] In some embodiments, the filter in the electronic device provided by the present application can be selected as an acoustic wave filter. Compared with dielectric filters, metal cavity filters and waveguides, acoustic wave filters can have relatively small size and relatively good performance, and can be used in small electronic devices.

[0056] At the same time, in order to improve the frequency selectivity and heat dissipation of the filter, the acoustic wave filter is usually formed by connecting multiple resonators in series and / or in parallel. This results in a larger volume of the acoustic wave filter and occupies a larger area on the circuit board in the electronic device, which is not conducive to installation in electronic devices with limited space.

[0057] For an example, see Figure 1 , Figure 1 A communication schematic diagram of an electronic device 100 provided in some embodiments of the present application. The radio frequency circuit in the electronic device 100 may include a radio frequency receiving circuit. Specifically, the radio frequency receiving circuit includes a wake-up receiver 10. The wake-up receiver 10 is used to continuously monitor the channel with low power consumption. When the wake-up receiver 10 receives a first wake-up signal from the transmitter 200, a second wake-up signal is generated to wake up the main receiver 20, so as to establish a communication connection with the transmitter 200 through the main receiver 20 to realize signal reception and transmission. When the data or signal transmission is completed, the main receiver 20 returns to the sleep state, thereby reducing the system power consumption.

[0058] See also Figure 2 , Figure 2 The wake-up receiver 10 provided in some embodiments of the present application is a structural block diagram. The wake-up receiver 10 may include a radio frequency filter 101 , a self-mixer 102 , an intermediate frequency filter 103 and a wake-up signal generating module 104 .

[0059] The RF filter 101 is used to filter a mixed signal including an input signal (that is, the first wake-up signal mentioned above) and a background noise signal to obtain a first filtered signal, where the first filtered signal includes the input signal and part of the background noise signal.

[0060] The self-mixer 102 is connected to the RF filter 101, and is used to make the first filtered signal self-mix. Specifically, the input signal is self-mixed to obtain a modulated signal, a part of the background noise signal is self-mixed to obtain a noise self-mixing signal, and the input signal and a part of the background noise signal are mixed to obtain a signal-noise mixed signal. The self-mixer 102 is used to output a mixed signal, and the mixed signal includes a modulated signal, a noise self-mixing signal, and a signal-noise mixed signal.

[0061] The intermediate frequency filter 103 is connected to the self-mixer 102 and is used to filter the mixed signal to remove the noise self-mixing signal in the mixed signal to obtain a second filtered signal, wherein the second filtered signal includes a modulation signal.

[0062] The wake-up signal generating module 104 is connected to the intermediate frequency filter 103 and is configured to obtain a second wake-up signal according to the modulation signal.

[0063] Among them, the RF filter 101 is a filter provided in the RF receiving circuit of the electronic device. With the development of wireless communication technology, the frequency bands such as WiFi, Bluetooth, and ISM in which the wake-up receiver 10 works have become increasingly crowded, and there are strong background noise signals in the environment. In order to suppress out-of-band interference and improve anti-interference capability, the RF filter 101 needs to implement extremely narrowband filtering, the useful signal is a narrowband signal, and the out-of-band signal is suppressed as much as possible, thereby improving the signal to interference ratio (SIR).

[0064] To achieve this, please refer to Figure 3 , Figure 3 The circuit diagram of the radio frequency filter 101 provided in some embodiments of the present application is shown in FIG. 1. In this embodiment, the radio frequency filter 101 is formed by a high overtone bulk acoustic wave resonator (HBAR) and a band pass filter (BPF) connected in series.

[0065] The resonant wave of HBAR is as follows Figure 4 As shown in Figure 1, it includes multiple extremely narrow-band resonant waves (the bandwidth of a single resonant wave is within 1 MHz). Figure 5 As shown, it includes a single resonant wave with a larger bandwidth, and the bandwidth of the resonant wave can be 20MHz. Figure 6 , Figure 6 for Figure 3 The filtering principle diagram of the RF filter 101 is shown. After the mixed signal is filtered by HBAR, multiple signals with large frequency differences are formed. Further, under the filtering action of BPF, a signal in one resonant wave is selected to pass, and the signals in other multiple resonant waves are suppressed, thereby achieving extremely narrowband filtering and improving SIR.

[0066] The BPF may include at least one film bulk acoustic resonator (FBAR).

[0067] See also Figure 7 , Figure 7The circuit diagram of the radio frequency filter 101 provided in some embodiments of the present application. The BPF includes a plurality of FBARs, and the plurality of FBARs are connected in series and in parallel in multiple stages, so that the out-of-band suppression of the BPF can be improved.

[0068] Therefore Figure 1 The filter in the electronic device 100 is formed by electrically connecting one HBAR and at least one FBAR.

[0069] See also Figure 8 , Figure 8 The cross-sectional structure diagram of the radio frequency filter 101 provided in some embodiments of the present application. The radio frequency filter 101 includes a packaging substrate 1011, a HBAR bare chip 1012, a FBAR bare chip 1013, a packaging material 1014 and a pin 1015. Figure 8 In the embodiment shown, the number of the FBAR bare chip 1013 is one. In other embodiments, for example, when the circuit of the RF filter 101 is Figure 7 When the circuit is shown, the number of FBAR bare chips 1013 can be multiple, or multiple FBAR resonator units can be integrated on the same FBAR bare chip 1013.

[0070] The packaging substrate 1011 is used to carry the HBAR bare chip 1012 and the FBAR bare chip 1013 , and realize the series connection of the HBAR bare chip 1012 and the FBAR bare chip 1013 .

[0071] The packaging material 1014 covers the HBAR bare chip 1012 , the FBAR bare chip 1013 and the packaging substrate 1011 to protect the HBAR bare chip 1012 , the FBAR bare chip 1013 and the circuits on the packaging substrate 1011 from moisture, dust and scratches.

[0072] The pin 1015 is used to be welded to an external circuit to output a signal inside the filter to the external circuit, or to input a signal from the external circuit to the inside of the filter. In some embodiments, the pin 1015 may include a positive pin 10151 and a negative pin 10152 .

[0073] exist Figure 8 In the illustrated embodiment, the HBAR bare chip 1012 and the FBAR bare chip 1013 can be electrically connected to the package substrate 1011 by flip-chip mounting. In other embodiments, the HBAR bare chip 1012 and the FBAR bare chip 1013 can also be electrically connected to the package substrate 1011 by face-up mounting and gold wire bonding.

[0074] See also Fig. 9 , Fig. 9 for Figure 8The structure diagram of the HBAR bare chip 1012 in the RF filter 101 is shown. The HBAR bare chip 1012 includes a substrate 1012a, a metal layer 1012b, a metal layer 1012c, a piezoelectric layer 1012d, an annular sidewall 1012e, a top cover 1012f, a metal column 1012g and a pin 1012h.

[0075] The metal layer 1012b is disposed on the base substrate 1012a, and the metal layer 1012b includes a first electrode A1.

[0076] The metal layer 1012c is disposed on a side of the metal layer 1012b that is away from the base substrate 1012a. The metal layer 1012c includes a second electrode A2 and a first connection region B1.

[0077] The piezoelectric layer 1012d is disposed between the metal layer 1012b and the metal layer 1012c, and the overlapping portion of the first electrode A1, the piezoelectric layer 1012d and the second electrode A2 forms a first transducer body T1.

[0078] The first connection region B1 is electrically connected to the first electrode A1 via the metallized via 1012i to lead out a signal of the first electrode A1.

[0079] The annular sidewall 1012e is disposed on a side of the piezoelectric layer 1012d facing away from the base substrate 1012a and surrounds the metal layer 1012c.

[0080] The top cover 1012f is arranged at an opening at one end of the annular side wall 1012e facing away from the piezoelectric layer 1012d. The annular side wall 1012e and the top cover 1012f form a first cavity Q1. The first cavity Q1 is located on a side of the first transducer body T1 facing away from the substrate 1012a. The first cavity Q1 is used as a mirror reflection layer (mirror ref lector) to reduce the energy loss of the first transducer body T1.

[0081] The pin 1012h is disposed on a surface of the top cover 1012f away from the first cavity Q1. The number of the pins 1012h may be two, and the two pins 1012h are used to lead out the electrodes of the first electrode A1 and the second electrode A2.

[0082] The number of metal pillars 1012g can be two, one of which is electrically connected between one lead 1012h and the first connection area B1 to lead out the first electrode A1, and the other metal pillar 1012g is electrically connected between another lead 1012h and the second electrode A2 to lead out the second electrode A2.

[0083] The resonant frequency f of the Nth order mode of the HBAR bare chip 1012 is HBAR It can be determined by the following formula.

[0084]

[0085] Wherein, N is the order, N=1, 2, 3, ..., Tp is the thickness of the piezoelectric layer 1012d, Vp is the speed of sound in the piezoelectric layer 1012d, Ts is the thickness of the base substrate 1012a, and Vs is the speed of sound in the base substrate 1012a.

[0086] It can be seen from this that the thickness and material of the piezoelectric layer 1012d and the thickness and material of the substrate 1012a will determine the resonant frequency of the HBAR (that is, Figure 4 The distance d between the two resonance peaks in the waveguide.

[0087] See also Fig.10 , Fig.10 for Figure 8 The structure diagram of the FBAR bare chip 1013 in the radio frequency filter 101 is shown. The FBAR bare chip 1013 includes a substrate 1013a, a metal layer 1013b, a metal layer 1013c, a piezoelectric layer 1013d, an annular sidewall 1013e, a top cover 1013f, a metal column 1013g and a pin 1013h.

[0088] The metal layer 1013b is disposed on the base substrate 1013a, and the metal layer 1013b includes a third electrode A3.

[0089] The metal layer 1013c is disposed on a side of the metal layer 1013b that is away from the base substrate 1013a. The metal layer 1013c includes a fourth electrode A4 and a second connection region B2.

[0090] The piezoelectric layer 1013d is disposed between the metal layer 1013b and the metal layer 1013c, and the overlapping portion of the third electrode A3, the piezoelectric layer 1013d and the fourth electrode A4 forms a second transducer body T2.

[0091] A second cavity Q2 is provided between the second transducer body T2 and the base substrate 1013a. The second cavity Q2 is used as a mirror reflection layer (mirror reflection layer) and can reduce the energy loss of the second transducer body T2.

[0092] The second connection region B2 is electrically connected to the third electrode A3 by means of the metallized via 1013i to lead out the signal of the third electrode A3.

[0093] The annular sidewall 1013e ​​is disposed on a side of the piezoelectric layer 1013d facing away from the base substrate 1013a and surrounds the metal layer 1013c.

[0094] The top cover 1013f is arranged at an opening at one end of the annular side wall 1013e ​​facing away from the piezoelectric layer 1013d. The annular side wall 1013e ​​and the top cover 1013f form a third cavity Q3. The third cavity Q3 is located on the side of the second transducer body T2 facing away from the substrate 1013a, and is used as a mirror reflection layer (mirror ref lector), which can reduce the energy loss of the second transducer body T2.

[0095] The pin 1013h is disposed on a surface of the top cover 1013f away from the third cavity Q3. There are two pins 1013h, and the two pins 1013h are used to lead out the third electrode A3 and the fourth electrode A4, respectively.

[0096] There are two metal pillars 1013g, one of which is electrically connected between a pin 1013h and the second connection area B2 to lead out the electrode of the third electrode A3, and the other metal pillar 1013g is electrically connected between another pin 1013h and the fourth electrode A4 to lead out the electrode of the fourth electrode A4.

[0097] See also Fig.11 , Fig.11 for Figure 8 The top view of the RF filter 101 is shown, and the packaging material is hidden in the figure. The HBAR bare chip 1012 and the FBAR bare chip 1013 are laid flat on the packaging substrate 1011, so that the dimension L of the filter 101 in the length direction is large, and the filter 101 occupies a large area on the circuit board. In addition, the HBAR bare chip 1012 and the FBAR bare chip 1013 need to be made of annular side walls and top covers respectively to form a top reflection cavity, so that the filter 101 includes more layer structures and the cost is higher.

[0098] To solve the above problems, see Fig.12 , Fig.12 This is a schematic diagram of the cross-sectional structure of a filter provided in some embodiments of the present application. The filter is formed by connecting a plurality of resonators in series and / or in parallel. The filter can be used as Figure 2 The RF filter 101 of the wake-up receiver 10 in the electronic device 100 shown can also be used as other filters in the electronic device 100 or filters in other electronic devices. Figure 2 The RF filter 101 of the wake-up receiver 10 in the electronic device 100 is shown for exemplary purposes only, and this should not be considered as a special limitation to the present application.

[0099] See also Fig.12 The filter includes a packaging substrate 1, a filter bare chip 2, a packaging material 3 and a pin 4.

[0100] The package substrate 1 may include at least one metal layer and at least one insulating dielectric layer, and the insulating dielectric layer includes but is not limited to polyimide (PI). The package substrate 1 is used to carry the filter bare chip 2 and realize the electrical connection of multiple resonators in the filter bare chip 2, and the form of the electrical connection can be series and / or parallel.

[0101] The filter bare chip 2 may include at least two resonators stacked in a direction perpendicular to the package substrate 1. In some embodiments, the filter bare chip 2 may include HBAR and FBAR stacked in a direction perpendicular to the package substrate 1. In some other embodiments, the filter bare chip 2 may also include multiple FBARs stacked in a direction perpendicular to the package substrate 1. In some other embodiments, the filter bare chip 2 may also include multiple HBARs stacked in a direction perpendicular to the package substrate 1.

[0102] The packaging material 3 is disposed on the packaging substrate 1 and covers the filter bare chip 2 to provide waterproof, dustproof and scratch-proof protection for the filter bare chip 2. Optionally, the packaging material 3 may also cover the circuit on the packaging substrate 1. Materials of the packaging material 3 include, but are not limited to, epoxy resin, polyester resin, crystal glue and silicone.

[0103] The pin 4 is used to be welded to an external circuit to output a signal inside the filter to the external circuit, or to input a signal from the external circuit into the filter. In some embodiments, the pin 4 may include a positive pin 41 and a negative pin 42.

[0104] In some embodiments, see Fig.13 , Fig.13 for Fig.12 A schematic diagram of a cross-sectional structure of a filter bare chip 2 in the filter shown. The filter bare chip 2 may include a first substrate 21, a first metal layer 22, a second metal layer 23, a first piezoelectric layer 24, a third metal layer 25, a fourth metal layer 26 and a second piezoelectric layer 27.

[0105] The material of the first base substrate 21 includes, but is not limited to, single crystal silicon, crystalline quartz, silicon carbide, fused quartz, and sapphire.

[0106] The first metal layer 22 is provided on the first base substrate 21, and the first metal layer 22 includes the first electrode A1. The first metal layer 22 may be formed by the first electrode A1, that is, the first metal layer 22 only includes the first electrode A1. In addition to the first electrode A1, the first metal layer 22 may also include other metal regions, and the other metal layer regions are spaced apart from the first electrode A1. This embodiment and the following embodiments are exemplified by the first metal layer 22 being formed by the first electrode A1.

[0107] The second metal layer 23 is disposed on a side of the first metal layer 22 facing away from the first base substrate 21 , and the second metal layer 23 includes a second electrode A2 .

[0108] At least a portion of the first piezoelectric layer 24 is disposed between the first metal layer 22 and the second metal layer 23. The first piezoelectric layer 24 may include a piezoelectric material, which is used to achieve conversion between electrical signals and mechanical acoustic wave signals. For example, the piezoelectric material may include but is not limited to aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lithium niobate (LiNbO 3 ) and lithium tantalate (LiTaO 3 ) at least one of.

[0109] The overlapping portion of the first electrode A1 , the first piezoelectric layer 24 , and the second electrode A2 forms a first transducing body T1 .

[0110] The orthographic projection of the first electrode A1 on the first base substrate 21 is defined as the first projection, the orthographic projection of the first piezoelectric layer 24 on the first base substrate 21 is defined as the second projection, and the orthographic projection of the second electrode A2 on the first base substrate 21 is defined as the third projection. The overlapping area of ​​the first projection, the second projection and the third projection is defined as the first overlapping area.

[0111] Based on this, the part of the first electrode A1 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned first overlapping area is the first part, the part of the first piezoelectric layer 24 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned first overlapping area is the second part, and the part of the second electrode A2 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned first overlapping area is the third part.

[0112] On the basis of the above, the overlapping part of the first electrode A1, the first piezoelectric layer 24 and the second electrode A2 refers to: a laminated structure formed by the first part of the first electrode A1, the second part of the first piezoelectric layer 24 and the third part of the second electrode A2, and the laminated structure is also the first transducer body T1. One of the first electrode A1 and the second electrode A2 is used for electrical signal input, and the other is used for electrical signal output.

[0113] When an electrical signal of a different frequency is input by one of the first electrode A1 and the second electrode A2, an electrical signal of a certain frequency is converted into a mechanical acoustic wave signal in the first piezoelectric layer 24, and the mechanical acoustic wave signal is transmitted to the other of the first electrode A1 and the second electrode A2 to be further converted into an electrical signal output at the other electrode, thereby realizing frequency selection of the signal.

[0114] Please continue reading Fig.13The third metal layer 25 is disposed on the side of the second metal layer 23 facing away from the first metal layer 22, and the third metal layer 25 includes a third electrode A3. The third metal layer 25 can be formed by the third electrode A3, that is, the third metal layer 25 only includes the third electrode A3, and the third metal layer 25 can also include other metal regions in addition to the third electrode A3, and the other metal layer regions are spaced apart from the third electrode A3. This embodiment and the following embodiments are exemplified by the third metal layer 25 being formed by the third electrode A3.

[0115] The fourth metal layer 26 is disposed on a side of the third metal layer 25 facing away from the second metal layer 23 , and the fourth metal layer 26 includes a fourth electrode A4 .

[0116] At least a portion of the second piezoelectric layer 27 is disposed between the third metal layer 25 and the fourth metal layer 26 . The second piezoelectric layer 27 may include a piezoelectric material, which is used to achieve conversion between an electrical signal and a mechanical sound wave signal.

[0117] The overlapping portion of the third electrode A3, the second piezoelectric layer 27 and the fourth electrode A4 forms a second transducing body T2.

[0118] The orthographic projection of the third electrode A3 on the first base substrate 21 is defined as the fourth projection, the orthographic projection of the second piezoelectric layer 27 on the first base substrate 21 is defined as the fifth projection, and the orthographic projection of the fourth electrode A4 on the first base substrate 21 is defined as the sixth projection. The overlapping area of ​​the fourth projection, the fifth projection and the sixth projection is defined as the second overlapping area.

[0119] Based on this, the part of the third electrode A3 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned second overlapping area is the fourth part, the part of the second piezoelectric layer 27 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned second overlapping area is the fifth part, and the part of the fourth electrode A4 whose orthographic projection on the first base substrate 21 overlaps with the above-mentioned second overlapping area is the sixth part.

[0120] Based on the above, the overlapping part of the third electrode A3, the second piezoelectric layer 27 and the fourth electrode A4 refers to: the stacked structure formed by the fourth part of the third electrode A3, the fifth part of the second piezoelectric layer 27 and the sixth part of the fourth electrode A4, and the stacked structure is also the second transducer body T2.

[0121] One of the third electrode A3 and the fourth electrode A4 is used for electrical signal input, and the other is used for electrical signal output.

[0122] When an electrical signal of a different frequency is input by one of the third electrode A3 and the fourth electrode A4, an electrical signal of a certain frequency is converted into a mechanical acoustic wave signal in the second piezoelectric layer 27, and the mechanical acoustic wave signal is transmitted to the other of the third electrode A3 and the fourth electrode A4 to be further converted into an electrical signal output at the other electrode, thereby realizing frequency selection of the signal.

[0123] On the basis of the above, please continue to refer to Fig.13 The filter bare chip 2 further includes a first cavity Q1. The first cavity Q1 is disposed between the second metal layer 23 and the third metal layer 25, and at least a portion of the first transducer body T1, at least a portion of the first cavity Q1, and at least a portion of the second transducer body T2 are overlapped, that is, the orthographic projections of at least a portion of the first transducer body T1, at least a portion of the first cavity Q1, and at least a portion of the second transducer body T2 on the first substrate 21 overlap.

[0124] In this way, the first transducer body T1 and the second transducer body T2 can form two resonators, which are stacked up and down, which can reduce the area occupied by the bare chip on the packaging substrate 1, which is conducive to reducing the size of the filter. In addition, the first transducer body T1 is used as the substrate of the second transducer body T2, and the second transducer body T2 is used as the top cover of the first transducer body T1. The first cavity Q1 is used as both the top reflection cavity of the first transducer body T1 and the bottom reflection cavity of the second transducer body T2. Therefore, the structural composition of the filter bare chip 2 can be simplified and the material cost of the filter bare chip 2 can be reduced.

[0125] exist Fig.13 In the embodiment shown, the first transducer body T1 and the second transducer body T2 are overlapped. In this way, the first transducer body T1 and the second transducer body T2 are aligned vertically, which can minimize the occupied area of ​​the bare chip on the packaging substrate 1.

[0126] In some other embodiments, see Fig.14 , Fig.14 The cross-sectional structure diagram of the filter bare chip 2 provided in some embodiments of the present application, the first transducer body T1 and the second transducer body T2 can also be arranged in an upper and lower offset manner, that is, a part of the first transducer body T1 and a part of the second transducer body T2 are arranged overlappingly.

[0127] In some other embodiments, the entire first transducer body T1 may be overlapped with a portion of the second transducer body T2; or a portion of the first transducer body T1 may be overlapped with the entire second transducer body T2, which is not specifically limited in the present application.

[0128] In any of the above embodiments, the first cavity Q1 can be obtained by etching the sacrificial layer. Based on this, in order to facilitate the injection of etching solution into the sacrificial layer, in some embodiments, refer to Fig.13 or Fig.14 At least one through hole h is also provided on the second piezoelectric layer 27, and "at least one" means one or more. One end of the through hole h is opened on the surface of the second piezoelectric layer 27 facing away from the first base substrate 21, and the other end is opened to communicate with the first cavity Q1. Thus, etching liquid can be poured into the sacrificial layer by means of the through hole h to form the first cavity Q1.

[0129] In some embodiments, please refer to Fig.13 and Fig.14 , the height H1 of the first cavity Q1 between the first transducer body T1 and the second transducer body T2 can be selected to be 500nm-10um. Specifically, the height H1 of the first cavity Q1 can be selected to be 500nm, 600nm, 800nm, 1um, 2um, 4um, 6um, 8um or 10um. In this way, the height of the first cavity Q1 is moderate, which can prevent the first cavity Q1 from disappearing when the second transducer body T2 vibrates relative to the first transducer body T1, thereby effectively reflecting the energy of the first transducer body T1 and the second transducer body T2 to prevent energy loss, and at the same time, it is beneficial to thin the thickness of the filter bare chip 2 and the filter.

[0130] In some embodiments, please refer to Fig.13 and Fig.14 , the first substrate 21, the first transducer body T1 and the first cavity Q1 can form HBAR. This structure is simple and has a reasonable layout. Based on this, the material of the first substrate 21 can be selected as sapphire or silicon carbide, which can improve the performance of HBAR, and the hardness of sapphire or silicon carbide is relatively large, which can improve the structural strength.

[0131] In some embodiments, to introduce the first electrode A1 and the second electrode A2 of the first transducer body T1, please continue to refer to Fig.13 and Fig.14 The second metal layer 23 may further include a first connection area B1. A first metallized via C1 may be provided in the first piezoelectric layer 24. The first metallized via C1 is electrically connected between the first electrode A1 and the first connection area B1, thereby leading the first electrode A1 to the second metal layer 23, facilitating further connection and having better appearance performance.

[0132] It should be noted that the metallized vias described in the above embodiments and the following embodiments include through holes arranged in the piezoelectric layer and metal materials arranged in the through holes. The metal materials can be selected from materials with relatively low resistivity. For example, the metal materials include but are not limited to molybdenum (Mo), gold (Au), gold-tin (Au-Sn) alloy, copper (Cu), copper-tin (Cu-Sn) alloy, aluminum (Al), aluminum alloy, etc., and the present application does not make specific limitations on this.

[0133] For further information, please refer to Fig.13 and Fig.14 The fourth metal layer 26 may further include a third connection area B3 and a fourth connection area B4, and a third metallized via C3 and a fourth metallized via C4 may further be provided in the second piezoelectric layer 27. The third metallized via C3 is electrically connected between the second electrode A2 and the third connection area B3, and the fourth metallized via C4 is electrically connected between the first connection area B1 and the fourth connection area B4, thereby leading the first electrode A1 and the second electrode A2 to the fourth metal layer 26, so as to further lead the first electrode A1 and the second electrode A2 to the upper end of the filter bare chip 2.

[0134] Similarly, to introduce the third electrode A3 and the fourth electrode A4 of the second transducer body T2, please continue to refer to Fig.13 and Fig.14 , the fourth metal layer 26 may further include a second connection area B2. A second metallized via C2 may also be provided in the second piezoelectric layer 27. The second metallized via C2 is electrically connected between the third electrode A3 and the second connection area B2, thereby leading the third electrode A3 to the fourth metal layer 26, so as to further lead the third electrode A3 and the fourth electrode A4 to the upper end of the filter bare chip 2.

[0135] In some embodiments, see Fig.15 , Fig.15 The cross-sectional structure diagram of the filter bare chip 2 provided in some embodiments of the present application, in this embodiment, the filter bare chip 2 includes Fig.13 In addition to the structure shown, it also includes an annular side wall 28 , a top cover 29 , a metal column 30 and a pin 31 .

[0136] The material of the annular side wall 28 includes but is not limited to polyimide (PI). The annular side wall 28 is disposed on the side of the second piezoelectric layer 27 that is opposite to the first base substrate 21, and the axial direction of the annular side wall 28 is consistent with the thickness direction of the second piezoelectric layer 27. The annular side wall 28 can be disposed around the periphery of the fourth electrode A4, or around the periphery of the entire fourth metal layer 26. One end of the annular side wall 28 that is opposite to the second piezoelectric layer 27 forms a first opening.

[0137] The top cover 29 is arranged on a side of the annular side wall 28 away from the second piezoelectric layer 27, and the top cover 29 covers the first opening. The annular side wall 28 and the top cover 29 enclose a second cavity Q2. At least a portion of the second cavity Q2 is at least partially overlapped with the second transducer body T2, that is, at least a portion of the orthographic projection of the second cavity Q2 on the first substrate 21 overlaps with at least a portion of the orthographic projection of the second transducer body T2 on the first substrate 21.

[0138] In this way, the second cavity Q2 forms a first mirror reflection structure, at least part of which overlaps with at least part of the second transducer body T2. The first mirror reflection structure serves as the top reflection structure of the second transducer body T2 and can reduce the energy loss of the second transducer body T2.

[0139] In some other embodiments, the first mirror reflection structure may also be replaced by a Bragg mirror reflection structure, which is formed by alternately stacking a plurality of high acoustic impedance layers and a plurality of low acoustic impedance layers, wherein the high acoustic impedance layer refers to a material layer having a higher acoustic impedance than the low acoustic impedance layer, and the low acoustic impedance layer refers to a material layer having a lower acoustic impedance than the high acoustic impedance layer. The portion of the Bragg mirror reflection structure facing the second transducer body T2 is the low acoustic impedance layer.

[0140] The first cavity Q1, the second transducer body T2 and the first mirror reflection structure form an FBAR. This layout is reasonable and has low material cost.

[0141] In some embodiments, see Fig.15 , a avoidance hole hd is provided on the annular side wall 28, and the avoidance hole hd is connected to the through hole h. In this way, the etching liquid can enter the area where the first cavity Q is located along the whole formed by the through hole h and the avoidance hole hd, so as to contact the sacrificial layer. Optionally, the number of the avoidance holes hd can be equal to the number of the through holes h, and they are connected one by one.

[0142] Please continue reading Fig.15 The number of the pins 31 may be four, and the four pins 31 are disposed on the surface of the top cover 29 facing away from the second piezoelectric layer 27. The structure of the pins 31 includes but is not limited to solder balls and solder pads. Fig.15 The pin 31 is used as a solder ball for example, so that the filter bare chip 2 can be flip-chip electrically connected to the Fig.12 On the packaging substrate 1 of the filter shown.

[0143] In other embodiments, the structure of the pin 31 can be selected as a pad, and in this case, the filter bare chip 2 can be electrically connected to the packaging substrate 1 in a face-up and gold wire bonding manner.

[0144] Please continue reading Fig.15The number of metal pillars 30 can be four, and the four metal pillars 30 correspond to the four pins 31 one by one. Among the four metal pillars 30, one metal pillar 30 is electrically connected between a corresponding pin 31 and the third connection area B3, one metal pillar 30 is electrically connected between a corresponding pin 31 and the fourth connection area B4, one metal pillar 30 is electrically connected between a corresponding pin 31 and the fourth electrode A4, and one metal pillar 30 is electrically connected between a corresponding pin 31 and the second connection area B2.

[0145] Among them, the metal column 30 can choose a material with relatively low resistivity. For example, the material of the metal column 30 includes but is not limited to molybdenum (Mo), gold (Au), gold-tin (Au-Sn) alloy, copper (Cu), copper-tin (Cu-Sn) alloy, aluminum (Al), aluminum alloy, etc., and the present application does not make specific limitations on this.

[0146] In addition, the processing method of the metal pillar 30 can be the same as the processing method of the aforementioned metallized via.

[0147] In this way, the first electrode A1 and the second electrode A2 of the first transducer body T1, and the third electrode A3 and the fourth electrode A4 of the second transducer body T2 can be led out to the surface of the top cover 29 facing away from the first base substrate 21 by means of four metal pillars 30 and four pins 31, so as to be externally connected to the packaging substrate 1, so as to further realize the series connection or parallel connection of the first transducer body T1 and the second transducer body T2 by means of the packaging substrate 1. This structure is simple, and the first transducer body T1 and the second transducer body T2 in the filter bare chip 2 are independent of each other, and the series connection or parallel connection is realized on the packaging substrate 1, which can improve the adaptability of the filter bare chip 2.

[0148] In other embodiments, the first transducer body T1 and the second transducer body T2 may also be connected in series inside the filter bare chip 2 .

[0149] For examples, see Fig.16 , Fig.16 Schematic diagram of the cross-sectional structure of the filter bare chip 2 provided in some embodiments of the present application. Fig.15 The difference of the filter bare chip 2 shown is that: in this embodiment, the fourth metal layer 26 further includes a connecting portion K, and the connecting portion K electrically connects the second connecting area B2 and the fourth connecting area B4 together.

[0150] In this way, the first transducer body T1 and the second transducer body T2 are connected in series by means of the connecting portion K. It is only necessary to respectively set metal pillars 30 in the third connecting area B3 and the fourth electrode A4 to respectively connect the two pins 31. This structure is simple and the cost is low.

[0151] For another example, see Fig.17 , Fig.17 Schematic diagram of the cross-sectional structure of the filter bare chip 2 provided in some embodiments of the present application. Fig.15 The difference of the filter bare chip 2 shown is that in this embodiment, the third metallized via C3 is electrically connected between the second electrode A2 and the third electrode A3.

[0152] In this way, the first transducer body T1 and the second transducer body T2 are connected in series by means of the third metallized via C3. It is only necessary to set metal pillars 30 in the fourth connection area B4 and the fourth electrode A4 to connect the two pins 31 respectively. This structure is simple and the cost is low.

[0153] Figure 15-17 The filter bare chip 2 shown is formed by stacking HBAR and FBAR. Fig.12 In the filter shown, HBAR and FBAR are connected in series to achieve extremely narrow-band filtering. This structure is simple and has a reasonable layout.

[0154] In some other embodiments, in addition to the filter bare chip 2, at least one FBAR bare chip may be disposed on the package substrate 1 in the filter to connect with the filter bare chip 2 to form a Figure 7 The circuit shown can thereby improve the out-of-band suppression of the BPF.

[0155] See also Fig.18 , Fig.18 Schematic diagram of the cross-sectional structure of the filter bare chip 2 provided in some embodiments of the present application. Fig.17 The difference of the filter bare chip 2 shown is that: in this embodiment, a third cavity Q3 is provided between the first substrate 21 and the first metal layer 22. In some embodiments, the surface of the first substrate 21 facing the first transducer body T1 is the first surface, and the surface of the first substrate 21 facing away from the first transducer body T1 is the second surface, based on which the third cavity Q3 is recessed from the first surface to the second surface. At least part of the third cavity Q3 overlaps with at least part of the first transducer body T1, that is, the orthographic projection of at least part of the third cavity Q3 on the first substrate 21 overlaps with the orthographic projection of at least part of the first transducer body T1 on the first substrate 21.

[0156] In this way, the third cavity Q3 forms a second mirror reflection structure, at least part of which overlaps with at least part of the first transducer body T1. The second mirror reflection structure serves as the bottom reflection structure of the first transducer body T1 and can reduce the bottom energy loss of the first transducer body T1.

[0157] In some other embodiments, the second mirror reflection structure may also be replaced by a Bragg mirror reflection structure, which is formed by alternately stacking a plurality of high acoustic impedance layers and a plurality of low acoustic impedance layers, wherein the high acoustic impedance layer refers to a material layer having a higher acoustic impedance than the low acoustic impedance layer, and the low acoustic impedance layer refers to a material layer having a lower acoustic impedance than the high acoustic impedance layer. The portion of the Bragg mirror reflection structure facing the first transducer body T1 is the low acoustic impedance layer.

[0158] The second mirror reflection structure, the first transducing body T1 and the first cavity Q1 form a FBAR.

[0159] In this way, the filter bare chip 2 is formed by stacking two FBARs up and down, which can also reduce the area occupied by the bare chip on the packaging substrate 1, which is conducive to reducing the size of the filter. At the same time, the first transducer body T is used as the substrate of the second transducer body T2, and the second transducer body T2 is also used as the top cover of the first transducer body T1. The first cavity Q1 is used as both the top reflection cavity of the first transducer body T1 and the bottom reflection cavity of the second transducer body T2, so the material cost of the filter bare chip 2 can be reduced.

[0160] When the filter bare chip 2 is applied to the filter, in order to achieve extremely narrow-band filtering, in addition to the filter bare chip 2, a HBAR bare chip may be arranged on the package substrate 1 in the filter to form a connection Figure 7 The circuit shown can thereby improve the out-of-band suppression of the BPF.

[0161] In other embodiments, the filter may also be provided with only the filter bare chip 2 to be used as a duplexer or a multiplexer.

[0162] In some other embodiments, see Fig.19 , Fig.19 Schematic diagram of the cross-sectional structure of the filter bare chip 2 provided in some other embodiments of the present application. In this embodiment, a second substrate 33 is provided on the side of the fourth metal layer 26 facing away from the second piezoelectric layer 27, and at least a portion of the second substrate 33 overlaps with at least a portion of the second transducer body T2. In this way, the first cavity Q1, the second transducer body T2 and the second substrate 33 can also form HBAR.

[0163] In any of the above embodiments, the materials of the first metal layer 22, the second metal layer 23, the third metal layer 25 and the fourth metal layer 26 can be selected from materials with relatively low resistivity. For example, at least one of molybdenum (Mo), gold (Au), gold-tin (Au-Sn) alloy, copper (Cu), copper-tin (Cu-Sn) alloy, aluminum (Al), aluminum alloy and the like can be selected.

[0164] The thickness of the first metal layer 22, the second metal layer 23, the third metal layer 25 and the fourth metal layer 26 can be selected to be 50nm-1um. Specifically, the thickness of the four metal layers can be selected to be 50nm, 100nm, 200nm, 300nm, 400nm, 600nm, 800nm ​​or 1um. In this way, the thickness of the metal layer is moderate, which can ensure the electrical performance and is conducive to the thinning of the filter bare chip 2 and the filter.

[0165] It should be noted that the “thickness” described in the above embodiment and the following embodiments refers to the size of the described object in a direction perpendicular to the first base substrate 21 .

[0166] The thickness of the first piezoelectric layer 24 between the first metal layer 22 and the second metal layer 23, and the thickness of the second piezoelectric layer 27 between the third metal layer 25 and the fourth metal layer 26 can be selected to be 100nm-10um. Specifically, the thickness of the two piezoelectric layers can be selected to be 100nm, 200nm, 300nm, 400nm, 600nm, 800nm, 1um, 2um, 4um, 6um, 8um or 10um. In this way, the thickness of the piezoelectric layer is moderate, the piezoelectric performance can be guaranteed, and it is also conducive to the thinning of the filter bare chip 2 and the filter.

[0167] The present application also provides a processing method, which is used to process the filter described in any of the above embodiments. Fig. 20 , Fig. 20 A flowchart of a filter processing method provided in some embodiments of the present application. The processing method may include the following steps S1 to S8.

[0168] Step S1: Arrange a first metal layer 22 on a first base substrate 21 to obtain Fig. 20 Specifically, step S1 can be implemented by physical vapor deposition (PVD), wherein PVD includes processes such as sputtering or evaporation.

[0169] The first metal layer 22 includes the first electrode A1. The first metal layer 22 may be formed by the first electrode A1, that is, the first metal layer 22 includes only the first electrode A1. The first metal layer 22 may also include other metal regions in addition to the first electrode A1, and the other metal regions are spaced apart from the first electrode A1. This embodiment and the following embodiments are exemplified by the first metal layer 22 being formed by the first electrode A1.

[0170] Step S2: a first piezoelectric layer 24 is provided on the surface of the first metal layer 22 facing away from the first base substrate 21, so as to obtain Fig. 20Specifically, step S2 can be implemented by physical vapor deposition (PVD).

[0171] The first piezoelectric layer 24 may only cover the first metal layer 22, but not cover the portion of the first base substrate 21 not covered by the first metal layer 22, or may cover the first metal layer 22 while also covering the portion of the first base substrate 21 not covered by the first metal layer 22. This embodiment and the following embodiments are illustrative in that the first piezoelectric layer 24 covers the first metal layer 22 while also covering the portion of the first base substrate 21 not covered by the first metal layer 22, which cannot be considered as a special limitation to the present application.

[0172] In some embodiments, after step S2, the filter processing method further includes the following steps S9 and S10.

[0173] Step S9: Arrange a first through hole N1 on the first piezoelectric layer 24 to obtain Fig. 20 The structure shown in (c) in FIG. 1 is a structure in which one end of the first through hole N1 is opened on the surface of the first piezoelectric layer 24 facing the first electrode A1, and the other end of the first through hole N1 is opened on the surface of the first piezoelectric layer 24 facing away from the first electrode A1. Specifically, step S9 can be implemented by etching.

[0174] Step S10: Arrange the first metal material K1 in the first through hole N1 to obtain Fig. 20 Specifically, step S10 can be implemented by physical vapor deposition (PVD) or electroplating.

[0175] The material of the first metal material K1 can be selected from materials with relatively low resistivity, for example, at least one of molybdenum (Mo), gold (Au), gold-tin (Au-Sn) alloy, copper (Cu), copper-tin (Cu-Sn) alloy, aluminum (Al), aluminum alloy and the like can be selected.

[0176] The first through hole N1 and the first metal material K1 form a first metallized via C1.

[0177] Step S3: Arrange a second metal layer 23 on the surface of the first piezoelectric layer 24 facing away from the first metal layer 22 to obtain Fig. 20 Specifically, step S3 can be implemented by physical vapor deposition (PVD).

[0178] The second metal layer 23 includes a second electrode A2.

[0179] In some embodiments, see Fig. 20In (e), the second metal layer 23 includes a first connection area B1 in addition to the second electrode A2. The first connection area B1 is spaced apart from the second electrode A2, and the first connection area B1 covers an end of the first metallized via C1 away from the first electrode A1, and is electrically connected to the first electrode A1 via the first metallized via C1.

[0180] In this way, the first electrode A1 can be led out to the second metal layer 23 by means of the first metallized via C1 , which can simplify the process difficulty and ensure the appearance performance of the filter bare chip 2 .

[0181] In some other embodiments, the second metal layer 23 may not have the first connection area B1, and the first piezoelectric layer 23 may not have the first metallized via C1. Instead, the first electrode A1 may be led out by other means (such as leads), which is not specifically limited in the present application.

[0182] Step S4: a first sacrificial layer N1 is provided on the surface of the second metal layer 23 facing away from the first piezoelectric layer 24 to obtain Fig. 20 Specifically, step S4 can be implemented by chemical vapor deposition (CVD).

[0183] The material of the first sacrificial layer N1 includes, but is not limited to, silicon oxide.

[0184] In some embodiments, see Fig. 20 In (f), the first sacrificial layer N1 may cover a portion of the second electrode A2, a portion of the first connection region B1, and a portion of the first piezoelectric layer 24 exposed by a gap between the second electrode A2 and the first connection region B1.

[0185] In other embodiments, the first sacrificial layer N1 may also cover the entire second metal layer 23 and a portion of the first piezoelectric layer 24 that is not covered by the second metal layer 23 .

[0186] This embodiment and the following embodiments are exemplified by using the first sacrificial layer N1 covering a portion of the second electrode A2 , a portion of the first connection region B1 , and a portion of the first piezoelectric layer 24 exposed by the gap between the second electrode A2 and the first connection region B1 .

[0187] Step S5: a third metal layer 25 is provided on the surface of the first sacrificial layer N1 facing away from the second metal layer 23, so as to obtain Fig. 20 Specifically, step S5 can be implemented by physical vapor deposition (PVD).

[0188] The third metal layer 25 may include a third electrode A3. Specifically, the third metal layer 25 may be formed by the third electrode A3, that is, the third metal layer 25 only includes the third electrode A3. The third metal layer 25 may also include other metal regions in addition to the third electrode A3, and the other metal regions are spaced apart from the third electrode A3. This embodiment and the following embodiments are exemplified by the third metal layer 25 being formed by the third electrode A3.

[0189] Step S6: a second piezoelectric layer 27 is provided on the surface of the third metal layer 25 facing away from the first sacrificial layer N1, so as to obtain Fig. 20 Specifically, step S6 can be implemented by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0190] In some embodiments, see Fig. 20 In (h), the first sacrificial layer N1 covers the third metal layer 25, and also covers the portion of the first sacrificial layer N1 not covered by the third metal layer 25, the second metal layer 23 not covered by the first sacrificial layer N1, and the first piezoelectric layer 24 not covered by the second metal layer 23. In this way, the process difficulty can be simplified, and it is convenient to set the metallized via to lead out the first electrode A1 and the second electrode A2.

[0191] On the basis of the above embodiment, optionally, after step S6, the filter processing method further includes the following steps S11 and S12.

[0192] Step S11: Arrange a second through hole N2, a third through hole N3 and a fourth through hole N4 on the second piezoelectric layer 27 to obtain Fig. 20 Specifically, step S11 can be implemented by an etching process.

[0193] One end of the second through hole N2 is opened at the surface of the second piezoelectric layer 27 facing the third electrode A3 , and the other end is opened at the surface of the second piezoelectric layer 27 facing away from the third electrode A3 .

[0194] One end of the third through hole N3 is opened on the surface of the second piezoelectric layer 27 facing the second electrode A2 , and the other end is opened on the surface of the second piezoelectric layer 27 facing away from the second electrode A2 .

[0195] One end of the fourth through hole N4 is opened on the surface of the second piezoelectric layer 27 facing the first connection area B1 , and the other end is opened on the surface of the second piezoelectric layer 27 facing away from the first connection area B1 .

[0196] Step S12: placing a second metal material K2 in the second through hole N2, placing a third metal material K3 in the third through hole N3, and placing a fourth metal material K4 in the fourth through hole N4, so as to obtain Fig. 20 Specifically, step S12 can be implemented by physical vapor deposition (PVD).

[0197] The second metal material K2, the third metal material K3 and the fourth metal material K4 can be selected from materials with relatively low specific resistance, for example, at least one of molybdenum (Mo), gold (Au), gold-tin (Au-Sn) alloy, copper (Cu), copper-tin (Cu-Sn) alloy, aluminum (Al), aluminum alloy, etc. Moreover, the materials of the second metal material K2, the third metal material K3 and the fourth metal material K4 can be the same or different, and this application does not make specific restrictions on this.

[0198] On the basis of the above, the second through hole N2 and the second metal material K2 form a second metallized via C2; the third through hole N3 and the third metal material K3 form a third metallized via C3; the fourth through hole N4 and the fourth metal material K4 form a fourth metallized via C4.

[0199] Step S7: Arrange a fourth metal layer 26 on the side of the second piezoelectric layer 27 facing away from the third metal layer 25 to obtain Fig. 20 The structure shown in (k).

[0200] The fourth metal layer 26 includes a fourth electrode A4. In some embodiments, the fourth metal layer 26 includes, in addition to the fourth electrode A4, a second connection region B2, a third connection region B3, and a fourth connection region B4.

[0201] The second electrode A2, the second connection region B2, the third connection region B3, and the fourth connection region B4 are arranged spaced apart from each other.

[0202] The second connection region B2 covers one end of the second metallized via C2 away from the third electrode A3 , and is electrically connected to the third electrode A3 via the second metallized via C2 , so as to lead the third electrode A3 to the fourth metal layer 26 .

[0203] The third connection region B3 covers one end of the third metallized via C3 away from the second electrode A2 , and is electrically connected to the second electrode A2 via the third metallized via C3 , so as to lead the second electrode A2 to the fourth metal layer 26 .

[0204] The fourth connection region B4 covers one end of the fourth metallized via C4 away from the first connection region B1 , and is electrically connected to the first connection region B1 via the fourth metallized via C4 , so as to lead the first electrode A1 to the fourth metal layer 26 .

[0205] In this way, the third electrode A3, the second electrode A2 and the first electrode A1 can be led out to the fourth metal layer 26 respectively by means of the second metallized via C2, the third metallized via C3 and the fourth metallized via C4, which is helpful to simplify the structural complexity and improve the appearance of the filter bare chip 2.

[0206] In some other embodiments, the fourth metal layer 26 may not be provided with at least one of the second connection area B2, the third connection area B3 and the fourth connection area B4, and the second piezoelectric layer 27 may not be provided with at least one of the second metallized via C2, the third metallized via C3 and the fourth metallized via C4, so as to lead out at least one of the third electrode A3, the second electrode A2 and the first electrode A1 by other means (such as leads), and the present application does not make any specific limitation on this.

[0207] Step S8: removing the first sacrificial layer N1 to form a first cavity Q1 between the second metal layer 23 and the third metal layer 25, thereby obtaining Fig. 20 The structure shown in (l).

[0208] Specifically, step S8 can be implemented by using a wet etching process.

[0209] Based on this, in some embodiments, before step S8 and after step S6, the filter processing method further includes the following step S13.

[0210] Step S13: at least one through hole h is provided on the second piezoelectric layer 27 at a portion opposite to the first sacrificial layer N1. One end of the through hole h is located on the surface of the second piezoelectric layer 27 facing the first sacrificial layer N1, and the other end is located on the surface of the second piezoelectric layer 27 facing away from the first sacrificial layer N1.

[0211] In this way, in step S8 , the through hole h can allow the etching solution to enter so as to dissolve the first sacrificial layer N1 , and can discharge the solution formed after the first sacrificial layer N1 reacts with the etching solution.

[0212] In some embodiments, after step S8, the processing method of the filter also includes: setting an annular side wall on the surface of the second piezoelectric layer 27 facing away from the first base substrate 21; setting a top cover at the end of the annular side wall away from the second piezoelectric layer 27, so that the annular side wall and the top cover form a second cavity; setting metal columns in the top cover and the second cavity; setting pins on the surface of the top cover facing away from the second piezoelectric layer 27 to lead out the electrodes of the second connection area B2, the third connection area B3, the fourth connection area B4 and the fourth electrode A4 respectively.

[0213] In the bare chip formed by the processing method described in this embodiment, the overlapping part of the first electrode A1, the first piezoelectric layer 24 and the second electrode A2 forms the first transducer body T1, the overlapping part of the third electrode A3, the second piezoelectric layer 27 and the fourth electrode A4 forms the second transducer body T2, and the first transducer body T1, the first cavity Q1 and the second transducer body T2 are at least partially overlapped. In this way, the first transducer body T1 and the second transducer body T2 can form two resonators, and the two resonators are stacked up and down, which can reduce the occupied area of ​​the bare chip on the packaging substrate 1, which is conducive to reducing the size of the filter. At the same time, the first transducer body T is used as the substrate of the second transducer body T2, and the second transducer body T2 is also used as the top cover of the first transducer body T1. The first cavity Q1 is used as both the top reflection cavity of the first transducer body T1 and the bottom reflection cavity of the second transducer body T2, so the material cost of the filter bare chip 2 can be reduced.

[0214] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0215] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A filter bare chip, characterized in that: include: a first substrate base plate; A first metal layer, the first metal layer is disposed on the first substrate, and the first metal layer includes a first electrode; a second metal layer, the second metal layer being disposed on a side of the first metal layer facing away from the first substrate, and the second metal layer comprising a second electrode; a first piezoelectric layer, at least a portion of the first piezoelectric layer is disposed between the first metal layer and the second metal layer, and an overlapping portion of the first electrode, the first piezoelectric layer, and the second electrode forms a first transducer body; a third metal layer, the third metal layer being disposed on a side of the second metal layer facing away from the first metal layer, the third metal layer comprising a third electrode; a fourth metal layer, the fourth metal layer being disposed on a side of the third metal layer facing away from the second metal layer, the fourth metal layer comprising a fourth electrode; a second piezoelectric layer, at least a portion of the second piezoelectric layer is disposed between the third metal layer and the fourth metal layer, and an overlapping portion of the third electrode, the second piezoelectric layer and the fourth electrode forms a second transducer body; a first cavity, wherein the first cavity is disposed between the second metal layer and the third metal layer, and at least a portion of the first transducer body, at least a portion of the first cavity, and at least a portion of the second transducer body are overlapped; The filter bare chip also includes an annular side wall and a top cover. The annular side wall is arranged on the side of the second piezoelectric layer facing away from the first substrate, and the top cover is arranged on the side of the annular side wall facing away from the second piezoelectric layer. The top cover and the annular side wall form a second cavity.

2. The filter bare chip according to claim 1, characterized in that: A height of a portion of the first cavity between the first transducer body and the second transducer body is greater than or equal to 500 nm and less than or equal to 10 μm.

3. The filter bare chip according to claim 1, characterized in that: At least a portion of the second cavity is overlapped with at least a portion of the second transducer body, and the second cavity forms a first mirror reflection structure.

4. The filter bare chip according to claim 3, characterized in that: The axial direction of the annular side wall is consistent with the thickness direction of the second piezoelectric layer, and the end of the annular side wall facing away from the second piezoelectric layer forms a first opening; The top cover covers the first opening.

5. The filter bare chip according to claim 3, characterized in that: The first mirror reflection structure is a Bragg mirror reflection structure.

6. The filter bare chip according to any one of claims 1 to 5, characterized in that: A second mirror reflection structure is provided between the first substrate and the first transducer body, and at least a portion of the second mirror reflection structure overlaps with at least a portion of the first transducer body.

7. The filter bare chip according to claim 6, characterized in that: The surface of the first substrate facing the first transducer body is a first surface, and the surface of the first substrate facing away from the first transducer body is a second surface; The first substrate is provided with a third cavity, and the third cavity is recessed from the first surface to the second surface; The third cavity forms the second mirror reflection structure.

8. The filter bare chip according to claim 7, characterized in that: The second mirror reflection structure is a Bragg mirror reflection structure.

9. The filter bare chip according to any one of claims 1 to 5, characterized in that: A second substrate is disposed on a side of the fourth metal layer facing away from the second piezoelectric layer, and at least a portion of the second substrate overlaps with at least a portion of the second transducer body.

10. The filter bare chip according to any one of claims 1 to 5, characterized in that: The second metal layer further includes a first connection region, and the first connection region is spaced apart from the second electrode; A first metallized via is provided in the first piezoelectric layer, and the first metallized via is electrically connected between the first electrode and the first connection area.

11. The filter bare chip according to claim 10, characterized in that: The fourth metal layer further includes a third connection area and a fourth connection area, and the third connection area, the fourth connection area, and the fourth electrode are arranged at intervals; A third metallized via and a fourth metallized via are provided in the second piezoelectric layer. The third metallized via is electrically connected between the second electrode and the third connection area, and the fourth metallized via is electrically connected between the first connection area and the fourth connection area.

12. The filter bare chip according to any one of claims 1 to 5, characterized in that: The fourth metal layer further includes a second connection region, and the second connection region is spaced apart from the fourth electrode; A second metallized via is provided in the second piezoelectric layer, and the second metallized via is electrically connected between the third electrode and the second connection area.

13. The filter bare chip according to any one of claims 1 to 5, characterized in that: A through hole is provided in the second piezoelectric layer, one end of the through hole is opened on the surface of the second piezoelectric layer facing away from the first cavity, and the other end of the through hole is opened on the surface of the second piezoelectric layer facing the first cavity and is connected to the first cavity.

14. The filter bare chip according to any one of claims 1 to 5, characterized in that: The first piezoelectric layer and the second piezoelectric layer include piezoelectric material, and the piezoelectric material includes at least one of aluminum nitride, scandium-doped aluminum nitride, lithium niobate, and lithium tantalate.

15. The filter bare chip according to any one of claims 1 to 5, characterized in that: The first substrate is made of sapphire or silicon carbide.

16. A filter, characterized in that: include: Package substrate; The filter bare chip according to any one of claims 1 to 15, wherein the filter bare chip is disposed on the packaging substrate, and the first transducer body and the second transducer body of the filter bare chip are electrically connected; A packaging material is disposed on the packaging substrate and covers the filter bare chip.

17. A radio frequency circuit board assembly, characterized in that: include: Circuit boards; A radio frequency circuit, wherein the radio frequency circuit is arranged on the circuit board, and the radio frequency circuit includes the filter according to claim 16.

18. The radio frequency circuit board assembly according to claim 17, characterized in that: The radio frequency circuit includes a wake-up receiver.

19. An electronic device, characterized in that: include: antenna; The radio frequency circuit board assembly of claim 17 or 18, wherein the radio frequency circuit board assembly is electrically connected to the antenna.

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