A silicon carbide power module and its integrated circuit, chip and chip packaging method

Abstract

The present application relates to the technical field of semiconductor power modules, and discloses a silicon carbide power module and its integrated circuit, chip and chip packaging method, wherein the silicon carbide power module comprises silicon carbide power devices respectively located at the switch positions of the upper half bridge and the lower half bridge and driving circuits respectively driving the silicon carbide power devices, a gate resistor is connected in series between the output end of the driving circuit and the input end of the silicon carbide power device, a gate resistor is connected in parallel at both ends of the gate resistor, and the resistance of the gate resistor is less than the resistance of the gate resistor; the gate resistor is connected in parallel with a triode for releasing the accumulated potential of the lower half bridge, the base of the triode is electrically connected to the output end of the driving circuit, the emitter of the triode is electrically connected to the input end of the silicon carbide power device, and the collector of the triode is grounded. The present application has the effect of improving the reliability of silicon carbide power devices by using active Miller clamping control, reducing damage to silicon carbide power devices, and reducing production costs.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor power modules, and in particular to a silicon carbide power module and its integrated circuit, chip and chip packaging method. Background Art

[0002] At present, silicon carbide power modules are regarded as the game changers of the future power electronics industry. Due to their superior low internal resistance, high temperature resistance and high frequency characteristics, silicon carbide devices still have a relatively gentle internal resistance change rate under harsh conditions of >150°C. They have the advantages of low loss, high energy conversion efficiency, low heat generation and high energy utilization efficiency. They help to extend the battery life of energy storage equipment and achieve high power output, maintain the stable operation of the power grid, and can match the low loss and high efficiency requirements of power grid energy storage applications. They have excellent application potential in the application scenarios of high voltage, high current, high power and high heat consumption of power energy storage, meeting users' needs for high-performance energy storage equipment. However, when the metal-oxide semiconductor field-effect transistor MOSFET of the silicon carbide power module is turned on, when the voltage between DS jumps from high to low, the gate current charges the parasitic capacitance Cgd between the gate and the drain, but does not charge the gate-source capacitance Cgc, so that Vgs no longer rises, forming a Miller platform, which leads to increased MOSFET device losses, switching delays, and even parasitic conduction problems, which in turn cause device switching losses and EMC electromagnetic interference problems, affecting system stability.

[0003] The existing way to alleviate the influence of the Miller platform voltage of the switching tube is to reduce the input capacitance and output capacitance of the switching tube by adopting wafer manufacturing process and technology, but the cost of wafer manufacturing process and technology is high; or, by adopting the compensation design of the external circuit, adding a negative feedback signal amplifier, minimizing the line length and resistance as much as possible, reducing the external signal change, thereby reducing the switching delay, but the added external circuit increases the number of electronic components, the size of the PCBA circuit board is large, and the cost is increased.

[0004] With respect to the above-mentioned related technologies, the inventors found that the existing method of alleviating the influence of the Miller platform voltage of the switching tube has the problem of high production cost. Summary of the invention

[0005] In order to reduce the production cost of the existing method of alleviating the influence of the Miller platform voltage of the switching tube, the present application provides a silicon carbide power module and its integrated circuit, chip and chip packaging method.

[0006] In a first aspect, the present application provides a silicon carbide power module.

[0007] This application is achieved through the following technical solutions:

[0008] A silicon carbide power module, whose topology is a half-bridge type, comprises silicon carbide power devices respectively located at switch positions of an upper half bridge and a lower half bridge and drive circuits respectively driving the silicon carbide power devices, a gate resistor is connected in series between an output end of the drive circuit and an input end of the silicon carbide power device, a gate resistor is connected in parallel at both ends of the gate resistor, and the resistance of the gate resistor is smaller than the resistance of the gate resistor;

[0009] The gate resistor is connected in parallel with a transistor for releasing the accumulated potential of the lower half bridge, the base of the transistor is electrically connected to the output end of the drive circuit, the emitter of the transistor is electrically connected to the input end of the silicon carbide power device, and the collector of the transistor is grounded.

[0010] In a preferred example, the present application may be further configured as follows: the silicon carbide power device includes a silicon carbide MOS tube;

[0011] The gate of the silicon carbide MOS tube is electrically connected to the output end of the driving circuit via a gate resistor, and the drain of the silicon carbide MOS tube receives a driving signal from the driving circuit.

[0012] In a preferred example, the present application may be further configured as follows: the driving circuit includes a gate driver;

[0013] The output end of the gate driver is electrically connected to the input end of the silicon carbide power device.

[0014] In a preferred example, the present application can be further configured as follows: the silicon carbide power module is flat, and the cross-sectional size of the silicon carbide power module is >50mm*50mm.

[0015] In a preferred example, the present application can be further configured as follows: the pin-free creepage distance of the silicon carbide power module is >2mm.

[0016] In a second aspect, the present application provides an integrated circuit.

[0017] This application is achieved through the following technical solutions:

[0018] An integrated circuit comprises any one of the above-mentioned silicon carbide power modules.

[0019] In a third aspect, the present application provides a chip.

[0020] This application is achieved through the following technical solutions:

[0021] A chip includes an integrated circuit, wherein the integrated circuit includes any one of the above-mentioned silicon carbide power modules.

[0022] In a fourth aspect, the present application provides a packaging method for a silicon carbide power chip.

[0023] This application is achieved through the following technical solutions:

[0024] A method for packaging a silicon carbide power chip comprises the following steps:

[0025] Chip mounting: fixing the silicon carbide power module on a substrate, performing face-up chip mounting with the front side of the silicon carbide power module to obtain an upper chip, performing flip-chip chip mounting with the back side of the silicon carbide power module to obtain a lower chip, and connecting the upper chip and the lower chip in series;

[0026] Ball planting: spot welding a small metal ball on the silicon carbide power module, and welding a gold wire connecting the silicon carbide power module and the substrate to the small metal ball;

[0027] Plastic packaging: covering the silicon carbide power module and the gold wire with a layer of epoxy resin or plastic;

[0028] Primary grinding: grinding the silicon carbide power module according to a preset size and a preset flatness;

[0029] One-time drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, wherein the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material;

[0030] Primary electroplating: electroplating the silicon carbide power module;

[0031] Primary etching: etching the silicon carbide power module;

[0032] The finished product is plastic sealed.

[0033] In a preferred example, the present application can be further configured as follows: before the step of plastic sealing the finished product, it also includes:

[0034] Primary ABF material filling: filling the silicon carbide power module with ABF material until the first ABF layer is formed;

[0035] Ball planting auxiliary components: spot welding auxiliary components on the first ABF layer, the auxiliary components including flux or glue;

[0036] Mounting auxiliary components: fixing the silicon carbide power module to the substrate through the auxiliary components.

[0037] In a preferred example, the present application can be further configured as follows: after the step of attaching the auxiliary original, it also includes:

[0038] Secondary ABF material filling: filling the silicon carbide power module with ABF material again until a second ABF layer is formed;

[0039] Secondary polishing: polishing the silicon carbide power module according to a preset size and a preset flatness;

[0040] Secondary drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, wherein the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material;

[0041] Secondary electroplating: electroplating the silicon carbide power module;

[0042] Secondary etching: etching the silicon carbide power module.

[0043] In summary, compared with the prior art, the technical solution provided by this application has at least the following beneficial effects:

[0044] The silicon carbide power module adopting the half-bridge topology has the advantages of high efficiency conversion and compact size; and the gate resistor connected in series between the output end of the driving circuit and the input end of the silicon carbide power device can increase the gate impedance of the silicon carbide power module and improve the electromagnetic compatibility problem caused by fast switching in the silicon carbide power module; in particular, the two ends of the gate resistor are connected in parallel with a gate resistor, and the resistance of the gate resistor is smaller than the resistance of the gate resistor, so that the equivalent gate resistance is reduced, and then the source resistance (input resistance) of the driving circuit is reduced, further alleviating the influence of the Miller platform voltage of the switch tube; further, when the upper half bridge is turned on and the lower half bridge is turned off, the driving circuit of the upper half bridge is The first half-bridge outputs a high level, which causes the silicon carbide power device to turn on. After the voltage is input from the drain of the silicon carbide power device, the current is output through the half-bridge node; the driving circuit of the lower half-bridge outputs a low level, but because the drain of the silicon carbide power device accumulates a lot of potential, under the influence of parasitic capacitance, the gate of the silicon carbide power device also generates a certain high potential. Therefore, through the tiny resistance of the driving circuit, in conjunction with the triode connected in parallel with the gate-level resistance, the triode is turned on, so that the current flows from the emitter to the collector and then directly forms a path to the ground, ensuring extremely low Igs. The Miller capacitance Cgs is close to 0, realizing active Miller clamping control, while reducing the influence of the Miller effect and reducing switching losses. The potential accumulated in the bridge device has a path for release, which improves the reliability of the lower half bridge device; when the upper half bridge is turned off and the lower half bridge is turned on, the drive circuit of the upper half bridge outputs a low level, prompting the silicon carbide power device to be cut off. After the voltage is input from the drain of the silicon carbide power device and blocked by the upper half bridge, the drain of the silicon carbide power device accumulates a lot of potential. Under the influence of parasitic capacitance, the gate of the silicon carbide power device generates a certain high potential. Therefore, through the tiny resistance of the drive circuit, in conjunction with the triode connected in parallel with the gate resistor, the triode is turned on, so that the current flows from the emitter to the collector and then directly forms a path to the ground, realizing active Miller clamp control, while reducing the influence of the Miller effect and reducing the switching At the same time as the loss, the potential accumulated in the upper half-bridge device has a path for release, which improves the reliability of the upper half-bridge device; the driving circuit of the lower half-bridge outputs a high level, prompting the silicon carbide power device to be turned on and grounded. The potential of the half-bridge node is on the high potential side relative to the potential of the silicon carbide power device of the lower half-bridge that is turned on and grounded. The current flows back from the half-bridge node to the silicon carbide power device of the lower half-bridge into the ground; furthermore, the present application adopts a gate-level resistor and a transistor to effectively alleviate the influence of the Miller platform voltage of the switching tube on the silicon carbide power module, reducing the production cost. At the same time, the active Miller clamp control is used to improve the reliability of the silicon carbide power device and reduce the damage of the silicon carbide power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the circuit connection relationship of a silicon carbide power module provided as an exemplary embodiment of the present application.

[0046] Figure 2 A schematic diagram of the back and front of a silicon carbide power module provided as another exemplary embodiment of the present application.

[0047] Figure 3 A schematic diagram of the main process of a packaging method for a silicon carbide power chip provided as another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0048] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed, but such modifications are protected by the patent law as long as they are within the scope of the claims of the present application.

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] In addition, the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article, unless otherwise specified, generally means that the associated objects before and after are in an "or" relationship.

[0051] Energy storage technology stores energy through media or equipment and releases it when needed. It is a key technology to solve the large-scale access of renewable energy and can be applied to distributed energy, smart grid, and energy Internet scenarios. Energy storage technology can increase the clean energy power generation ratio, thereby achieving clean and efficient utilization of fossil energy, effectively reducing pollutant emissions, and promoting the governance of environmental problems such as haze and improving the living environment. At the same time, the development of energy storage technology is related to the development of many important industries such as energy, transportation, and electricity. Especially in today's environment of increasing energy depletion and unbalanced supply and demand of energy consumption, energy storage technology can break through the time and space limitations of traditional energy models, and its important role is becoming increasingly prominent. In the field of energy storage, how to improve energy conversion efficiency and reduce losses is an important support for solving the peak shaving and valley filling of conventional electricity and improving the efficiency of conventional energy generation and transmission.

[0052] Furthermore, compared with traditional Si materials, SiC materials can withstand high temperatures as high as hundreds of degrees Celsius and still continue to work, while traditional Si materials are generally paralyzed above 150 degrees Celsius; the breakdown voltage of SiC (the maximum voltage that it can withstand without being broken down) is much higher than the breakdown voltage of Si, that is, SiC performs better than Si in high-voltage applications; and SiC has good electrical conductivity; therefore, in the scenario of high-frequency and high-efficiency conversion of electrical energy, the performance of power devices made of SiC materials is better than that of power devices made of Si materials.

[0053] In addition, the Miller effect of the switching tube in power devices can easily lead to increased losses of MOSFET devices and IGBT devices, switching delays, and even parasitic conduction and EMC electromagnetic interference, resulting in device damage and affecting the stability of the system. During the conduction of the MOSFET tube, when the voltage between DS jumps from high to low, the gate current charges the parasitic capacitance Cgd between the gate and the drain, but does not charge the gate-source capacitance Cgc, which causes the gate voltage VGS to no longer rise, forming a Miller voltage platform; or, during the conduction or shutdown of the IGBT composite tube, the gate voltage VGE or VGS no longer conforms to the RC charging model of the gate voltage, and the gate voltage remains basically unchanged for a period of time during the switching process. From the driving waveform, there will be a platform voltage. The Miller effect is more obvious when MOSFET and IGBT are loaded with inductive switches. The main source of loss of the Miller effect on the power switch tube is the switching loss, that is, the power loss of the electronic energy during the charging process, which is reflected in the amount of charge inside the MOSFET, the equivalent input capacitance Cgd and the equivalent output capacitance Cgs, affecting the parasitic capacitance Cds.

[0054] Therefore, wafer manufacturing processes or external circuit compensation designs are generally used to alleviate the impact of the Miller platform voltage of silicon carbide power devices, but the production cost is relatively high. For this reason, the present application is based on the existing silicon carbide power module and adopts an embedded structure of a gate resistor and a transistor to embed the compensation circuit for suppressing the Miller effect into the device, which effectively alleviates the impact of the Miller platform voltage of the switching tube on the silicon carbide power module and reduces the production cost. At the same time, the active Miller clamping control is used to improve the reliability of the silicon carbide power device and reduce the damage of the silicon carbide power device.

[0055] The embodiment of the present application provides a silicon carbide power module, whose topology structure is a half-bridge type, including:

[0056] Silicon carbide power devices located at the switch positions of the upper half bridge and the lower half bridge, respectively, and driving circuits for driving the silicon carbide power devices, respectively, a gate resistor is connected in series between the output end of the driving circuit and the input end of the silicon carbide power device, and gate resistors are connected in parallel at both ends of the gate resistor, and the resistance of the gate resistor is less than the resistance of the gate resistor;

[0057] The gate resistor is connected in parallel with a transistor for releasing the accumulated potential of the lower half bridge, the base of the transistor is electrically connected to the output end of the drive circuit, the emitter of the transistor is electrically connected to the input end of the silicon carbide power device, and the collector of the transistor is grounded.

[0058] The present application adopts a gate-level resistor and a transistor to effectively alleviate the influence of the Miller platform voltage of the switching tube on the silicon carbide power module, thereby reducing the production cost. At the same time, the active Miller clamp control is used to improve the reliability of the silicon carbide power device, reduce the damage of the silicon carbide power device, and ensure the stability of the silicon carbide power module.

[0059] It is worth noting that the Miller effect charges the input and output capacitors inside the half-bridge SiC power device when it is switched, causing the voltage of the SiC power device to be unable to continuously increase or decrease, resulting in switching losses of the device; and the larger the input and output capacitances, the longer the Miller voltage platform effect is maintained, and the greater the switching losses of the device. Furthermore, due to the fast switching speed of SiC power devices, when the SiC power device is turned on or off quickly, the parasitic capacitance Cds and output capacitance Cgs inside the device will instantly supplement a reverse voltage output, causing the gate voltage VGS of the device to generate a large spike pulse before it is turned on, causing greater damage to the device. Therefore, how to suppress the Miller effect of the half-bridge SiC power module is crucial to the working reliability of the SiC power module.

[0060] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.

[0061] Reference Figure 1 , exemplarily, the silicon carbide power device adopts a silicon carbide MOS tube.

[0062] The gate G of the silicon carbide MOS tube of the upper half bridge is electrically connected to the output end of the driving circuit via the gate resistor Rg, the drain D of the silicon carbide MOS tube of the upper half bridge receives the driving signal HV_BUS of the driving circuit, and the source S of the silicon carbide MOS tube of the upper half bridge is electrically connected to the drain D of the silicon carbide MOS tube of the lower half bridge.

[0063] Exemplarily, the driving circuit adopts a Gate driver, and an output end of the Gate driver is electrically connected to an input end of the silicon carbide power device.

[0064] The output end of the gate driver (Gate#1) of the upper half bridge is electrically connected to the gate G of the silicon carbide MOS tube of the upper half bridge via the gate resistor Rg of the upper half bridge.

[0065] According to the equivalent input voltage Vgd = (gate resistance Rg + circuit parallel resistance Rnew after adding Miller control) * equivalent output current Igs, the smaller the Gate source resistance, the smaller the impact of the Miller platform effect, reducing the current path loss of the device. 并 The gate resistor R of the upper half bridge is connected in parallel. 并 The resistance of is smaller than the resistance of the gate resistor Rg of the upper half bridge.

[0066] The gate resistance R of the upper half bridge 并 The two ends are connected in parallel with the transistor of the upper half bridge, the base B of the transistor is electrically connected to the output end of the gate driver of the upper half bridge, the emitter E of the transistor is electrically connected to the gate G of the silicon carbide MOS tube of the upper half bridge, and the collector C of the transistor is grounded GND1.

[0067] The base B of the transistor of the upper half bridge is electrically connected to the output end of the gate driver of the upper half bridge via the first resistor R1 , and the base B of the transistor of the upper half bridge is connected to the ground GND1 via the second resistor R2 .

[0068] By adding a transistor, when Vgs reaches the conduction threshold of the transistor, the transistor is triggered to turn on, so that the current is directly directed to the ground after passing through the transistor, ensuring extremely low Igs. Since there is no current flowing through Igs, the Miller capacitance Cgs is close to 0, realizing active Miller clamping control and effectively alleviating the impact of the Miller effect on the device.

[0069] The output end of the gate driver (Gate#2) of the lower half bridge is electrically connected to the gate G of the silicon carbide MOS tube of the lower half bridge through the gate resistor Rg of the lower half bridge, and the source S of the silicon carbide MOS tube of the lower half bridge is grounded GND.

[0070] Similarly, the two ends of the gate resistor Rg of the lower half bridge and the gate resistor R 并 The gate resistor R of the lower half bridge is connected in parallel. 并 The resistance of is smaller than the resistance of the gate resistor Rg of the lower half bridge.

[0071] Similarly, the gate resistance R 并 The two ends are connected in parallel with the transistor of the lower half bridge, the base B of the transistor is electrically connected to the output end of the gate driver of the lower half bridge, the emitter E of the transistor is electrically connected to the gate G of the silicon carbide MOS tube of the lower half bridge, and the collector C of the transistor is grounded GND2.

[0072] The base B of the transistor of the lower half bridge is electrically connected to the output end of the gate driver of the lower half bridge via the first resistor R1 , and the base B of the transistor of the lower half bridge is connected to the ground GND2 via the second resistor R2 .

[0073] In one embodiment, since the size of Eon (tsw starts from 10% of VGE and ends at 2% of VCE) and Eoff (tsw starts from 90% of VGE and ends at 2% of IC) is directly related to parasitic inductance, parasitic capacitance, and line resistance, the reduction of Eon and Eoff can be achieved by reducing the parasitic parameters of the package interconnection such as parasitic inductance, parasitic capacitance, and line resistance circuit at the package level, such as reducing the size and length of the internal resistance and inductance of the device, or increasing the cross-sectional area of ​​the resistance or inductance to reduce the parasitic parameters such as parasitic inductance, parasitic resistance, and line resistance. In this embodiment, optimization can be performed by reducing the size and length of the internal resistance and inductance of the device.

[0074] Further, refer to Figure 2 a and Figure 2 b. In one embodiment, the silicon carbide power module is flat, and the cross-sectional size of the silicon carbide power module is >50mm*50mm, so as to ensure that the high heat dissipation demand for the silicon carbide power module in the energy storage field is met while taking into account the energy storage power size.

[0075] In one embodiment, the silicon carbide power module is a pinless power module product. Considering the creepage requirement, the pinless creepage distance of the silicon carbide power module is >2mm to meet the high heat dissipation requirements of the silicon carbide power module in the energy storage field.

[0076] The implementation principle of a silicon carbide power module in the embodiment of the present application is as follows:

[0077] When the upper half bridge is turned on and the lower half bridge is turned off: the Gate driver of the upper half bridge outputs a high level, so that the drain D-source S of the silicon carbide MOS tube of the upper half bridge is turned on, and the voltage is input from HV_BUS and output through the half-bridge node PHASE. At this time, the drain D of the silicon carbide MOS tube of the lower half bridge accumulates a lot of potential; the Gate driver of the lower half bridge outputs a low level, and the drain D of the silicon carbide MOS tube of the lower half bridge accumulates a lot of potential. Under the influence of the equivalent parasitic capacitance Cds of the silicon carbide MOS tube, the gate of the silicon carbide MOS tube of the lower half bridge G also generates a certain high potential, which easily leads to the micro-opening of the silicon carbide MOS tube of the lower half bridge, causing the loss of the silicon carbide MOS tube. Therefore, the present application adopts a gate resistor with a resistance value less than the gate resistance value between the driving circuit and the silicon carbide power device in combination with a transistor, so that the Gate source resistance is reduced, the Miller platform effect of the module is alleviated, and the base B of the transistor is enabled through the small Gate resistance, driving the emitter E-collector C of the transistor to conduct to the ground, and then the potential accumulated in the drain D of the silicon carbide MOS tube of the lower half bridge is released to GND2 through the transistor. At this time, the charge on the equivalent output capacitor Cgs of the silicon carbide MOS tube of the lower half bridge is almost zero, which well protects VGS, improves the reliability of the silicon carbide power device of the lower half bridge, reduces switching losses, and reduces the influence of the Miller effect on the silicon carbide power module.

[0078] When the upper half bridge is turned off and the lower half bridge is turned on: the Gate driver of the upper half bridge outputs a low level, so that the drain D-source S of the silicon carbide MOS tube of the upper half bridge is turned off, and the voltage is input from HV_BUS and blocked by the upper half bridge. At this time, the drain D of the silicon carbide MOS tube of the upper half bridge accumulates a lot of potential. Under the influence of the parasitic capacitance Cds, Vd passes through Cds to make the gate G of the silicon carbide MOS tube of the upper half bridge also generate a certain high potential, which can easily make the silicon carbide power device of the upper half bridge slightly turned on, causing the loss of the silicon carbide power device. Therefore, the present application adopts a gate-level resistor with a resistance value less than the gate resistance value between the driving circuit and the silicon carbide power device in combination with a transistor, so that the equivalent gate resistance is reduced, and then Ga te source resistance (Gate gate driver input resistance) is reduced, which alleviates the Miller platform effect of the module, and enables the base B of the transistor through the small Gate resistance, driving the emitter E-collector C of the transistor to conduct to the ground, and then the potential accumulated in the drain D of the silicon carbide MOS tube of the upper half bridge is released to GND1 through the transistor, thereby improving the reliability of the silicon carbide power device of the upper half bridge, reducing switching losses, and reducing the influence of the Miller effect on the silicon carbide power module; the lower half bridge is turned on, and the potential of the half-bridge node PHASE is on the high potential side relative to the potential of the silicon carbide power device of the lower half bridge that is turned on and grounded, and the current flows back from the half-bridge node to the silicon carbide power device of the lower half bridge and leads to the ground GND.

[0079] Each part of the above-mentioned silicon carbide power module can be fully or partially implemented by software, hardware or a combination thereof.

[0080] An embodiment of the present application also provides an integrated circuit, comprising any one of the above-mentioned silicon carbide power modules.

[0081] An embodiment of the present application also provides a chip, including an integrated circuit, which includes any one of the above-mentioned silicon carbide power modules.

[0082] Reference Figure 3 The present application also provides a method for packaging a silicon carbide power module. The method for packaging a silicon carbide power module corresponds one-to-one to the silicon carbide power module in the above embodiment. The method for packaging a silicon carbide power module includes:

[0083] Chip: fix the silicon carbide power module on the substrate;

[0084] Ball planting: spot welding a small metal ball on the silicon carbide power module, and welding a gold wire connecting the silicon carbide power module and the substrate to the small metal ball;

[0085] Plastic packaging: covering the silicon carbide power module and the gold wire with a layer of epoxy resin or plastic;

[0086] Primary grinding: grinding the silicon carbide power module according to a preset size and a preset flatness;

[0087] One-time drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material, so as to realize electrical interconnection of the chip;

[0088] Primary electroplating: electroplating the silicon carbide power module;

[0089] Primary etching: etching the silicon carbide power module;

[0090] The finished product is plastic-sealed.

[0091] In one embodiment, before the step of plastic packaging the finished product, the step further includes:

[0092] Primary ABF material filling: filling the silicon carbide power module with ABF material until the first ABF layer is formed;

[0093] Ball planting auxiliary components: spot welding auxiliary components on the first ABF layer, the auxiliary components include flux or glue; the auxiliary components can be epoxy resin glue, organic silicone glue, acrylic glue, etc.;

[0094] Mounting auxiliary components: fixing the silicon carbide power module to the substrate through the auxiliary components.

[0095] In one embodiment, after the step of attaching the auxiliary original, the method further includes:

[0096] Secondary ABF material filling: filling the silicon carbide power module with ABF material again until a second ABF layer is formed;

[0097] Secondary polishing: polishing the silicon carbide power module according to a preset size and a preset flatness;

[0098] Secondary drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material to achieve electrical interconnection of the chips;

[0099] Secondary electroplating: electroplating the silicon carbide power module;

[0100] Secondary etching: etching the silicon carbide power module.

[0101] This embodiment adopts the MODING process to achieve a 5-layer circuit design: the bottom layer is the PAD layer, the second layer is the power switch device layer, the third layer is the PHASE circuit layer; the fourth layer is the compensation electronic component layer, the fifth layer is the compensation circuit layout layer, and the last layer is the EMC appearance MODING package.

[0102] In one embodiment, when the silicon carbide power module is fixed on a substrate, the following steps are included:

[0103] Performing face-up mounting on the front side of the silicon carbide power module to obtain an upper chip;

[0104] Perform flip-chip bonding on the back side of the silicon carbide power module to obtain a lower chip;

[0105] The upper chip and the lower chip are connected in series.

[0106] By combining the forward mounting and reverse mounting of silicon carbide power modules, the circuit topology path can be shortened, thereby reducing the capacitance, inductance and resistance, greatly reducing the parasitic parameters of silicon carbide power devices, reducing device losses and improving device power performance.

[0107] In summary, a silicon carbide power module and its integrated circuit, chip and chip packaging method use a gate-level resistor and a transistor as an embedded compensation circuit of the silicon carbide power module, which effectively alleviates the influence of the Miller platform voltage of the switching tube on the silicon carbide power module, suppresses the Miller effect, and reduces the production cost. At the same time, the active Miller clamping control is used to improve the reliability of the silicon carbide power device, reduce the damage of the silicon carbide power device, and ensure the stability of the silicon carbide power module.

[0108] In addition, the silicon carbide power module achieves low parasitic inductance and fast heat dissipation with a flat pinless package, and can be used in high-power and high-voltage energy storage applications.

[0109] Furthermore, the copper filling process technology is used during packaging to improve the thermal management capability of the silicon carbide power module, reduce parasitic parameters, and reduce dv / dt under thermal effects.

[0110] It should be understood that the execution order of each process in the above-mentioned embodiment should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0111] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A method for packaging a silicon carbide power chip, characterized in that: The following steps are included: Chip mounting: fixing the silicon carbide power module on the substrate, performing face-up mounting on the front side of the silicon carbide power module to obtain an upper chip, performing flip-chip mounting on the back side of the silicon carbide power module to obtain a lower chip, and connecting the upper chip and the lower chip in series; Ball planting: spot welding a small metal ball on the silicon carbide power module, and welding a gold wire connecting the silicon carbide power module and the substrate to the small metal ball; Plastic packaging: covering the silicon carbide power module and the gold wire with a layer of epoxy resin or plastic; Primary grinding: grinding the silicon carbide power module according to a preset size and a preset flatness; One-time drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, wherein the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material; Primary electroplating: electroplating the silicon carbide power module; Primary etching: etching the silicon carbide power module; The finished product is plastic sealed.

2. The packaging method of silicon carbide power chip according to claim 1, characterized in that: Before the step of plastic sealing the finished product, the step further includes: Primary ABF material filling: filling the silicon carbide power module with ABF material until the first ABF layer is formed; Ball planting auxiliary components: spot welding auxiliary components on the first ABF layer, the auxiliary components including flux or glue; Mounting auxiliary components: fixing the silicon carbide power module to the substrate through the auxiliary components.

3. The packaging method of silicon carbide power chip according to claim 2, characterized in that: After the step of attaching the auxiliary original part, the method further includes: Secondary ABF material filling: filling the silicon carbide power module with ABF material again until a second ABF layer is formed; Secondary polishing: polishing the silicon carbide power module according to a preset size and a preset flatness; Secondary drilling and copper pouring: drilling and copper pouring the insulating dielectric material on the silicon carbide power module, wherein the silicon carbide power module is electrically connected to the substrate through the copper-filled holes on the insulating dielectric material; Secondary electroplating: electroplating the silicon carbide power module; Secondary etching: etching the silicon carbide power module.

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