A non-differential coupled analog storage and computing unit

Abstract

The present invention discloses a non-differential decoupled analog storage and computing integrated unit, which specifically relates to the field of AI chip technology, including: a data storage circuit and a non-differential decoupled synaptic circuit; the non-differential decoupled synaptic circuit includes: a 4-state setting circuit, a synaptic capacitor and a conjugate discharge circuit; the information output end of the data storage circuit is connected to the signal input end in the 4-state setting circuit, and the output end of the 4-state setting circuit and the positive electrode of the synaptic capacitor are both connected to the input end of the conjugate discharge circuit; the output end of the conjugate discharge circuit is connected to the OUT signal line. The present invention is based on a dynamic CMOS logic circuit design to realize a storage and computing integrated unit circuit with a non-differential decoupled characteristic of unidirectional transmission characteristics, and realizes an SRAM storage and computing integrated array with multi-bit computing capabilities; effectively solves the problems of storage wall and power consumption wall in the transmission and processing of massive data, and improves the stability, reliability and processing efficiency of the system.

Description

Technical Field

[0001] The present invention relates to the field of AI chip technology, and more specifically, to a non-differential coupled analog storage and computing integrated unit. Background Art

[0002] It is known that with the development of artificial neural network technology, commercial neural network acceleration applications have put forward higher requirements on hardware computing power, which are mainly manifested in faster response speed, higher computing energy efficiency and higher autonomous controllability; however, data processing is separated from storage, and large-scale data processing will lead to frequent data migration, which causes waste of CPU performance and reduced rapid response capability, and also generates additional power consumption, the magnitude of which even exceeds the computing behavior itself; therefore, a new data-centric computing architecture - a storage and computing integrated structure has gradually attracted widespread attention.

[0003] Among them, the integrated storage and computing chip provides a new design idea for neural network hardware: by embedding a certain computing power inside the memory, such as embedding computing units on the chip periphery or in the storage array to reduce data migration between the memory and the processor, thereby improving the computing speed, alleviating bandwidth pressure and reducing power consumption; from the computing paradigm point of view, there are two types of integrated storage and computing architecture: digital and analog: the computing unit of the digital integrated storage and computing solution is implemented by a digital adder or multiplier, while the analog storage and computing solution realizes multiplication and accumulation operations through current, voltage superposition or charge accumulation.

[0004] At present, analog storage and computing integrated chips have shown better prospects in neural network acceleration because the design of multiplication and addition circuits is more concise and effective, and neural networks have a relatively high tolerance for calculation accuracy;

[0005] The core structure of the analog storage and computing integration includes three parts: input unit, output unit and storage and computing unit. The peripheral circuit mainly includes memory access interface and control circuit. The input unit converts the external input digital signal into an analog signal that can be used for the storage and computing integration array. The storage unit calculates the input analog signal and transmits the calculation result to the output unit in the form of analog voltage or current. The output unit performs analog-to-digital conversion and then outputs the digital signal to the outside.

[0006] It is known that there are many integrated storage and computing circuit designs based on different storage media, including SRAM, FeFET, MRAM, Nand Flash, Nor Flash, RRAM, PCRAM, etc. Among them, due to the mature technology and the ability to directly use the most advanced process nodes, the analog storage and computing integrated design based on SRAM has shown greater cost-effectiveness advantages.

[0007] However, in actual use, the integrated storage and computing designs based on new non-volatile memory devices (FeFET, MRAM, Nand Flash, NorFlash, RRAM, PCRAM) are mostly still in the laboratory, and their cost and reliability still need to be improved; in contrast, the integrated storage and computing based on SRAM is considered to be an integrated storage and computing solution based on technical feasibility and commercial value because of its more mature technology and good coupling with advanced processes; however, due to the constraints of circuit structure, most of the analog integrated storage and computing circuits implemented based on SRAM currently use differential schemes to store negative information; in this scheme, the positive and negative properties are mainly characterized by the difference in positive and negative properties of the differential circuit, which in actual situations brings a lot of circuit redundancy, resulting in area and Waste of power consumption; for example: the existing storage-computing integrated technology integrates static memory (SRAM) and logic computing unit into one unit; in many designs, the SRAM stores the matrix data required for matrix-vector multiplication operations, receives vector information from outside the SRAM, and the logic computing unit performs multiplication and accumulation operations, but in the differential scheme, the implementation of negative elements of the matrix often means double the logic computing units; therefore, compared with the differential scheme, the negative weight element unit implemented based on the non-differential scheme has a smaller storage area, which can achieve higher integration and smaller area; therefore, a non-differential decoupled analog storage-computing integrated unit is proposed as a further improvement. Summary of the invention

[0008] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a non-differential coupled analog storage and computing integrated unit to solve the problems raised in the above-mentioned background technology.

[0009] To achieve the above object, the present invention provides the following technical solution: a non-differential decoupled analog storage and computing integrated unit, comprising: a data storage circuit and a non-differential decoupled synaptic circuit;

[0010] The non-differential decoupled synaptic circuit comprises: a 4-state setting circuit, a synaptic capacitor and a conjugate discharge circuit;

[0011] The information output terminal of the data storage circuit is connected to the signal input terminal of the 4-state setting circuit, the output terminal of the 4-state setting circuit and the positive electrode of the synaptic capacitor are both connected to the input terminal of the conjugate discharge circuit; the output terminal of the conjugate discharge circuit is connected to the OUT signal line;

[0012] The sign signal, the resn signal and the res signal are all input into the 4-state setting circuit; the pulse signal and the pulsen signal are all input into the conjugate discharge circuit.

[0013] Further, the 4-state setting circuit includes: a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube;

[0014] Two sign signals are respectively input into the G pole of the first NMOS tube and the G pole of the first PMOS tube, the resn signal and the res signal are respectively input into the S pole of the first NMOS tube and the D pole of the first PMOS tube, the information output terminals Qn and Q of the data storage circuit are respectively connected to the S pole of the second NMOS tube and the D pole of the second PMOS tube, the D pole of the first NMOS tube is connected to the G pole of the second NMOS tube, the S pole of the first PMOS tube is connected to the G pole of the second PMOS tube, and the D pole of the second NMOS tube, the S pole of the second PMOS tube and the positive pole of the synaptic capacitor are all connected to the conjugate discharge circuit.

[0015] Furthermore, the conjugate discharge circuit includes: a third NMOS tube and a third PMOS tube;

[0016] The pulse signal and the pulsen signal are respectively input into the G pole of the third NMOS tube and the G pole of the third PMOS tube, the D pole of the second NMOS tube, the S pole of the second PMOS tube, the positive pole of the synaptic capacitor, the D pole of the third NMOS tube and the D pole of the third PMOS tube are connected, and the S pole of the third NMOS tube and the S pole of the third PMOS tube are both connected to the OUT signal line.

[0017] Furthermore, the non-differential decoupled synaptic circuit has two working states: reset and release;

[0018] In the reset phase: the pulse signal is low, the pulsen signal is high; the res signal is pulled high, the resn signal is pulled low, and the res signal and the resn signal are a pair of conjugate signals;

[0019] In the release phase: the res signal is pulled low and the resn signal is pulled high. At this time, when there is a pulse input, the pulse is pulled high to VDD / 2 and the pulsen signal is pulled low to VDD / 2.

[0020] Furthermore, in the reset phase: if Q=0, the synaptic capacitor is in an insensitive state, then the synaptic capacitor will not be fully charged or discharged:

[0021] When sign=0, the second NMOS tube is turned off, and the first PMOS tube and the second PMOS tube are turned on; if the two PMOS tubes bring a voltage rise of 2×Vthp, the synaptic capacitor voltage Vcbl cannot be fully configured to VDD or GND, but is preset to 2×Vthp;

[0022] When sign = 1, the second PMOS transistor is turned off, and the first NMOS transistor and the second NMOS transistor are turned on. If the two NMOS transistors introduce a voltage drop of 2×Vthn, the voltage Vcbl of the synaptic capacitor cannot be fully configured to VDD or GND, but is pre-set to VDD - 2×Vthn; in the subsequent release stage: the gate voltage of the third NMOS transistor and the gate voltage of the third PMOS transistor are both VDD / 2; the VGS of the third PMOS transistor > -Vthp, and the VGS of the third NMOS transistor < Vthn. If the third NMOS transistor and the third PMOS transistor are turned off, the synaptic capacitor is in the refractory state, and the synaptic capacitor does not release any positive or negative charges, that is, the current on the OUT signal line is 0.

[0023] Further, in the reset stage: if Q = 1 and the synaptic capacitor is in the responsive state, then the configuration direction of the synaptic capacitor voltage Vcbl is determined by the sign signal at this time:

[0024] When sign = 0, the first PMOS transistor and the second PMOS transistor are turned on. At this time, the synaptic capacitor voltage Vcbl is pre-charged to VDD; in the subsequent release stage: the third PMOS transistor is turned on, and the third NMOS transistor is turned off. The non-differential decoupled synaptic circuit is allowed to release positive charges to the OUT signal line in the release stage, and this positive current decreases as the synaptic capacitor voltage decreases and approaches 0 as the synaptic capacitor voltage approaches VDD / 2 + Vthp. The total amount of charge released to the OUT signal line is: +(VDD / 2 - Vthp) × synaptic capacitor;

[0025] When sign = 1, the first NMOS transistor and the second NMOS transistor are turned on, and the synaptic capacitor is pre-discharged to 0V. At this time, the third PMOS transistor is turned off, and the third NMOS transistor is turned on. The non-differential decoupled synaptic circuit is allowed to release negative charges in the release stage. The total amount of charge released at this time is: -(VDD / 2 - Vthn) × synaptic capacitor.

[0026] The technical effects and advantages of the present invention:

[0027] 1. Compared with the prior art, the present invention is based on the design of a dynamic CMOS logic circuit, realizes a circuit structure with unidirectional transmission characteristics, obtains a memory-computation integrated unit circuit with non-differential decoupling characteristics, and realizes a SRAM memory-computation integrated array with multi-bit computing capabilities; effectively solves the problems of memory wall and power wall in the transmission and processing of massive data, and improves the stability, reliability and processing efficiency of the system.

[0028] 2. Compared with the corresponding differential circuit, the non-differential decoupled synaptic circuit designed by the present invention saves a set of capacitor overheads and is area-friendly. It also implements a charge transfer storage and computing solution instead of a charge balancing solution, and has no DC component. It realizes a unidirectional current transmission characteristic, and the reverse conductance is extremely small, that is, the voltage on the OUT signal line will basically not be coupled to the inside of the synaptic capacitor. The decoupling circuit connects the storage and computing array with the PADC circuit through a simple partially biased PMOS tube, thereby constraining the voltage on the OUT signal line to the voltage range required for decoupling, decoupling the positive weight storage and computing unit, the negative weight storage and computing unit and the PADC circuit, and fixing the storage and computing array to unidirectionally transmit current to the PADC, which significantly improves the calculation dynamic range of the PADC circuit and improves the linearity of the storage and computing array performing analog MAC calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of the non-differential coupled synaptic circuit of the present invention.

[0030] Figure 2 It is a structural schematic diagram of the data storage circuit of the present invention.

[0031] Figure 3 Schematic diagram of the control signal timing of the non-differential decoupled synaptic circuit of the present invention.

[0032] Figure 4 It is a structural schematic diagram of a 5-bit non-differential coupled signed storage and calculation integrated unit of the present invention.

[0033] Figure 5 It is a non-differential decoupled storage and computing crossbar structure in which the storage and computing units are decoupled from each other.

[0034] Figure 6 It is a structural diagram of the pulse ADC circuit.

[0035] The accompanying drawings are marked as follows:

[0036] 1. Data storage circuit;

[0037] 2. Non-differential coupled synaptic circuit;

[0038] 21. 4-state set circuit;

[0039] N1, first NMOS tube; N2, second NMOS tube; P1, first PMOS tube; P2, second PMOS tube; 22, synaptic capacitor;

[0040] 23. Conjugate discharge circuit; N3, the third NMOS tube; P3, the third PMOS tube;

[0041] C1: capacitor; C2: capacitor; P4: fourth PMOS tube; N4: fourth NMOS tube; N5: fifth NMOS tube; N6: sixth NMOS tube. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] As attached Figure 1-4 The non-differential decoupled analog storage and computing integrated unit shown includes: a data storage circuit 1 and a non-differential decoupled synaptic circuit 2;

[0044] Wherein, the data storage circuit 1 is used to store weight data;

[0045] The non-differential decoupled synaptic circuit 2 comprises: a 4-state setting circuit 21, a synaptic capacitor 22 and a conjugate discharge circuit 23;

[0046] The 4-state setting circuit 21 is used to preset the capacitor voltage to one of four levels according to the sign information and the weight information;

[0047] Among them, the conjugate discharge circuit 23 generates a positive or negative current to the OUT signal line according to the capacitance level, and the reverse current is 0; it ensures that the current is unidirectional from the storage and computing unit to the pulse ADC circuit, and significantly reduces the coupling between the pulse sending behavior of the pulse ADC circuit and the storage and computing unit; the non-differential decoupled synaptic circuit 2 realizes a non-differential negative weight storage and computing circuit, and adopts charge transfer rather than charge balancing to eliminate DC current and improve linearity. The constructed storage and computing circuit can respond to input data in pulse form and generate calculation results in pulse form.

[0048] in, Figure 1 The non-differential decoupled synaptic circuit 2 is shown to be composed of a 4-state setting circuit 21, a synaptic capacitor 22 and a conjugate discharge circuit 23, with a total of 3 NMOS tubes, 3 PMOS tubes and a capacitor; the non-differential characteristic of the non-differential decoupled synaptic circuit 2 is reflected in the use of only one capacitor to simultaneously realize the positive and negative weighting schemes;

[0049] The information output terminal of the data storage circuit 1 is connected to the signal input terminal of the 4-state setting circuit 21, the output terminal of the 4-state setting circuit 21 and the positive electrode of the synaptic capacitor 22 are both connected to the input terminal of the conjugate discharge circuit 23; the output terminal of the conjugate discharge circuit 23 is connected to the OUT signal line;

[0050] in, Figure 2An SRAM memory cell is shown, which is a standard 6T SRAM cell used for data storage circuit 1;

[0051] The sign signal, the resn signal and the res signal are all input into the 4-state setting circuit 21 ; the pulse signal and the pulsen signal are all input into the conjugate discharge circuit 23 .

[0052] Among them, the pulse signal is conjugated with the pulsen signal, and the res signal is conjugated with the resn signal, that is, when one signal is high, the other signal is low;

[0053] In a preferred embodiment, as shown in the attached Figure 1-4 As shown, the 4-state setting circuit 21 includes: a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1 and a second PMOS tube P2;

[0054] The two sign signals are respectively input into the G pole of the first NMOS tube N1 and the G pole of the first PMOS tube P1, the resn signal and the res signal are respectively input into the S pole of the first NMOS tube N1 and the D pole of the first PMOS tube P1, the information output terminals Qn and Q of the data storage circuit 1 are respectively connected to the S pole of the second NMOS tube N2 and the D pole of the second PMOS tube P2, the D pole of the first NMOS tube N1 is connected to the G pole of the second NMOS tube N2, the S pole of the first PMOS tube P1 is connected to the G pole of the second PMOS tube P2, and the D pole of the second NMOS tube N2, the S pole of the second PMOS tube P2 and the positive pole of the synaptic capacitor 22 are all connected to the conjugate discharge circuit 23.

[0055] In a preferred embodiment, as shown in the attached Figure 1-4 As shown, the conjugate discharge circuit 23 includes: a third NMOS transistor N3 and a third PMOS transistor P3;

[0056] The pulse signal and the pulsen signal are respectively input into the G pole of the third NMOS tube N3 and the G pole of the third PMOS tube P3, the D pole of the second NMOS tube N2, the S pole of the second PMOS tube P2, the positive pole of the synaptic capacitor 22, the D pole of the third NMOS tube N3 and the D pole of the third PMOS tube P3 are connected, and the S pole of the third NMOS tube N3 and the S pole of the third PMOS tube P3 are both connected to the OUT signal line.

[0057] In a preferred embodiment, as shown in the attached Figure 1-4 As shown, the non-differential coupled synaptic circuit 2 has two working states: reset and release;

[0058] Reset phase: the pulse signal is low, the pulsen signal is high; the res signal is pulled high, and the resn signal is pulled low;

[0059] At this time, the 4-state setting circuit 21 preset the capacitor to one of the four levels according to the information Q, Qn stored in the data storage circuit 1 and the symbol signal sign;

[0060] Release stage: The res signal is pulled low and the resn signal is pulled high. At this time, when a pulse is input, the pulse is pulled high to VDD / 2 and the pulsen signal is pulled low to VDD / 2.

[0061] In a preferred embodiment, as shown in the appendix Figure 1-4 As shown, in the reset stage: If Q = 0 and the synaptic capacitor 22 is in the refractory state, then the synaptic capacitor 22 will not be fully charged or discharged at this time:

[0062] That is: corresponding to weight 0:

[0063] When sign = 0, the second NMOS transistor N2 is turned off, and the first PMOS transistor P1 and the second PMOS transistor P2 are turned on; if the two PMOS transistors bring a voltage rise of 2×Vthp, the voltage Vcbl of the synaptic capacitor 22 cannot be fully configured to VDD or GND, but is preset to 2×Vthp;

[0064] When sign = 1, the second PMOS transistor P2 is turned off, and the first NMOS transistor N1 and the second NMOS transistor N2 are turned on. If the two NMOS transistors bring a voltage drop of 2×Vthn, the voltage Vcbl of the synaptic capacitor 22 cannot be fully configured to VDD or GND, but is preset to VDD - 2×Vthn; in the subsequent release stage: the gate voltages of the third NMOS transistor N3 and the third PMOS transistor P3 are both VDD / 2; the VGS of the third PMOS transistor P3 > -Vthp, and the VGS of the third NMOS transistor N3 < Vthn. If the third NMOS transistor N3 and the third PMOS transistor P3 are turned off, the synaptic capacitor 22 is in the refractory state, and the synaptic capacitor 22 does not release any positive or negative charges, that is, the current on the OUT signal line is 0.

[0065] Wherein, Vthn and Vthp are the turn-on voltages of the NMOS and PMOS transistors respectively;

[0066] In a preferred embodiment, as shown in the appendix Figure 1-4 As shown, in the reset stage: If Q = 1 and the synaptic capacitor 22 is in the responsive state, then the configuration direction of the voltage Vcbl of the synaptic capacitor 22 is determined by the sign signal at this time:

[0067] When sign=0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, at this time, the voltage Vcbl of the synaptic capacitor 22 is precharged to VDD; in the subsequent release phase: the third PMOS transistor P3 is turned on, and the third NMOS transistor N3 is turned off, and the non-differential decoupled synaptic circuit 2 is allowed to release positive charge to the OUT signal line in the release phase, and this forward current decreases as the voltage of the synaptic capacitor 22 decreases, and approaches 0 in the process of the voltage approaching VDD / 2+Vthp. The total amount of charge released to the OUT signal line is: +(VDD / 2-Vthp)×synaptic capacitor 22; the corresponding weight is +1.

[0068] When sign=1, the first NMOS transistor N1 and the second NMOS transistor N2 are turned on, and the synaptic capacitor 22 is pre-discharged to 0V. At this time, the third PMOS transistor P3 is turned off, and the third NMOS transistor N3 is turned on. The non-differential decoupled synaptic circuit 2 is allowed to release negative charges in the release phase. At this time, the total amount of charge released is: -(VDD / 2-Vthn)×synaptic capacitor 22; the corresponding weight is -1.

[0069] Among them, by adjusting the MOS tube parameters, Vthn is equal to Vthp.

[0070] Among them, the non-differential coupled analog storage and computing integrated unit is as follows Figure 4 As shown, it is composed of a 5-bit data storage circuit 1 for storing weight data and four non-differential coupled synaptic circuits 2 with different synaptic capacitances;

[0071] Among them, Weight[4] is used to indicate the weight sign, abbreviated as W[4], and the remaining 4-bit data uses the capacitance value to realize bit weighting, abbreviated as W[3:0]. For the SRAM representing the i-th bit, the capacitance size of the corresponding synaptic capacitor 22 is: 2^i×synaptic capacitor 22; all 4 non-differential decoupled synaptic circuits 2 in a unit share an OUT signal line as the output signal line.

[0072] Among them, the non-differential decoupled synapse circuit 2 uses a half pulse as an input pulse; when the pulse is valid, for the conjugate discharge circuit 23, when the voltage of the OUT signal line is in the range of (VDD / 2-Vthn, VDD / 2+Vthp), the input impedance of the D pole approaches infinity; this characteristic is attributed to the intrinsic PN junction property of the MOS tube; therefore, for different synaptic capacitor 22 voltages Vcbl, the conjugate discharge circuit 23 has a unidirectional current characteristic; because the input impedance of the D / S electrode of the MOS tube approaches infinity under certain conditions, the OUT port voltage of the non-differential decoupled synapse will not have current flowing back to the non-differential decoupled synapse circuit 2 within a certain interval, but only affects the current output by the synaptic capacitor 22, regardless of the positive or negative weight; this characteristic is attributed to the unidirectional current characteristic, which is called the decoupling characteristic.

[0073] Among them, based on the decoupling characteristics, when multiple 5-bit non-differential decoupled signed storage-computation integrated units are connected in parallel, a non-differential decoupled storage-computation integrated crossbar structure in which the storage-computation integrated units are decoupled from each other can be obtained, such as Figure 5 As shown,

[0074] Among them, Pulse ADC is a pulse ADC circuit referred to as PADC. Figure 6 As shown; a fourth PMOS tube P4 is connected between PADC and the bit-cell array, and its gate voltage is biased to Vb; the conduction condition of the PMOS tube is that the voltage at the output end out of the NDDC bit-cell array is greater than Vb+Vthp; by adjusting the Vb voltage value, the voltage of the out signal line can be made to fall within the voltage range required for triggering the decoupling, thereby ensuring the decoupling between all 5-bit non-differential decoupled signed storage-computation integrated units on a column of Crossbar; at this time, the influence of the voltage change in the PADC on the bit-cell array is significantly weakened, and as a counteraction, the coupling influence of the control signal change in the bit-cell array on the PADC is also significantly weakened, both of which are beneficial to the storage-computation integrated circuit.

[0075] (By adjusting the Vbias voltage, the conductance of N4 can be adjusted to control the charge transfer rate between C1 and C2. For details, see the cited patent.)

[0076] Among them, PADC uses the charge integrator counter circuit proposed in [] as the functional main body to convert the charge from the non-differential coupled storage and computing integrated array into pulses;

[0077] Among them, PADC uses the charge integrator counter circuit proposed in [] as the functional main body to convert the charge from the non-differential coupled storage and computing integrated array into pulses;

[0078] In the set phase, i.e., the reset phase of the non-differential decoupled synaptic circuit 2, the SET signal is pulled high, so that the voltage of capacitor C1 is set to Vref, and capacitor C2 is completely discharged; in the calculation phase, i.e., the release phase of the non-differential decoupled synaptic circuit 2, the charges from several 5-bit signed storage and calculation integrated units in the bit-cell array will be aggregated in the capacitor C1 of the PADC; and as the charge in capacitor C1 accumulates, capacitor C2 will also receive charge from capacitor C1, and the voltage of capacitor C2 will gradually rise. When the voltage of capacitor C2 is higher than the Vref voltage, the output signal of comparator COM will change from high to low, which will turn on N6 and open N5, thereby discharging C2 while retaining the charge of C1. The output signal of comparator COM passes through three inverters and is used as a pulse signal to drive a counter circuit. After several similar discharges, COM will emit a certain number of pulses, the specific number of which is determined by the total amount of charge from the bit-cell array. When the voltage of C1 is also lower than Vref, the whole calculation result, PADC successfully accumulates the multiplication result of 5-bit weight * 1-bit input of the storage and calculation unit in the bit-cell array, and generates the corresponding digital signal, that is, counter is the output data. When multiple groups of the above calculation cycles are completed, the multiplication and accumulation calculation operation of 5-bit weight * arbitrary precision input can be obtained.

[0079] References:

[0080] "Storage-computing integrated unit based on charge transfer and its storage-computing integrated structure";

[0081] "Analog storage and computing integrated structure based on pulse truncation circuit";

[0082] "Charge integrating and counting circuits and their analog storage and computing integrated structure".

[0083] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0084] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A non-differential coupled analog storage and computing integrated unit, characterized in that: The analog storage and computing integrated unit comprises: a data storage circuit (1) and a non-differential decoupled synaptic circuit (2); The non-differential decomposition coupling synaptic circuit (2) comprises: a 4-state setting circuit (21), a synaptic capacitor (22) and a conjugate discharge circuit (23); The information output end of the data storage circuit (1) is connected to the signal input end of the 4-state setting circuit (21); the output end of the 4-state setting circuit (21) and the positive electrode of the synaptic capacitor (22) are both connected to the input end of the conjugate discharge circuit (23); and the output end of the conjugate discharge circuit (23) is connected to the OUT signal line; The sign signal, the resn signal and the res signal are all input into the 4-state setting circuit (21); the pulse signal and the pulsen signal are all input into the conjugate discharge circuit (23); The 4-state setting circuit (21) comprises: a first NMOS tube (N1), a second NMOS tube (N2), a first PMOS tube (P1) and a second PMOS tube (P2); Two sign signals are respectively input into the G pole of the first NMOS tube (N1) and the G pole of the first PMOS tube (P1); the resn signal and the res signal are respectively input into the S pole of the first NMOS tube (N1) and the D pole of the first PMOS tube (P1); the information output terminals Qn and Q of the data storage circuit (1) are respectively connected to the S pole of the second NMOS tube (N2) and the D pole of the second PMOS tube (P2); the D pole of the first NMOS tube (N1) is connected to the G pole of the second NMOS tube (N2); the S pole of the first PMOS tube (P1) is connected to the G pole of the second PMOS tube (P2); the D pole of the second NMOS tube (N2), the S pole of the second PMOS tube (P2) and the positive pole of the synaptic capacitor (22) are all connected to the conjugate discharge circuit (23); The conjugate discharge circuit (23) generates a positive or negative current to the OUT signal line according to the capacitance level, while the reverse current is 0, ensuring that the current flows unidirectionally from the storage and computing integrated unit to the pulse ADC circuit, and significantly reducing the coupling between the pulse sending behavior of the pulse ADC circuit and the storage and computing integrated unit.

2. The non-differential coupled analog storage and computing integrated unit according to claim 1, characterized in that: The conjugate discharge circuit (23) comprises: a third NMOS tube (N3) and a third PMOS tube (P3); The pulse signal and the pulsen signal are respectively input into the G pole of the third NMOS tube (N3) and the G pole of the third PMOS tube (P3); the D pole of the second NMOS tube (N2), the S pole of the second PMOS tube (P2), the positive pole of the synaptic capacitor (22), the D pole of the third NMOS tube (N3) and the D pole of the third PMOS tube (P3) are connected; and the S pole of the third NMOS tube (N3) and the S pole of the third PMOS tube (P3) are both connected to the OUT signal line.

3. The non-differential coupled analog storage and computing integrated unit according to claim 2, characterized in that: The non-differential coupled synaptic circuit (2) has two working states: reset and release; In the reset stage: the pulse signal is low and the pulsen signal is high; the res signal is pulled high and the resn signal is pulled low, and the res signal and the resn signal are a pair of conjugate signals; In the release stage: the res signal is pulled low and the resn signal is pulled high. At this time, when a pulse is input, the pulse is pulled high to VDD / 2 and the pulsen signal is pulled low to VDD / 2.

4. The non-differential coupled analog storage and computing integrated unit according to claim 3, characterized in that: In the reset stage: If Q = 0 and the synaptic capacitor (22) is in the refractory state, the synaptic capacitor (22) will not be fully charged or discharged at this time: When sign = 0, the second NMOS transistor (N2) is turned off, and the first PMOS transistor (P1) and the second PMOS transistor (P2) are turned on; if the two PMOS transistors bring a voltage increase of 2×Vthp, the voltage Vcbl of the synaptic capacitor (22) cannot be fully configured to VDD or GND, but is preset to 2×Vthp; When sign = 1, the second PMOS transistor (P2) is turned off, and the first NMOS transistor (N1) and the second NMOS transistor (N2) are turned on. If the two NMOS transistors bring a voltage drop of 2×Vthn, the voltage Vcbl of the synaptic capacitor (22) cannot be fully configured to VDD or GND, but is preset to VDD - 2×Vthn; In the subsequent release stage: the gate voltages of the third NMOS transistor (N3) and the third PMOS transistor (P3) are both VDD / 2; the VGS of the third PMOS transistor (P3) > -Vthp, and the VGS of the third NMOS transistor (N3) < Vthn. If the third NMOS transistor (N3) and the third PMOS transistor (P3) are turned off, the synaptic capacitor (22) is in the refractory state, and the synaptic capacitor (22) does not release any positive or negative charges, that is, the current on the OUT signal line is 0.

5. The non-differential coupled analog storage and computing integrated unit according to claim 4, characterized in that: In the reset stage: If Q = 1 and the synaptic capacitor (22) is in the responsive state, the configuration direction of the voltage Vcbl of the synaptic capacitor (22) is determined by the sign signal at this time: When sign = 0, the first PMOS transistor (P1) and the second PMOS transistor (P2) are turned on. At this time, the voltage Vcbl of the synaptic capacitor (22) is precharged to VDD; in the subsequent release stage: the third PMOS transistor (P3) is turned on and the third NMOS transistor (N3) is turned off. The differential decoupled synaptic circuit (2) is allowed to release positive charges to the OUT signal line in the release stage, and this positive current decreases as the voltage Vcbl of the synaptic capacitor (22) decreases, and approaches 0 as the voltage Vcbl of the synaptic capacitor (22) approaches VDD / 2 + Vthp. The total amount of charge released to the OUT signal line is: +(VDD / 2 - Vthp) × synaptic capacitor (22); When sign=1, the first NMOS transistor (N1) and the second NMOS transistor (N2) are turned on, and the synaptic capacitor (22) is pre-discharged to 0V. At this time, the third PMOS transistor (P3) is turned off, and the third NMOS transistor (N3) is turned on. The non-differential decoupled synaptic circuit (2) is allowed to release negative charges in the release phase. At this time, the total amount of charge released is: -(VDD / 2-Vthn)×synaptic capacitor (22).

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