Power parallel control circuit and method, power management circuit, and electronic equipment

Abstract

The present application discloses a power parallel control circuit and method, a power management circuit, and an electronic device, wherein the power parallel control circuit includes: at least two current-sharing master control circuits, which respectively obtain the power supply output current provided by each power supply circuit to the external load circuit, and adjust each power supply output current to a current-sharing modulation voltage; a current-sharing bus, which receives the current-sharing modulation voltage sent by each current-sharing master control circuit to obtain the bus average current, and sends the bus average current to each current-sharing master control circuit, so that each current-sharing master control circuit uses the difference between the bus average current and each power supply output current to obtain a current-sharing output voltage, and each current-sharing output voltage is superimposed with the power supply output voltage provided by each power supply circuit to the load circuit, and then output to the load circuit. Through the above method, the power parallel control circuit in the present application can effectively take into account the high precision of the output voltage of each power supply circuit and the current-sharing degree.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to a power parallel control circuit and method, a power management circuit, and an electronic device. Background Art

[0002] Nowadays, in order to improve the power supply reliability and availability of the power supply system, or to increase the total power output capacity of the power supply system, it is usually necessary to parallel the power supply to connect two or more independent power supply systems in a specific way to jointly supply power to the load.

[0003] However, the existing power parallel control method often adopts proportional integral control, which has the problem of error accumulation. It is difficult to meet the current sharing index while meeting the customer's high-precision requirements for output voltage. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a power parallel control circuit and method, a power management circuit, and an electronic device, which can solve the problem that the power parallel control method in the prior art has error accumulation and it is difficult to meet the current equalization index while meeting the customer's high-precision requirements for the output voltage.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a power supply parallel control circuit, wherein the power supply parallel control circuit includes: at least two current balancing main control circuits, each current balancing main control circuit is used to couple with a power supply circuit to respectively obtain the power supply output current provided by the power supply circuit to the external load circuit, and adjust each power supply output current to a current balancing modulation voltage; a current balancing bus, coupled with each current balancing main control circuit to receive the current balancing modulation voltage sent by each current balancing main control circuit to obtain the bus average current, and send the bus average current to each current balancing main control circuit, so that each current balancing main control circuit uses the difference between the bus average current and each power supply output current to obtain the current balancing output voltage, and each current balancing output voltage is superimposed with the power supply output voltage provided by each power supply circuit to the load circuit, and then output to the load circuit.

[0006] Among them, the current sharing output voltage is positively correlated with the difference.

[0007] When the current sharing main control circuit determines that the bus average current is within the first threshold range, or the difference is within the second threshold range, the current sharing output voltage is set to 0.

[0008] Among them, the current sharing main control circuit includes a signal processing sub-circuit and a current sharing modulation sub-circuit. The signal processing sub-circuit is coupled to the current sharing modulation sub-circuit and is used to couple with the power supply circuit. The signal processing sub-circuit receives the power supply output current sent by the power supply circuit, and adjusts the power supply output current to a mapping calibration voltage and sends it to the current sharing modulation sub-circuit, so that the current sharing modulation sub-circuit adjusts the mapping calibration voltage to a current sharing modulation voltage; the signal processing sub-circuit receives the bus average current sent by the current sharing bus, and uses the difference between the bus average current and the currently received power supply output current to obtain the current sharing output voltage, and after superimposing the current sharing output voltage with the power supply output voltage, outputs it to the load circuit.

[0009] Among them, the current sharing main control circuit also includes a signal modulation sub-circuit, which is coupled between the signal processing sub-circuit and the current sharing modulation sub-circuit. The signal processing sub-circuit uses the power supply output current to obtain the modulation characteristic parameters, and sends the modulation characteristic parameters to the signal modulation sub-circuit, so that the signal modulation sub-circuit maps the power supply output current to a set pulse width modulation signal, and uses the set pulse width modulation signal to obtain the mapping calibration voltage.

[0010] Among them, the current equalization main control circuit also includes a first sampling sub-circuit, which is coupled to the signal processing sub-circuit and used to couple with the power supply circuit. The first sampling sub-circuit is used to sample and obtain the power supply output current provided by the power supply circuit to the load circuit, and send the power supply output current to the signal processing sub-circuit.

[0011] Among them, the current sharing main control circuit also includes a second sampling sub-circuit, which is coupled between the current sharing bus and the signal processing sub-circuit. The second sampling sub-circuit is used to sample and obtain the bus average voltage on the current sharing bus, so as to use the bus average voltage to obtain the bus average current, and send the bus average current to the signal processing sub-circuit.

[0012] Among them, the current balancing main control circuit also includes an on-off control subcircuit, which is coupled between the current balancing modulation subcircuit and the current balancing bus. When the signal processing subcircuit detects a fault in the power supply circuit, it sends a shutdown signal to the on-off control subcircuit to trigger the on-off control subcircuit to disconnect the connection between the current balancing modulation subcircuit and the current balancing bus.

[0013] Among them, the current equalization main control circuit also includes a drive control subcircuit, which is coupled to the signal processing subcircuit and is used to couple with the power supply circuit. The drive control subcircuit receives the control signal sent by the signal processing subcircuit, and sends a drive signal to the power supply circuit in response to the control signal, so as to trigger the power supply circuit to stop or output the power supply output current and power supply output voltage to the load circuit.

[0014] Among them, the current sharing modulation subcircuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and an amplifier; wherein the first end of the first resistor is coupled to the signal processing subcircuit, the second end of the first resistor is coupled to the first end of the second resistor, the first end of the first capacitor and the first end of the amplifier, the second end of the second resistor, the second end of the second capacitor, the second end of the third resistor, the second end of the second capacitor, the fourth end of the amplifier, the second end of the sixth resistor, the second end of the fourth capacitor and grounded, the first end of the third resistor is coupled to the first end of the second capacitor, the second end of the amplifier, the first end of the third capacitor and the first end of the fourth resistor, the third end of the amplifier is coupled to the setting level providing end, the second end of the third capacitor is coupled to the second end of the fourth resistor, the fifth end of the amplifier and the first end of the fifth resistor, the second end of the fifth resistor is coupled to the first end of the sixth resistor, the first end of the fourth capacitor and the current sharing bus.

[0015] To solve the above technical problems, another technical solution adopted in the present application is: to provide a power parallel control method, which includes: obtaining the power supply output current provided by each external power supply circuit to the external load circuit; adjusting each power supply output current to a current sharing modulation voltage; using each current sharing modulation voltage to obtain the bus average current; using the difference between the bus average current and each power supply output current to obtain the current sharing output voltage; and superimposing each current sharing output voltage with the power supply output voltage provided by each power supply circuit to the load circuit, and outputting them to the load circuit.

[0016] Among them, the step of using the difference between the bus average current and each power supply output current to obtain the current-sharing output voltage includes: using a first setting function to calculate the difference between the bus average current and each power supply output current to obtain the current-sharing loop control parameter; multiplying each current-sharing loop control parameter by each difference to obtain the current-sharing output voltage.

[0017] Among them, the step of adjusting each power supply output current to a current-sharing modulation voltage includes: using a second setting function to calculate each power supply output current to obtain a modulation characteristic parameter; using each modulation characteristic parameter to map each power supply output current to a set pulse width modulation signal; using each set pulse width modulation signal to obtain a mapping calibration voltage; and adjusting the mapping calibration voltage to a current-sharing modulation voltage.

[0018] Among them, after the step of obtaining the current-sharing output voltage using the difference between the bus average current and each power supply output current, it also includes: detecting whether the bus average current is within a first threshold range; if the bus average current is within the first threshold range, setting each current-sharing output voltage to 0.

[0019] Among them, after the step of obtaining the current-sharing output voltage by using the difference between the bus average current and each power supply output current, it also includes: detecting whether each difference is within the second threshold range; if there is a difference within the second threshold range, setting the current-sharing output voltage corresponding to the difference within the second threshold range to 0.

[0020] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a power management circuit, wherein the power management circuit includes at least two power supply circuits and a power parallel control circuit, the power parallel control circuit includes at least two current equalizing main control circuits, each current equalizing main control circuit is coupled to a power supply circuit; wherein the power parallel control circuit is a power parallel control circuit as described in any of the above items.

[0021] To solve the above technical problems, another technical solution adopted in the present application is: to provide an electronic device, wherein the electronic device includes a coupled shell and a signal processing circuit; wherein the signal processing circuit is a power parallel control circuit as described in any of the above items, or a power management circuit as described above.

[0022] The beneficial effect of the present application is as follows: Different from the prior art, at least two current sharing main control circuits in the power supply parallel control circuit provided by the present application are respectively used to couple with the power supply circuit to obtain the power supply output current provided by each power supply circuit to the external load circuit, and adjust each power supply output current to a current sharing modulation voltage to send it to the current sharing bus, and use the current sharing bus to obtain the bus average current, so as to use the difference between the bus average current and each power supply output current to obtain the current sharing output voltage, and each current sharing output voltage is superimposed with the power supply output voltage provided by each power supply circuit to the load circuit, and then output to the load circuit, so that the output error of each power supply circuit can be accurately adjusted in response to the real-time feedback to ensure the current sharing of the power supply parallel; and by superimposing the output error of each power supply circuit to the corresponding power supply output voltage, the high precision of the output voltage of each power supply circuit is also effectively guaranteed, so that while meeting the power supply parallel current sharing index, it can also effectively meet the customer's high precision requirements for the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0024] Figure 1 It is a structural schematic diagram of the first embodiment of the power parallel control circuit of the present application;

[0025] Figure 2 It is a structural schematic diagram of a second embodiment of the power parallel control circuit of the present application;

[0026] Figure 3 yes Figure 2 A schematic diagram of the framework of the signal processing logic of the parallel control circuit of the power supply;

[0027] Figure 4 is a schematic structural diagram of a third embodiment of the voltage holding circuit of the present application;

[0028] Figure 5 yes Figure 4 A schematic diagram of the structure of a specific embodiment of a power supply circuit;

[0029] Figure 6 It is a flow chart of the first implementation mode of the power parallel control method of the present application;

[0030] Figure 7 yes Figure 6 S42 is a flow chart of an embodiment;

[0031] Figure 8 yes Figure 6 S44 is a flow chart of an embodiment;

[0032] Fig. 9 It is a flow chart of the second implementation mode of the power parallel control method of the present application;

[0033] Fig.10 It is a flow chart of the third implementation mode of the power parallel control method of the present application;

[0034] Fig.11 It is a schematic diagram of a framework of an implementation method of a power management circuit of the present application;

[0035] Fig.12 It is a schematic diagram of the framework of an implementation scheme of the electronic device of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the implementation mode of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0038] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0039] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0040] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of the first embodiment of the power parallel control circuit of the present application. In this embodiment, the power parallel control circuit 10 specifically includes: at least two current sharing main control circuits 11 and a current sharing bus 12.

[0041] Among them, a power parallel control circuit 10 provided in the present application is specifically used in the case where two or more independent power circuits 101 are connected in a specific manner to jointly power a load circuit 102, so as to perform parallel control and adjustment on the power supply output of each power circuit 101.

[0042] It is worth noting that the power supply circuit 101 can be understood as a power supply regulating circuit that converts and regulates power supply from a power grid to obtain power output capability, or it can be a power supply regulating circuit that is itself configured with a power supply.

[0043] In addition, the term "coupled" herein refers to any direct and indirect connection means. Therefore, if the first circuit is described as being coupled to the second circuit, it means that the first circuit can be directly connected to the second circuit through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or can be indirectly connected to the second circuit through other circuits or connection means.

[0044] Among them, the current balancing main control circuit 11 is mainly responsible for monitoring and controlling the current distribution between multiple power supply circuits 101 working in parallel, ensuring that the current provided by each power supply circuit 101 is balanced, and avoiding problems such as local overheating, reduced efficiency, shortened life and even equipment damage caused by current imbalance between the power supply circuits 101.

[0045] The current sharing bus 12 can be understood as a central node, coupled with each independent current sharing main control circuit 11, to play the role of information exchange and signal integration. Under this architecture, a closed-loop feedback network is formed between each current sharing main control circuit 11 and the current sharing bus 12, which work together to achieve more accurate and dynamic current balancing control.

[0046] Specifically, two or more independent power supply circuits 101 are connected in parallel and connected to a load circuit 102. The power parallel control circuit 10 is configured with a current sharing main control circuit 11 corresponding to each power supply circuit 101, and each current sharing main control circuit 11 is used to couple with a power supply circuit 101 to obtain the power supply output current supplied by each power supply circuit 101 to the external load circuit 102 in real time. To facilitate subsequent parallel control, each current sharing main control circuit 11 adjusts each power supply output current to a current sharing modulation voltage.

[0047] Furthermore, the current sharing bus 12 receives the current sharing modulation voltage sent by each current sharing main control circuit 11, so that each current sharing modulation voltage is integrated on the same current sharing bus 12 to obtain a bus average current, and the bus average current is fed back to each current sharing main control circuit 11.

[0048] This bus average current actually represents the balanced current value that all power circuits 101 should maintain together under ideal conditions. Each current-sharing main control circuit 11 compares the received bus average current with the power supply output current of the power circuit 101 currently coupled thereto to calculate the difference between each power supply output current and the bus average current, and uses the difference to obtain a current-sharing output voltage based on a preset rule. The power supply output voltage will be used to adjust the output characteristics of the corresponding power circuit 101 so that its current approaches the bus average current to achieve overall current balance.

[0049] Specifically, each power supply circuit 101 superimposes its original power supply output voltage with each current-sharing output voltage currently obtained to form a new output voltage, which is provided to the external load circuit 102 respectively, so that through the joint action of all power supply circuits 101, the total current received by the load circuit 102 is kept evenly distributed among the power supply circuits 101, that is, to ensure that the power supply output currents of all parallel power supply circuits 101 tend to be consistent.

[0050] The above scheme effectively ensures the current sharing of the power supply in parallel by enabling each current sharing main control circuit 11 to perform precise adjustments in response to the output error fed back in real time by each power supply circuit 101 coupled thereto; and by superimposing the output error of each power supply circuit 101 to the corresponding power supply output voltage, it also effectively ensures the high accuracy of the output voltage of each power supply circuit 101, thereby meeting the current sharing index of the power supply in parallel while also effectively meeting the customer's high accuracy requirements for the output voltage.

[0051] In one embodiment, the current-sharing output voltage is positively correlated with the difference between the power supply output current calculated by the current-sharing main control circuit 11 and the bus average current. That is, the larger the difference, the larger the current-sharing output voltage, and the smaller the difference, the smaller the current-sharing output voltage, so that when the current-sharing output voltage is superimposed on the corresponding power supply output voltage, a larger compensation can be made for the power supply output voltage with a larger output error, and a smaller compensation can be made for the power supply output voltage with a smaller output error, so as to ensure that the power supply output currents of all parallel power supply circuits 101 tend to be consistent.

[0052] For ease of understanding, taking the example of power supply circuit 1, power supply circuit 2, ..., power supply circuit n (n is a positive integer not less than 2) connected in parallel to jointly supply power to load circuit 102, the power supply parallel control circuit 10 is correspondingly configured with current sharing main control circuit 1, current sharing main control circuit 2, ..., current sharing main control circuit n and current sharing bus 12 to realize power supply parallel control. The current sharing main control circuit 1, current sharing main control circuit 2, ..., current sharing main control circuit n are specifically connected to power supply circuit 1, power supply circuit 2, ..., power supply circuit n, respectively, and are all connected to the current sharing bus 12.

[0053] Among them, under ideal conditions, power supply circuit 1, power supply circuit 2, ..., power supply circuit n will respectively have the same power supply output current and power supply output voltage, but in the actual power supply parallel power supply process, there will inevitably be a power supply imbalance, that is, there are different differences between each power supply output current and the bus average current obtained by integrating the current sharing bus 12, and some of the differences will be positive and the other part will be negative. After the differences are superimposed on the corresponding power supply output voltages, the power supply output voltage with a positive error can be reversely compensated, and the power supply output voltage with a negative error can be positively compensated, so as to ultimately ensure that the power supply output currents of all parallel power supply circuits 101 tend to be consistent.

[0054] In one embodiment, when each current balancing main control circuit 11 determines that the currently acquired bus average current is within the first threshold range, the current balancing output voltage is set to 0, that is, each current balancing main control circuit 11 does not superimpose the power supply output voltage provided by each power supply circuit 101 to the load circuit 102.

[0055] Among them, the first threshold range can specifically be ±5% of the rated output current of each power supply circuit 101, that is, when each current sharing main control circuit 11 determines that the currently obtained bus average current is less than +5% of the rated output current and greater than -5% of the rated output current, the current current sharing output voltage is set to 0, and no additional voltage regulation action is used to further adjust the power supply output current of each power supply circuit 101, thereby effectively avoiding the problem of high no-load output voltage drift.

[0056] In one embodiment, when there is a current balancing main control circuit 11 that determines that the difference between the currently obtained bus average current and the power supply output current sent by the power supply circuit 101 is within the second threshold range, the current balancing output voltage is set to 0. That is, when there are at least some current balancing main control circuits 11 that determine that the currently obtained difference is within the second threshold range, the power supply output voltage provided by the corresponding power supply circuit 101 to the load circuit 102 is not superimposed or adjusted.

[0057] Optionally, the second threshold range may be any reasonable threshold range such as greater than -0.3A and less than 0.3A, or greater than -0.2A and less than 0.2A, which is determined by an actual control scenario and is not limited in this application.

[0058] It is understandable that if the difference between the current power supply output current and the average bus current is small, that is, the difference is within the second threshold range, this indicates that the current difference between the power supply circuits 101 is already very weak, and continuing to apply the current-sharing output voltage adjustment may cause unnecessary fluctuations or control errors. Therefore, in this case, setting the current-sharing output voltage to zero helps avoid over-regulation, maintain system stability, and ensure that the power supply circuit 101 can continue to provide high-quality, high-precision, and stable power output to the load circuit 102. At the same time, this approach also helps to reduce system losses and improve energy efficiency.

[0059] See also Figure 2 , Figure 2 The power parallel control circuit in this embodiment is different from the first embodiment of the power parallel control circuit provided in this application in that the current sharing main control circuit 21 in the power parallel control circuit 20 further includes a signal processing subcircuit 211 and a current sharing modulation subcircuit 212.

[0060] Specifically, the signal processing sub-circuit 211 is coupled to the current sharing modulation sub-circuit 212 and is used to couple with the power supply circuit 101 to jointly form a current monitoring and regulation system for each power supply circuit 101 .

[0061] The signal processing sub-circuit 211 receives the power supply output current sent by the power supply circuit 101, and adjusts the power supply output current to a mapping calibration voltage and sends it to the current sharing modulation sub-circuit 212, so that the current sharing modulation sub-circuit 212 adjusts the mapping calibration voltage to the current sharing modulation voltage;

[0062] The specific working process is as follows: the signal processing subcircuit 211 collects and processes the received power supply output current of the power supply circuit 101 in real time, and if necessary, performs filtering, analog-to-digital conversion, signal conversion and other steps to convert the original current signal into an electrical signal that is convenient for subsequent precise control, that is, to adjust the power supply output current to a mapping calibration voltage to be sent to the current equalization modulation subcircuit 212.

[0063] The current balancing modulation sub-circuit 212 is used to adjust the mapped calibration voltage to the current balancing modulation voltage, that is, each current balancing modulation sub-circuit 212 is used to divide, filter and amplify the mapped calibration voltage to obtain each current balancing modulation voltage, and then use the current balancing bus 22 to integrate each current balancing modulation voltage to obtain the bus average current.

[0064] The signal processing subcircuit 211 is also used to obtain the bus average current obtained by integrating each current sharing modulation voltage of the current sharing bus 22, so as to compare the currently received power supply output current, that is, the current output by the single power supply circuit 101 currently working and the bus average current obtained from the current sharing bus 22, and calculate the difference between the two, so as to generate a corresponding current sharing output voltage signal based on the above difference.

[0065] Among them, the function of the current-sharing output voltage signal is to compensate for the current imbalance, so that the output current of all parallel power modules is more uniform. The signal processing subcircuit 211 specifically superimposes the current-sharing output voltage on the original power supply output voltage to form a new total output voltage, and then outputs this regulated voltage to the load circuit 102. Through such a mechanism, the power supply parallel control circuit 20 can dynamically adjust the output of each power supply circuit 101 according to the actual current distribution, thereby achieving accurate and efficient current-sharing control, ensuring that the load circuit 102 is stably powered, and avoiding the risk of overheating or damage to the power supply circuit 101 due to uneven current distribution.

[0066] Optionally, the signal processing sub-circuit 211 may specifically include a DSP (Digital Signal Process), an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, a discrete gate or transistor logic device, a discrete hardware, or any other reasonable circuit unit with a signal processing function, and the present application does not limit this.

[0067] It is worth noting that the signal processing sub-circuit 211 can be specifically understood as a digital control circuit, and the current sharing modulation sub-circuit 212 can be understood as an analog circuit, so that the power parallel control circuit 20 can adopt a combination of analog and digital methods to implement the power parallel control method, and specifically use the analog circuit to obtain the average parallel current, that is, the bus average current, and use the digital control circuit to implement the current sharing loop control, and specifically can adopt variable parameter P (Proportional) control.

[0068] It should be pointed out that the current sharing of parallel machines realized by full analog circuits is limited by the inflexibility of analog devices, and usually has problems such as high no-load output voltage drift. The current sharing realized by full digital control inevitably needs to adopt RS485 (a standard jointly issued by the Telecommunications Industry Association and the Electronic Industry Alliance) bus, I2C (Inter Integrated Circuit) bus or CAN (Controller Area Network) bus communication technology. Therefore, it is necessary to add a communication protocol between power supplies, calculate the average current of the parallel system through communication data to realize current sharing control, which increases the complexity of the software and puts higher requirements on the reliability and real-time performance of communication.

[0069] By adopting a combination of analog and digital methods to implement the power supply parallel control method, the problem of high no-load output voltage drift in the full analog circuit is effectively overcome, and the problem of full digital control requiring the addition of communication protocols between power supplies and increased software complexity is avoided. That is, the power supply parallel control circuit 20 effectively takes into account the requirements of high precision and equal current of the output voltage of the power supply circuit 101, and can also use the flexibility of the digital current equalizing loop to solve the problem of high no-load output voltage drift in the analog circuit parallel solution.

[0070] Please continue reading Figure 3 , Figure 3 yes Figure 2 Schematic diagram of the signal processing logic of the power parallel control circuit.

[0071] In a specific embodiment, the signal processing subcircuit 211 specifically adopts the digital current sharing loop variable parameter P control, firstly converts the currently obtained bus average current The power supply output current of the power supply circuit 101 is obtained by Subtract to get the difference , and then use the first setting function to calculate the average bus current With the supply output current The difference between Calculate to obtain the current balancing loop control parameter P, and compare each current balancing loop control parameter P with the difference Multiply to get the current-sharing output voltage .

[0072] Among them, the first setting function specifically corresponds to ; , is a variable parameter coefficient, which can be set and adjusted according to the actual application scenario. , for superimposing on the power supply output voltage of the power supply circuit 101 , to get , and The regulated output voltage is provided to the load circuit 102 to realize current sharing control. By making full use of the fast sampling characteristic of the current sharing bus 22 to quickly reflect the average current of each power supply, the current sharing loop variable parameter P control can achieve fast adjustment.

[0073] It is worth mentioning that Figure 3 The figure shows the signal processing logic of one of the signal processing sub-circuits 211 for realizing parallel control, and the other signal processing sub-circuits 211 are similar, so that at least two corresponding signal processing sub-circuits 211 can obtain at least two corresponding signals through independent signal processing. , can be synchronously provided to the load circuit 102.

[0074] In the actual power supply parallel power supply process, the power supply output current of the power supply circuit 1 is The output current of power supply circuit 2 is 49A. is 51A, and the average bus current Taking 50A as an example, the difference will be is 1A, the difference is -1A, and then the corresponding calculations are obtained and will be a positive value, a negative value, and the power supply output current Corresponding power supply output voltage The positive compensation will be superimposed, and the power supply output current Corresponding power supply output voltage Negative compensation superposition will be obtained, thereby ensuring that the power supply output currents of all parallel power supply circuits 101 tend to be consistent.

[0075] In a specific embodiment, the signal processing subcircuit 211 uses a second setting function to calculate the power supply output current to obtain a modulation characteristic parameter, and uses the modulation characteristic parameter to map each power supply output current to a set pulse width modulation signal, and uses each set pulse width modulation signal to obtain a mapping calibration voltage, so as to adjust the mapping calibration voltage to a current equalizing modulation voltage.

[0076] The modulation characteristic parameter is specifically to set the signal frequency of the pulse width modulation signal and / or the duty cycle , the second setting function specifically corresponds to ; is the power supply output current, is the conversion factor. It is related to the voltage range and duty cycle range of the current-sharing bus 22. The voltage range of the current-sharing bus 22 is determined by the product specifications, and the duty cycle range is generally not more than 80%; , The calibration coefficient can be set and adjusted according to the actual application scenario, so that the voltage of the current-sharing bus 22 can be conveniently calibrated through mapping, thereby meeting the requirements of some customers that power circuits 101 from different manufacturers can be mixed and connected using the current-sharing bus 22.

[0077] In one embodiment, the current balancing main control circuit 21 specifically also includes a signal modulation sub-circuit 213, which is coupled between the signal processing sub-circuit 211 and the current balancing modulation sub-circuit 212 to perform data conversion and transmission functions, and cooperate with the signal processing sub-circuit 211 and the current balancing modulation sub-circuit 212 to achieve precise current control and power regulation.

[0078] Specifically, the signal processing sub-circuit 211 extracts modulation characteristic parameters reflecting the state of the power supply output current through specific algorithm analysis and calculation, and transmits the modulation characteristic parameters to the signal modulation sub-circuit 213 in real time.

[0079] Among them, the modulation characteristic parameter can specifically be a duty cycle and / or a signal frequency, so that after the signal modulation sub-circuit 213 receives the modulation characteristic parameter, it can map the power supply output current into a set pulse width modulation signal with a specific frequency and an adjustable duty cycle according to the modulation characteristic parameter, and then use the set pulse width modulation signal to obtain a mapping calibration voltage, for example, multiplying the amplitude of the set pulse width modulation signal by its duty cycle to obtain a mapping calibration voltage.

[0080] It is understandable that the modulation characteristic parameter can be specifically determined by the signal processing subcircuit 211 using the second setting function Calculated duty cycle , and set the signal frequency to any one of 80K-120K, such as 100K, and then map it to a signal frequency of 100K and a duty cycle of The set pulse width modulation signal is then used to obtain the mapping calibration voltage , To set the amplitude of the pulse width modulation signal.

[0081] In one embodiment, the current balancing main control circuit 21 specifically also includes a first sampling sub-circuit 214, which is coupled to the signal processing sub-circuit 211 and is used to couple with the power supply circuit 101 to ensure that the working status of the power supply circuit 101 can be monitored in real time, and directly or indirectly sample and obtain the power supply output current supplied by the power supply circuit 101 to the load circuit 102. It is usually implemented by using components such as current transformers, Hall effect sensors, and resistor shunts to convert the changing current signal into a processable voltage or digital signal, and then send the sampled power supply output current to the signal processing sub-circuit 211 in real time or at a certain period to serve as basic data for subsequent processing and analysis.

[0082] In one embodiment, the current balancing main control circuit 21 specifically also includes a second sampling sub-circuit 215, which is coupled between the current balancing bus 22 and the signal processing sub-circuit 211, so as to be able to sense and read the voltage condition on the current balancing bus 22 in real time, and collect the average voltage value on the current balancing bus 22 through voltage sampling elements, such as voltage dividing resistors, voltage transformers, etc., so as to calculate the bus average current based on Ohm's law and other possible relationships between voltage and current, such as through known resistance values ​​or known internal characteristics of the power module.

[0083] The bus average current represents the average current of all parallel power supply circuits 101, and the second sampling subcircuit 215 is also used to send the bus average current to the signal processing subcircuit 211, or convert the bus average current into a corresponding digital signal and send it to the signal processing subcircuit 211.

[0084] In one embodiment, the current balancing main control circuit 21 also includes an on-off control subcircuit 216, which is coupled between the current balancing modulation subcircuit 212 and the current balancing bus 22 to serve as an important safety protection link. When an abnormality or failure of the power supply circuit 101 is detected, action is taken to protect the entire system.

[0085] Specifically, the signal processing subcircuit 211 continuously monitors the state of the power supply circuit 101, and when a fault is detected, such as an abnormal condition such as overload, short circuit, overtemperature, abnormal voltage, etc., a shutdown signal is sent to the on-off control subcircuit 216 to cut off the communication or electrical connection between the current equalization modulation subcircuit 212 and the current equalization bus 22, thereby avoiding potential safety risks and equipment damage. Through such a design, the faulty circuit part can be isolated at the first time to ensure the normal operation of the remaining parts, while also ensuring the stability and safety of the entire power supply system, and effectively avoiding the adverse effects of the current equalization bus 22 obtaining the average bus current.

[0086] In one embodiment, the current equalizing main control circuit 21 specifically also includes a drive control subcircuit 217, which is coupled to the signal processing subcircuit 211 and is used to couple with the power supply circuit 101 to receive and analyze the control signal sent by the signal processing subcircuit 211, and to perform real-time control of the operating status of the power supply circuit 101.

[0087] Specifically, the signal processing subcircuit 211 is also used to make a comprehensive judgment based on the working state of the power supply circuit 101, such as the power supply output current, power supply output voltage, bus average current, etc., to generate a corresponding control signal, and send the control signal to the drive control subcircuit 217, so that the drive control subcircuit 217 generates a corresponding drive signal based on the control signal. The drive signal generally includes a variety of control instructions such as start, stop, and adjust the amplitude. When the drive signal is sent to the power supply circuit 101, it can control the on and off states of each switch element in the power supply circuit 101 to achieve precise control of the output characteristics of the power supply circuit 101. According to the instructions of the control signal, the drive control subcircuit 217 can stop the power supply circuit 101 from supplying power to the load circuit 102, or make the power supply circuit 101 continue to supply power to the load circuit 102, or adjust the output power supply output current and power supply output voltage to meet the load demand and system optimization goals, such as realizing current balancing, voltage stabilization, overload protection and other functions.

[0088] Similarly, taking the example that there are power supply circuits 1, 2, ..., and n connected in parallel to supply power to the load circuit 102 together, the power supply parallel control circuit 20 is correspondingly configured with a signal processing subcircuit 1, a signal processing subcircuit 2, ..., and a signal processing subcircuit n, a current sharing modulation subcircuit 1, a current sharing modulation subcircuit 2, ..., and a current sharing modulation subcircuit n, a signal modulation subcircuit 1, a signal modulation subcircuit 2, ..., and a signal modulation subcircuit n, a first sampling subcircuit 1, a first sampling subcircuit 2, ..., and a first sampling subcircuit n, a second sampling subcircuit 1, a second sampling subcircuit 2, ..., and a second sampling subcircuit n, an on-off control subcircuit 1, an on-off control subcircuit 2, ..., and an on-off control subcircuit n, a drive control subcircuit 1, a drive control subcircuit 2, ..., and a drive control subcircuit n, and the corresponding connections are as follows: Figure 2 As shown, no further description is given here.

[0089] Furthermore, if Figure 3 As shown, the signal processing logic of the signal processing sub-circuit 1 is used as an example for explanation. The signal processing sub-circuit 1 uses the drive control sub-circuit 1 to control the power supply circuit 1 to output the power supply current Provided to the load circuit 102, or shut down the power supply output of the power supply circuit 1, and use the current sharing modulation sub-circuit 1 to obtain the current sharing bus voltage , to make the current sharing bus voltage Output to the current sharing bus 22, so as to use the current sharing bus to obtain the current sharing bus voltages of the current sharing modulation sub-circuit 1, the current sharing modulation sub-circuit 2, ..., the current sharing modulation sub-circuit n respectively After integration, the average bus current is obtained .

[0090] The signal processing subcircuit 1 further uses the second sampling subcircuit 1 to sample and obtain the average bus current , with the power supply output current Difference , which is used to realize the digital current sharing loop. The current sharing loop adopts variable parameter proportional control (P control). P control has no error accumulation and can take into account the output voltage accuracy, dynamics and current sharing. Finally, the output of the current sharing loop, that is, the current sharing output voltage Superimposed on the power supply output voltage of power supply circuit 1 The above two components serve as the given value of the current sharing loop, that is, to adjust the output voltage To jointly adjust the voltage output to the load circuit 102 to achieve current sharing.

[0091] The signal processing logics of the signal processing sub-circuit 2, ..., and the signal processing sub-circuit n are the same as above, and are not described in detail here.

[0092] See also Figure 4 , Figure 4 It is a structural diagram of the third embodiment of the power parallel control circuit of the present application. The difference between the power parallel control circuit in this embodiment and the first embodiment of the power parallel control circuit provided in this application is that the current sharing modulation subcircuit 312 of each current sharing main control circuit 31 in the power parallel control circuit 30 specifically further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and an amplifier FD.

[0093] Among them, the first end of the first resistor R1 is coupled to the signal processing sub-circuit 311, the second end of the first resistor R1 is coupled to the first end of the second resistor R2, the first end of the first capacitor C1 and the first end of the amplifier FD, the second end of the second resistor R2, the second end of the second capacitor C2, the second end of the third resistor R3, the second end of the second capacitor C2, the fourth end of the amplifier FD, the second end of the sixth resistor R6, the second end of the fourth capacitor C4 and grounded, the first end of the third resistor R3 is coupled to the first end of the second capacitor C2, the second end of the amplifier FD, the first end of the third capacitor C3 and the first end of the fourth resistor R4, the third end of the amplifier FD is coupled to the setting level providing end, the second end of the third capacitor C3 is coupled to the second end of the fourth resistor R4, the fifth end of the amplifier FD and the first end of the fifth resistor R5, the second end of the fifth resistor R5 is coupled to the first end of the sixth resistor R6, the first end of the fourth capacitor C4 and the current sharing bus 32.

[0094] Furthermore, in one embodiment, the current balancing main control circuit 31 specifically includes an on-off control subcircuit 316 and a second sampling subcircuit 315 , the on-off control subcircuit 316 includes an isolation switch S, and the second sampling subcircuit 315 includes a seventh resistor R7 and an eighth resistor R8 .

[0095] Among them, the first end of the isolation switch S is coupled to the second end of the fifth resistor R5, the first end of the sixth resistor R6 and the first end of the fourth capacitor C4, the second end of the isolation switch S is coupled to the first end of the seventh resistor R7, and is coupled to the current sharing bus 32, the second end of the seventh resistor R7 is coupled to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is coupled to the second end of the second resistor R2, the second end of the second capacitor C2, the second end of the third resistor R3, the second end of the second capacitor C2, the fourth end of the amplifier FD, the second end of the sixth resistor R6, the second end of the fourth capacitor C4 and grounded.

[0096] It is worth mentioning that Figure 4 Only a detailed structural diagram of a current balancing main control circuit 31 in the power parallel control circuit 30 is shown, and the detailed structural diagrams of other current balancing main control circuits 31 and corresponding signal processing logics are similar, which will not be repeated here one by one.

[0097] It is understandable that the signal processing sub-circuit 311 specifically uses the signal modulation sub-circuit 313 to convert the current power supply output current of the power supply circuit 101 into Mapped to frequency 100k, duty cycle Adjustable pulse width modulation signal, the duty cycle of the pulse width modulation signal , and then get the mapping calibration voltage .

[0098] This maps the calibration voltage Then, the voltage is divided and filtered by the first resistor R1, the second resistor R2, and the first capacitor C1 in the current-sharing modulation subcircuit 312 to become a DC quantity, and then outputted by the amplifier FD as: .then After the voltage is divided by the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 and the isolation switch S outputs .

[0099] When a fault occurs in the power circuit 101 , in order not to affect the effective bus average current obtained by the current sharing bus 32 , the isolating switch S needs to be disconnected to isolate the current sharing modulation subcircuit 312 corresponding to the faulty power circuit 101 from the current sharing bus 32 .

[0100] Here, the current sharing main control circuit 31 is regarded as a voltage source for analysis. The current sharing main control circuit 31 is consistent for each power supply circuit 101. Assume: ,

[0101] For a single current sharing main control circuit 31, the voltage of the current sharing bus 32 is: ;

[0102] When n current-sharing main control circuits 31 are connected in parallel, the voltage of the current-sharing bus 32 is: ;

[0103] When current sharing is achieved: , that is, the voltage of the current-sharing bus 32:

[0104]

[0105] From the above expression, it can be seen that the voltage of the current-sharing bus 32 When current sharing is achieved in parallel, the expression is the same as that of a single current sharing main control circuit 31. For a single current sharing main control circuit 31, it represents the output current. For n current sharing main control circuits 31 connected in parallel, it represents the output average current.

[0106] Finally, the voltage of the current sharing bus 32 The seventh resistor R7 and the eighth resistor R8 divide the voltage and feed it back to the signal processing sub-circuit 311 to obtain the average bus current . Then with the local current Difference , which is used to realize the digital current sharing loop variable parameter P control, the current sharing loop control parameter .

[0107] The current-sharing output voltage is , to be superimposed on the power supply output voltage of the power supply circuit 101 Get , and The regulated output voltage is provided to the load circuit 102 to realize current sharing control. By making full use of the fast sampling characteristic of the current sharing bus 32 to quickly reflect the average current of each power supply, the current sharing loop variable parameter P control can achieve fast adjustment.

[0108] In order to make full use of the fast sampling of the current sharing bus 32 and quickly reflect the average current of each power circuit 101, the current sharing loop can be adjusted quickly. The size of the design current balancing loop control parameter P, the difference The larger it is, the larger the current balancing loop control parameter P is, so as to meet the current balancing degree and output dynamic indicators.

[0109] In addition, in order to reduce the influence of the current-sharing loop on the output voltage accuracy when the single power supply circuit 101 is working, when the difference In ± ( The current sharing loop is not adjusted, that is, the current sharing output voltage is set to 0, and the power supply output voltage of the power supply circuit 101 is not adjusted. To solve the problem of high no-load output voltage drift, the average bus current Less than ( The current sharing loop is not adjusted, that is, the current sharing output voltage is set to 0, and the power supply output voltage of the power supply circuit 101 is not adjusted. Perform voltage superposition regulation.

[0110] It can be understood that the signal processing sub-circuit 311 can be specifically understood as a digital control circuit, and the current equalizing modulation sub-circuit 312 is an analog circuit, which adopts a combination of analog and digital methods to implement the power supply parallel control method, effectively overcoming the problems of high no-load output voltage drift in the full analog circuit, and avoiding the need for full digital control to increase the communication protocol between power supplies and increase software complexity. That is, the power supply parallel control circuit 30 effectively takes into account the high precision and current equalization requirements of the output voltage of the power supply circuit 101, and can also use the flexibility of the digital current equalizing loop to solve the problems of high no-load output voltage drift in the analog circuit parallel scheme, and has strong practicality and operability.

[0111] It can be understood that, in this embodiment, the signal processing subcircuit 311, the signal modulation subcircuit 313, the first sampling subcircuit 314, the drive control subcircuit 317 and the current sharing bus 32 are respectively the same as the signal processing subcircuit 311, the signal modulation subcircuit 313, the first sampling subcircuit 314, the drive control subcircuit 317 and the current sharing bus 32. For details, please refer to Figure 2And the related text content will not be repeated here.

[0112] Please continue reading Figure 5 , Figure 5 yes Figure 4 A schematic structural diagram of a specific embodiment of the power supply circuit 101.

[0113] In one embodiment, the power supply circuit 101 specifically includes a voltage-stabilizing capacitor C, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8, a resonant inductor Lr, a resonant capacitor Cr, an isolation transformer Is, and an output capacitor Cf.

[0114] Among them, the first end of the voltage-stabilizing capacitor C is coupled to the first end of the external power supply, the second end of the first switch tube Q1, and the second end of the second switch tube Q2; the second end of the voltage-stabilizing capacitor C is coupled to the second end of the external power supply, the first end of the third switch tube Q3, and the first end of the fourth switch tube Q4; the first end of the first switch tube Q1 is coupled to the second end of the third switch tube Q3 and the first end of the resonant capacitor Cr; the first end of the second switch tube Q2 is coupled to the second end of the fourth switch tube Q4 and the first end of the resonant inductor Lr; the second end of the resonant inductor Lr is coupled to the first end of the isolation transformer Is; the second end of the resonant capacitor Cr is coupled to the second end of the isolation transformer Is; the third end of the isolation transformer Is is coupled to the first end of the fifth switch tube Q5. The fourth end of the isolation transformer Is is coupled to the first end of the sixth switch tube Q6 and the second end of the eighth switch tube Q8. The second end of the fifth switch tube Q5 is coupled to the second end of the sixth switch tube Q6, the first end of the output capacitor Cf and the first end of the load circuit 102. The first end of the seventh switch tube Q7 is coupled to the first end of the eighth switch tube Q8, the second end of the output capacitor Cf and the second end of the load circuit 102. The third end of each of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7 and the eighth switch tube Q8 is coupled to the drive control sub-circuit 317.

[0115] It is understandable that the power supply circuit 101 is used to receive a DC input from an external power supply. , so as to utilize the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eighth switch tube Q8 controlled by the signal processing sub-circuit 311 and the drive control sub-circuit 317 to input the DC Corresponding voltage conversion is performed to obtain a power supply output voltage, which is then output to the load circuit 102 .

[0116] Optionally, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eighth switch tube Q8 can specifically be a MOS (Metal Oxide Semiconductor Field Effect Transistor) tube, a triode, a thin film transistor or a field effect transistor or any other reasonable switch tube, and the present application does not limit this.

[0117] In other embodiments, the power supply circuit 101 may specifically be a voltage conversion circuit with its own power supply or any other reasonable circuit form, or may only include a DC voltage source, which is not limited in the present application.

[0118] This application also specifically adopts a power parallel control method, see Figure 6 , Figure 6 This is a flow chart of the first embodiment of the power parallel control method of the present application. Specifically, it may include the following steps:

[0119] S41: Obtaining the power supply output current provided by each external power supply circuit to the external load circuit.

[0120] It is understandable that the power parallel control method in this embodiment is specifically a method of using a power parallel control circuit to perform parallel control and adjustment on the power supply output of each power circuit when two or more independent power circuits are connected in a specific manner to jointly supply power to a load circuit. The power parallel control circuit specifically includes at least two current sharing main control circuits and a current sharing bus, each current sharing main control circuit is used to couple with a power circuit, and both are coupled to the current sharing bus.

[0121] Specifically, each current-sharing main control circuit is used to sample and obtain the power supply output current provided to the external load circuit by each power supply circuit coupled thereto.

[0122] S42: Regulate each power supply output current to a current sharing modulation voltage.

[0123] To facilitate subsequent parallel control, each current sharing main control circuit adjusts each power supply output current to a current sharing modulation voltage.

[0124] S43: Obtain the average bus current using each current-sharing modulation voltage.

[0125] The current sharing bus receives the current sharing modulation voltage sent by each current sharing master control circuit, so that each current sharing modulation voltage is integrated on the same current sharing bus to obtain the bus average current, and the bus average current is fed back to each current sharing master control circuit.

[0126] S44: Obtain a current-sharing output voltage using a difference between the bus average current and each power supply output current.

[0127] Each current-sharing master control circuit compares the received bus average current with the power supply output current of the power supply circuit currently coupled to it to calculate the difference between each power supply output current and the bus average current, and uses the difference to obtain a current-sharing output voltage based on preset rules. The power supply output voltage will be used to adjust the output characteristics of the corresponding power supply circuit so that its current approaches the bus average current to achieve overall current balance.

[0128] S45: Each current-sharing output voltage is respectively superimposed on the power supply output voltage provided by each power supply circuit to the load circuit, and then outputted to the load circuit.

[0129] Each current sharing main control circuit uses the difference to obtain a current sharing output voltage based on a preset rule. The power supply output voltage will be used to adjust the output characteristics of the corresponding power supply circuit so that its current approaches the average bus current to achieve overall current balance.

[0130] Each power supply circuit specifically superimposes its original power supply output voltage with each currently obtained current-sharing output voltage to form a new output voltage, which is provided to the external load circuit respectively. Through the joint action of all power supply circuits, the total current received by the load circuit is kept evenly distributed among the power supply circuits, that is, to ensure that the power supply output currents of all parallel power supply circuits tend to be consistent.

[0131] See also Figure 7 , Figure 7 yes Figure 6 In one embodiment, the voltage maintaining method of the present application includes, in addition to the above S41-S44, further includes some more specific steps. Specifically, the above S42 may also include the following steps:

[0132] S421: Calculate each power supply output current using the second setting function to obtain a modulation characteristic parameter.

[0133] It is understandable that each current sharing main control circuit uses the second setting function to calculate each power supply output current to obtain the modulation characteristic parameter.

[0134] The modulation characteristic parameter may specifically be a signal frequency and / or a duty cycle of a pulse width modulation signal. , the second setting function specifically corresponds to ; is the power supply output current, is the conversion factor. It is related to the voltage range of the current-sharing bus and the duty cycle range. The voltage range of the current-sharing bus is determined by the product specifications, and the duty cycle range generally does not exceed 80%; , It is a calibration coefficient, which can be set and adjusted according to the actual application scenario, so that the current-sharing bus voltage can be calibrated through mapping, thereby meeting the requirements of some customers that power circuits of different manufacturers can be mixed and connected using the current-sharing bus.

[0135] Optionally, the signal frequency may be any one of 80K-120K, and preferably 100K, which may be set and adjusted according to the actual application scenario, and this application does not limit this.

[0136] S422: Map each power supply output current into a set pulse width modulation signal using each modulation characteristic parameter.

[0137] Each power supply output current is mapped to a modulation characteristic parameter, that is, a specific signal frequency and a duty cycle. The setting pulse width modulation signal.

[0138] S423: Obtain a mapping calibration voltage using each set pulse width modulation signal.

[0139] Using each set pulse width modulation signal to obtain the mapping calibration voltage , To set the amplitude of the pulse width modulation signal.

[0140] S424: Adjust each mapping calibration voltage to a current sharing modulation voltage.

[0141] Each mapped calibration voltage is adjusted to a current sharing modulation voltage for subsequent adjustment.

[0142] See also Figure 8 , Figure 8 yes Figure 6 In one embodiment, the voltage maintaining method of the present application includes not only the above S41-S44, but also some more specific steps. Specifically, the above S44 may also include the following steps:

[0143] S441: Using the first setting function to calculate the difference between the bus average current and each power supply output current to obtain the current sharing loop control parameter.

[0144] It is understandable that the current balancing main control circuit converts the currently acquired bus average current The current obtained by the power supply circuit is the output current of the power supply Subtract to get the difference , and then use the first setting function to calculate the average bus current With the supply output current The difference between Calculation is performed to obtain the current sharing loop control parameter P.

[0145] S442: Multiply each current sharing loop control parameter by each difference value to obtain a current sharing output voltage.

[0146] Each current balancing loop control parameter P and the difference Multiply to get the current-sharing output voltage .

[0147] See also Fig. 9 , Fig. 9 1 is a flow chart of the second embodiment of the power parallel control method of the present application. The power parallel control method of this embodiment is Figure 6 A flowchart of a detailed implementation of the power parallel control method in the embodiment of the present invention specifically includes the following steps:

[0148] S51: Obtaining the power supply output current provided by each external power supply circuit to the external load circuit.

[0149] S52: Regulate each power supply output current to a current sharing modulation voltage.

[0150] S53: Obtain the average bus current using each current-sharing modulation voltage.

[0151] S54: Obtain a current-sharing output voltage using a difference between the bus average current and each power supply output current.

[0152] Among them, S51, S52, S53 and S54 are Figure 6 S41, S42, S43 and S44 are the same. Please refer to S41, S42, S43 and S44 and their related text descriptions for details, which will not be repeated here.

[0153] S55: Detect whether the average bus current is within a first threshold range.

[0154] In order to solve the problem of high no-load output voltage drift, each current balancing main control circuit detects whether the current bus average current is within a first threshold range.

[0155] The first threshold range can specifically be ±5% of the rated output current of each power supply circuit, that is, each current sharing main control circuit determines whether the currently obtained bus average current is less than +5% of the rated output current and greater than -5% of the rated output current.

[0156] If the average bus current is within the first threshold range, S56 is executed; if the average bus current is not within the first threshold range, S57 is executed.

[0157] S56: Set the current sharing output voltage to 0.

[0158] When it is determined that the bus average current is within the first threshold range, the current sharing output voltage is set to 0, that is, no additional voltage regulation action is used to further adjust the power supply output current of each power supply circuit, thereby effectively avoiding the problem of high no-load output voltage drift.

[0159] S57: Each current-sharing output voltage is respectively superimposed on the power supply output voltage provided by each power supply circuit to the load circuit, and then outputted to the load circuit.

[0160] Among them, S57 and Figure 6 For details, please refer to S45 and its related text descriptions, which will not be repeated here.

[0161] See also Fig.10 , Fig.10 1 is a flow chart of the third embodiment of the power parallel control method of the present application. The power parallel control method of this embodiment is Figure 6 A flowchart of a detailed implementation of the power parallel control method in the embodiment of the present invention specifically includes the following steps:

[0162] S61: Obtain the power supply output current provided by each external power supply circuit to the external load circuit.

[0163] S62: Regulate each power supply output current to a current sharing modulation voltage.

[0164] S63: Obtain the average bus current using each current-sharing modulation voltage.

[0165] S64: Obtain a current-sharing output voltage using a difference between the bus average current and each power supply output current.

[0166] Among them, S51, S52, S53 and S54 are Figure 6 S41, S42, S43 and S44 are the same. Please refer to S41, S42, S43 and S44 and their related text descriptions for details, which will not be repeated here.

[0167] S65: Detect whether each difference is within a second threshold range.

[0168] It is understandable that if the difference between the current power supply output current and the average bus current is small, that is, the difference is within the second threshold range, this indicates that the current difference between the various power supply circuits is already very weak, and continuing to apply the current-sharing output voltage adjustment may cause unnecessary fluctuations or control errors. Therefore, in this case, setting the current-sharing output voltage to zero helps avoid over-adjustment, maintain system stability, and ensure that the power supply circuit can continue to provide high-quality, high-precision, and stable power output to the load circuit. At the same time, this approach also helps to reduce system losses and improve energy efficiency.

[0169] Specifically, each current sharing main control circuit detects whether each difference is within the second threshold range.

[0170] Optionally, the second threshold range may be any reasonable threshold range such as greater than -0.3A and less than 0.3A, or greater than -0.2A and less than 0.2A, which is determined by an actual control scenario and is not limited in this application.

[0171] If there is a difference within the second threshold range, S66 is executed; if there is no difference within the second threshold range, S67 is executed.

[0172] S66: Setting the current-sharing output voltage corresponding to the difference within the second threshold range to 0.

[0173] When at least part of the current balancing main control circuits determine that the currently obtained difference is within the second threshold range, no voltage superposition or adjustment is performed on the power supply output voltage provided by the corresponding power supply circuit to the load circuit.

[0174] S67: Each current-sharing output voltage is respectively superimposed on the power supply output voltage provided by each power supply circuit to the load circuit, and then outputted to the load circuit.

[0175] Among them, S67 and Figure 6 For details, please refer to S45 and its related text descriptions, which will not be repeated here.

[0176] It is understandable that in some other embodiments, the power parallel control circuit specifically includes some other more specific circuit units to implement other more specific power parallel control methods. For details, please refer to Figure 1-Figure 5 And related text descriptions will not be repeated here.

[0177] This application also specifically adopts a power management circuit, see Fig.11 , Fig.11Schematic diagram of a power management circuit of the present application. In this embodiment, the power management circuit 70 includes at least two power circuits 71 and a power parallel control circuit 72. The power parallel control circuit 72 includes at least two current sharing main control circuits 721 and a current sharing bus 722. Each current sharing main control circuit 721 is coupled to a power circuit 71 and is coupled to the current sharing bus 722. Each power circuit 71 is coupled to the load circuit 701.

[0178] It should be noted that the power parallel control circuit 72 described in this embodiment is the power parallel control circuit 10, the power parallel control circuit 20 or the power parallel control circuit 30 described in any one of the above embodiments. Figure 1-Figure 5 And the related text content will not be repeated here.

[0179] This application also specifically uses an electronic device, see Fig.12 , Fig.12 Schematic diagram of the framework of an electronic device of the present application. In this embodiment, the electronic device 80 includes a housing 81 and a signal processing circuit 82 connected to the housing 81 .

[0180] It should be noted that the signal processing circuit 82 described in this embodiment is the power parallel control circuit 10, the power parallel control circuit 20 or the power parallel control circuit 30 described in any of the above embodiments, or the power management circuit 50. Figure 1-Figure 5 , Fig.11 And the related text content will not be repeated here.

[0181] The beneficial effect of the present application is as follows: Different from the prior art, at least two current sharing main control circuits in the power supply parallel control circuit provided by the present application are respectively used to couple with the power supply circuit to obtain the power supply output current provided by each power supply circuit to the external load circuit, and adjust each power supply output current to a current sharing modulation voltage to send it to the current sharing bus, and use the current sharing bus to obtain the bus average current, so as to use the difference between the bus average current and each power supply output current to obtain the current sharing output voltage, and each current sharing output voltage is superimposed with the power supply output voltage provided by each power supply circuit to the load circuit, and then output to the load circuit, so that the output error of each power supply circuit can be accurately adjusted in response to the real-time feedback to ensure the current sharing of the power supply parallel; and by superimposing the output error of each power supply circuit to the corresponding power supply output voltage, the high precision of the output voltage of each power supply circuit is also effectively guaranteed, so that while meeting the power supply parallel current sharing index, it can also effectively meet the customer's high precision requirements for the output voltage.

[0182] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A power parallel control circuit, characterized in that: The power parallel control circuit comprises: At least two current sharing main control circuits, each of which is used to couple with a power supply circuit to respectively obtain the power supply output current provided by each power supply circuit to the external load circuit, and adjust each power supply output current to a current sharing modulation voltage; A current-sharing bus, coupled to each of the current-sharing main control circuits, to receive the current-sharing modulation voltage sent by each of the current-sharing main control circuits to obtain a bus average current, and to send the bus average current to each of the current-sharing main control circuits, so that each of the current-sharing main control circuits uses the difference between the bus average current and each of the power supply output currents to obtain a current-sharing output voltage, and to output each of the current-sharing output voltages to the load circuit after superimposing each of the power supply output voltages provided by each of the power supply circuits to the load circuit; Wherein, the current balancing main control circuit includes a signal processing subcircuit and a current balancing modulation subcircuit, the signal processing subcircuit is coupled to the current balancing modulation subcircuit, and is used to couple with the power supply circuit, the signal processing subcircuit receives the power supply output current sent by the power supply circuit, and adjusts the power supply output current to a mapping calibration voltage and sends it to the current balancing modulation subcircuit, so that the current balancing modulation subcircuit adjusts the mapping calibration voltage to a current balancing modulation voltage; The signal processing subcircuit receives the bus average current sent by the current-sharing bus, obtains a current-sharing output voltage by using the difference between the bus average current and the currently received power supply output current, and outputs the current-sharing output voltage to the load circuit after superimposing the power supply output voltage. The current sharing modulation subcircuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and an amplifier; the first end of the first resistor is coupled to the signal processing subcircuit, the second end of the first resistor is coupled to the first end of the second resistor, the first end of the first capacitor, and the first end of the amplifier, the second end of the second resistor is coupled to the second end of the first capacitor, the second end of the third resistor, the second end of the second capacitor, the fourth end of the amplifier, the second end of the sixth resistor, the second end of the fourth capacitor and grounded, the first end of the third resistor is coupled to the first end of the second capacitor, the second end of the amplifier, the first end of the third capacitor and the first end of the fourth resistor, the third end of the amplifier is coupled to the setting level providing end, the second end of the third capacitor is coupled to the second end of the fourth resistor, the fifth end of the amplifier and the first end of the fifth resistor, and the second end of the fifth resistor is coupled to the first end of the sixth resistor, the first end of the fourth capacitor and the current sharing bus.

2. The power parallel control circuit according to claim 1, characterized in that: The current-sharing output voltage is positively correlated with the difference.

3. The power parallel control circuit according to claim 1, characterized in that: When the current balancing main control circuit determines that the bus average current is within the first threshold range, or the difference is within the second threshold range, the current balancing output voltage is set to 0.

4. The power parallel control circuit according to claim 1, characterized in that: The current balancing main control circuit also includes a signal modulation subcircuit, which is coupled between the signal processing subcircuit and the current balancing modulation subcircuit. The signal processing subcircuit uses the power supply output current to obtain modulation characteristic parameters, and sends the modulation characteristic parameters to the signal modulation subcircuit, so that the signal modulation subcircuit maps the power supply output current to a set pulse width modulation signal, and uses the set pulse width modulation signal to obtain the mapping calibration voltage.

5. The power parallel control circuit according to claim 1, characterized in that: The current balancing main control circuit also includes a first sampling sub-circuit, which is coupled to the signal processing sub-circuit and used to couple with the power supply circuit. The first sampling sub-circuit is used to sample and obtain the power supply output current provided by the power supply circuit to the load circuit, and send the power supply output current to the signal processing sub-circuit.

6. The power parallel control circuit according to claim 1, characterized in that: The current balancing main control circuit also includes a second sampling sub-circuit, which is coupled between the current balancing bus and the signal processing sub-circuit. The second sampling sub-circuit is used to sample and obtain the bus average voltage on the current balancing bus, so as to obtain the bus average current using the bus average voltage, and send the bus average current to the signal processing sub-circuit.

7. The power parallel control circuit according to claim 1, characterized in that: The current balancing main control circuit also includes an on-off control subcircuit, which is coupled between the current balancing modulation subcircuit and the current balancing bus. When the signal processing subcircuit detects that the power supply circuit has a fault, it sends a shutdown signal to the on-off control subcircuit to trigger the on-off control subcircuit to disconnect the connection between the current balancing modulation subcircuit and the current balancing bus.

8. The power parallel control circuit according to claim 1, characterized in that: The current equalizing main control circuit also includes a drive control subcircuit, which is coupled to the signal processing subcircuit and is used to couple with the power supply circuit. The drive control subcircuit receives a control signal sent by the signal processing subcircuit, and sends a drive signal to the power supply circuit in response to the control signal, so as to trigger the power supply circuit to stop outputting the power supply output current and the power supply output voltage to or to the load circuit.

9. A power parallel control method, applied to the power parallel control circuit according to any one of claims 1 to 8, characterized in that: The power parallel control method comprises: Obtaining a power supply output current provided by each external power supply circuit to an external load circuit; Regulating each of the power supply output currents to a current-sharing modulation voltage; Obtaining a bus average current using each of the current-sharing modulation voltages; Obtaining a current-sharing output voltage using a difference between the bus average current and each of the power supply output currents; Each of the current-sharing output voltages is respectively superimposed on the power supply output voltage provided by each of the power supply circuits to the load circuit, and then output to the load circuit.

10. The power parallel control method according to claim 9, characterized in that: The step of obtaining the current-sharing output voltage by using the difference between the bus average current and each of the power supply output currents comprises: The first setting function is used to calculate the difference between the bus average current and each of the power supply output currents to obtain the current sharing loop control parameter; Each of the current balancing loop control parameters is multiplied by each of the differences to obtain the current balancing output voltage.

11. The power parallel control method according to claim 9, characterized in that: The step of adjusting each of the power supply output currents to a current sharing modulation voltage comprises: Using a second setting function to calculate each of the power supply output currents to obtain a modulation characteristic parameter; Mapping each of the power supply output currents into a set pulse width modulation signal using each of the modulation characteristic parameters; Using each of the set pulse width modulation signals to obtain a mapping calibration voltage; The mapping calibration voltage is adjusted to the current sharing modulation voltage.

12. The power parallel control method according to claim 9, characterized in that: After the step of obtaining the current-sharing output voltage by using the difference between the bus average current and each of the power supply output currents, the method further includes: Detecting whether the bus average current is within a first threshold range; If the bus average current is within the first threshold range, each of the current-sharing output voltages is set to 0.

13. The power parallel control method according to claim 9, characterized in that: After the step of obtaining the current-sharing output voltage by using the difference between the bus average current and each of the power supply output currents, the method further includes: Detecting whether each of the difference values ​​is within a second threshold range; If the difference is within the second threshold range, the current sharing output voltage corresponding to the difference within the second threshold range is set to 0.

14. A power management circuit, characterized in that: The power management circuit includes at least two power circuits and a power parallel control circuit, the power parallel control circuit includes at least two current sharing main control circuits, and each of the current sharing main control circuits is coupled to one of the power circuits; Wherein, the power parallel control circuit is the power parallel control circuit as claimed in any one of claims 1-8.

15. An electronic device, characterized in that: The electronic device comprises a housing and a signal processing circuit coupled to each other; Wherein, the signal processing circuit is the power parallel control circuit as described in any one of claims 1 to 8, or the power management circuit as described in claim 14.

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