Video processing method, device, chip, equipment and medium

Abstract

The present application relates to a video processing method, device and video processing chip. The method is applied to a video processing chip, wherein the processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0; the method includes: during the display process of a video frame, determining the target processing unit to which the target configuration table loaded in the current target RAM is applicable; the target RAM is an unused RAM in the N+1 RAMs; adjusting the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM; reading the target configuration table loaded in the current target RAM pointed to by the target processing unit, and displaying the video frame according to the target configuration table. The present application can reduce the area of ​​the video processing chip to reduce costs.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a video processing method, apparatus, video processing chip, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the development of science and technology, video processing and display technology has been more and more widely used in people's daily life, resulting in more and more demand and requirements for video processing chips. The current video processing chip is usually a SoC (System on Chips) that integrates many modules such as ISP (Image Signal Process) and DPU (Display Process Unit). The integration is getting higher and higher, and the cost of the chip is also getting higher and higher.

[0003] In order to meet the requirements of excellent image quality, there are usually some adaptive algorithms in the video acquisition and display process to cope with different scenes. For example, according to the scenes of daytime and night, the relevant configuration parameters are adaptively switched dynamically according to the scene to distinguish the display. Video acquisition and display have real-time requirements, which also requires that the parameters take effect in real time (timely) when the scene is dynamically switched. The processing module in the video processing chip usually faces a large number of lookup table submodules, such as 3DLUT (Three-Dimensional Look-Up Table), gamma and other submodules. Among them, 3DLUT is a commonly used video processing technology, which can perform color correction, brightness adjustment and other processing on the input video signal to improve the quality of the video. However, the implementation of 3DLUT requires a lot of storage space and computing resources, which increases the cost of video processing and display chips.

[0004] In the traditional way, in order to meet the needs of timely effectiveness of submodules with a large number of parameter configurations such as 3DLUT, shadow registers are usually used in chip design in combination with ping-pong RAM (Random Access Memory). However, when it comes to scenarios that require docking with multiple acquisition channels or multiple display screens, that is, multi-channel video acquisition or display scenarios, when a three-dimensional lookup table is required for each video channel, the need for ping-pong RAM will lead to a sharp increase in chip area, greatly increasing the chip manufacturing cost. Summary of the invention

[0005] Based on this, it is necessary to provide a video processing method, device, computer equipment, computer-readable storage medium and computer program product that can reduce chip area and reduce chip manufacturing costs in response to the above technical problems.

[0006] In a first aspect, the present application provides a video processing method, which is applied to a video processing chip, wherein a processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0; the method includes:

[0007] During the display process of the video frame, determining the target processing unit to which the target configuration table loaded into the target RAM at that time is applicable; the target RAM is an unused RAM in the N+1 RAMs;

[0008] Adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM;

[0009] The target configuration table loaded into the current target RAM pointed to by the target processing unit is read, and the video frame is displayed according to the target configuration table.

[0010] In a second aspect, the present application further provides a video processing device, which is applied to a video processing chip, wherein a processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0; the device includes:

[0011] A determination module, used for determining, during the display process of the video frame, a target processing unit applicable to the target configuration table loaded into the current target RAM; the target RAM is an unused RAM in the N+1 RAMs;

[0012] An adjustment module, used for adjusting the address pointed to by the target processing unit, so that the target processing unit points to the target RAM of the current time, and the RAM originally pointed to by the target processing unit is updated to the target RAM of the next time;

[0013] The reading module is used to read the target configuration table loaded into the current target RAM pointed to by the target processing unit, and display the video frame according to the target configuration table.

[0014] In the third aspect, the present application also provides a video processing chip, comprising N+1 RAMs and N processing units, any of the processing units being connected to the N+1 RAMs respectively through a multi-way switch, N being a positive integer greater than 0, and the video processing chip being used to implement the above-mentioned video processing method.

[0015] In a fourth aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned video processing method when executing the computer program.

[0016] In a fifth aspect, the present application also provides a computer-readable storage medium on which a computer program is stored, and the computer program implements the above-mentioned video processing method when executed by a processor.

[0017] In a sixth aspect, the present application also provides a computer program product, including a computer program, which implements the above-mentioned video processing method when executed by a processor.

[0018] The above-mentioned video processing method, device, video processing chip, computer equipment, computer-readable storage medium and computer program product, in the process of displaying the video frame, pre-loads the target configuration table in the target RAM that is not used at the time, and when it is needed, it can directly determine the target processing unit applicable to the target configuration table loaded in the target RAM that is not used at the time, and then adjust the address pointed to by the target processing unit so that the target processing unit points to the target RAM of the time. In this way, the target configuration table loaded in the target RAM of the time can be read and switched immediately, and the RAM originally pointed to by the target processing unit will be used as the target RAM of the next time. In this way, the present application designs the use of N+1 RAMs, which can provide a dynamic switching function of the configuration table on the one hand, and meet the requirements of timely effectiveness, and can be applied to different scenarios; on the other hand, compared with the design of ping-pong RAM, it can reduce the storage space required for the video processing chip, reduce the area of ​​the video processing chip, and also reduce the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is an internal structure diagram of a video processing chip in one embodiment;

[0021] Figure 2 A control timing diagram of video frame display in one embodiment;

[0022] Figure 3 is a schematic flow chart of a video processing method in one embodiment;

[0023] Figure 4 is a structural block diagram of a video processing device in one embodiment;

[0024] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] The video processing method provided in the embodiment of the present application can be applied to a computer device. The computer device can be a device with an image acquisition device, or a device with a display screen, or a device with both an image acquisition device and a display screen. The image acquisition device can specifically be a camera. The computer device can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, vehicles, portable wearable devices, etc.

[0027] Before introducing the video processing method provided by this application, the video processing chip used in this application is introduced. The video processing chip in this application may include a processor and a processing module. The processor may be a CPU (Central Processing Unit), and the processing module may be a real-time processing module such as an ISP and a DPU. For a video processing chip integrated with the above-mentioned related processing modules, any processing module may include N+1 RAMs and N processing units.

[0028] Take the DPU as an example for explanation. Please refer to Figure 1 , Figure 1 The DDR (double rate synchronous dynamic random access memory, a type of memory) in the video processing chip is the external memory of the video processing chip, and the RAM is the internal storage of the video processing chip. Taking N as 2 as an example, the DPU module may include 3 RAMs (RAM0, RAM1, and RAM2) and 2 processing units (such as 3DLUT1 and 3DLUT2). During the video processing process, the DPU module will load the configuration table (such as lut1, lut2, lut3, lut4) in the DDR into the RAM of the video processing chip.

[0029] The traditional ping-pong RAM design requires 2N RAMs, while the video processing chip designed in this application only requires N+1 RAMs. Combined with the video processing method introduced later, it can meet the needs of different scenarios, provide dynamic switching function of the configuration table, and the requirement of timely effectiveness, which reduces the storage space required for the video processing chip, thereby reducing the area of ​​the video processing chip and reducing its manufacturing cost.

[0030] Reference below Figure 2 , let’s introduce the display-related signals involved in the video display process:

[0031] Vertical synchronization signal (VSYNC): indicates the start and end of a frame of image. When the Vsync signal is high, it indicates the end of a frame of image; when the Vsync signal is low, it indicates the beginning of a frame of image.

[0032] Vertical Front Porch (VFP): refers to the time before the vertical synchronization signal, which is used to adjust the position of the image or refresh the screen. During the period before the Vsync signal, the screen can be refreshed or adjusted.

[0033] Vertical Back Porch (VBP): refers to the time after the vertical sync signal, which is used to adjust the position of the image or refresh the screen. During the period after the Vsync signal, the screen can be refreshed or adjusted.

[0034] Horizontal synchronization signal (HSYNC): indicates the start and end of each line of the image. When the Hsync signal is high, it indicates the end of a line of the image; when the Hsync signal is low, it indicates the beginning of a line of the image.

[0035] Horizontal Front Porch (HFP): refers to the time before the horizontal sync signal, which is used to adjust the position of the image or refresh the screen. During the period before the Hsync signal, the screen can be refreshed or adjusted.

[0036] Horizontal Back Porch (HBP): Refers to the time after the horizontal sync signal, which is used to adjust the image position or refresh the screen. The screen can be refreshed or adjusted during the period after the Hsync signal.

[0037] It should be noted that generally, each video frame of any video channel has interrupt1 and interrupt2. Taking two videos as an example, the video frames in video 1 correspond to interrupt11 and intterupt12, and the video frames in video 2 correspond to interrupt21 and intterupt22. 3DLUT1 processes the video frames of video 1, and 3DLUT2 processes the video frames of video 2.

[0038] In an exemplary embodiment, Figure 3 As shown, a video processing method is provided, and the method is described by taking the application of the method to a video processing chip in a computer device as an example, including the following steps 302 to 306. Among them:

[0039] Step 302, during the display process of the video frame, determine the target processing unit applicable to the target configuration table loaded into the current target RAM; the target RAM is the unused RAM in the N+1 RAMs.

[0040] The video processing chip is a chip used for processing and displaying video data, which may include a processor and a processing module. The processor may be a CPU, and the processing module may be an ISP, a DPU, etc. The processing module includes N processing units, each of which can process one video frame, and each video frame can be connected to at least one panel (display) for display.

[0041] The target RAM is the unused RAM in the current N+1 RAMs. It can be understood that for each processing unit in the processing module, a RAM is associated and used in each video frame display process, then N processing units will use N RAMs, and the remaining unused RAM is the target RAM. Exemplarily, the target RAM can be the above Figure 1 RAM0 in.

[0042] The target configuration table is the configuration table indicated by the configuration switching instruction, that is, the configuration table that needs to be switched to currently. The configuration table can be a three-dimensional lookup table related to color. Different configuration tables can correspond to different display scenarios, such as configuration table 1 for day mode and configuration table 2 for night mode.

[0043] It can be understood that one processing unit can be used to process video frames of one video channel, and one video channel can be connected to at least one display screen for display. N processing units can process N videos, and these N videos can correspond to the same configuration table or different configuration tables. This can be set based on actual business needs. In other words, N processing units can use the same configuration table or different configuration tables, that is, when configuration switching is required, the configuration table used by a single or multiple processing units can be switched. In this application, only one displayed configuration table can be switched at the same time; when multiple displays need to be switched at the same time, it is necessary to switch them serially one by one.

[0044] Specifically, after receiving the configuration switching instruction, the processor in the video processing chip can respond to the configuration switching instruction and check whether the target RAM is loaded with the target configuration table indicated by the configuration switching instruction. If not, the target configuration table can be found from the external memory and loaded into the target RAM. If the target RAM is loaded with the target configuration table indicated by the configuration switching instruction, the target processing unit adapted by the target configuration table can be determined, and the preset instruction can be sent to the processing module (such as DPU). The processing module determines the target processing unit to which the target configuration table loaded in the target RAM is applicable by reading the preset instruction.

[0045] During the display of the video frame, the video processing chip can read the value of the target register and determine the target processing unit to which the target configuration table loaded in the target RAM is applicable according to the value of the target register. Specifically, the processor in the video processing chip can read the value of the target register and determine whether the target configuration table is successfully loaded in the target RAM according to the value of the target register, and which processing unit the loaded target configuration table is used for, thereby sending a preset instruction to the processing module.

[0046] The register may be a flag register, also known as a program status word, which may store multi-bit data, and different data may represent different states. The target register may be the first register and the second register in the following embodiment, or the third register in the following embodiment.

[0047] In some embodiments, the configuration switching instruction may be received by the processor when displaying the video frame before the i-th frame, and includes configuration information, and the configuration information may specifically include the address of the target configuration table in the DDR, and the processing unit identifier, and the processing unit identifier is used to indicate the target processing unit. After the processor receives the configuration switching instruction, it can load the target configuration table indicated by the configuration switching instruction to the target RAM at an appropriate time, so that it can be read and taken effect immediately during the display process of the i-th video frame. Among them, the video frame before the i-th frame may be the i-1th frame, or the 1-2th frame, etc., wherein i is a positive integer greater than or equal to 1.

[0048] Step 304, adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM.

[0049] Specifically, the processing module in the video processing chip can adjust the address pointed to by the target processing unit so that the target processing unit points to the target RAM at that time. The adjustment method can be specifically to control the path between the target processing unit and the originally connected RAM to be disconnected, and control the path between the target processing unit and the target RAM to be connected, so that the target processing unit can point to the target RAM, and can directly read the target configuration table in the target RAM when reading data.

[0050] It can be understood that when the address pointed to by the target processing unit is the address of the target RAM, the target RAM is in use, and the RAM originally pointed to by the target processing unit is released and is in an unused state and will be used as the next target RAM.

[0051] In some embodiments, the video processing chip includes N+1 RAMs and N processing units. Any processing unit is connected to the N+1 RAMs respectively through a multi-way switch. The processor can control the multi-way switch to disconnect the path between the originally connected RAM and connect the path to the target RAM.

[0052] Step 306, read the target configuration table loaded in the current target RAM pointed to by the target processing unit, and display the video frame according to the target configuration table.

[0053] Specifically, the processing module in the video processing chip can read the target configuration table loaded in the current target RAM pointed to by the target processing unit, and in the process of horizontal synchronization and vertical synchronization for the current video frame or the next video frame, update the pixel value of each pixel based on the target configuration table, thereby realizing the display of the video frame, that is, realizing the state switching.

[0054] In the above-mentioned video processing method, during the display process of the video frame, the target configuration table is pre-loaded in the target RAM that is not used at the time. When it is needed, the target processing unit applicable to the target configuration table loaded in the target RAM that is not used at the time can be directly determined, and then the address pointed to by the target processing unit is adjusted so that the target processing unit points to the target RAM of the time. In this way, the target configuration table loaded in the target RAM of the time can be read and switched immediately, and the RAM originally pointed to by the target processing unit will be used as the target RAM for the next time. In this way, the present application designs the use of N+1 RAMs, which can provide a dynamic switching function of the configuration table on the one hand, and meet the requirements of timely effectiveness, and can be applied to different scenarios; on the other hand, compared with the design of ping-pong RAM, it can reduce the storage space required for the video processing chip, reduce the area of ​​the video processing chip, and also reduce the manufacturing cost.

[0055] Exemplarily, the present application may implement the above-mentioned video processing method through two registers, as follows:

[0056] In some embodiments, before determining the target processing unit to which the target configuration table loaded into the current target RAM is applicable, the method further includes: in response to a configuration switching instruction, obtaining the corresponding target configuration table and loading the target configuration table into the current target RAM, and setting the value of the first register to a first preset value after successful loading.

[0057] It can be understood that if the target configuration table is to be effective in time in the i-th video frame or the video frame after the i-th video frame, the target configuration table can be loaded into the target RAM in advance to avoid the time consumption caused by loading the configuration table in the external memory of the video processing chip into the RAM. In other words, the configuration switching instruction can be received during the display process of the video frame before the i-th video frame.

[0058] The configuration switching instruction includes configuration information, which may specifically include the address of the target configuration table in the DDR and a processing unit identifier, which is used to indicate the target processing unit. After receiving the configuration switching instruction, the processor updates the value of the second register according to the processing unit identifier.

[0059] In one implementation, in response to a configuration switching instruction, the video processing chip can obtain the target configuration table from the DDR according to the address of the target configuration table in the DDR in the configuration information, and load the target configuration table into the current RAM. If the loading is successful before the next video frame start interrupt time arrives, the value of the first register is adjusted so that the adjusted value of the first register indicates that the target configuration table is loaded successfully.

[0060] In another implementation, in response to a configuration switching instruction, the video processing chip can read the value of the second register. If the value of the second register represents any one of a plurality of specified values, a corresponding target configuration table is obtained according to the value of the second register, and the target configuration table is loaded into the current target RAM. After successful loading, the value of the first register is adjusted, and the adjusted value of the first register represents successful loading.

[0061] It should be noted that the processor can read the value of the second register at an appropriate time. The appropriate time can be any time, or a frame interruption time. The frame interruption time includes a video frame start interruption time and a video frame end interruption time.

[0062] If the value of the second register represents any value among a plurality of specified values, the target processing unit is determined according to the value of the second register, and the corresponding target configuration table is obtained from the DDR according to the storage address in the DDR associated with the target processing unit. The target configuration table is loaded into the current target RAM. If the loading is successful before the next video frame start interruption time arrives, the value of the first register is updated, and the updated value of the first register represents that the target configuration table is loaded successfully. In this way, during the display process of the next video frame, the target configuration table stored in the target RAM can be directly used by adjusting the address pointing, thereby realizing flexible switching and timely adjustment of the configuration.

[0063] It should be noted that the number of the first registers may be one or more.

[0064] If the number of first registers is 1, then the value of the first register can be set to a first preset value, such as 1, to indicate that the target configuration table is loaded successfully; the value of the first register can be set to a second preset value, such as 0, to indicate that the target configuration table is not loaded successfully.

[0065] If the number of first registers is more than one, then a value obtained by combining the values ​​of multiple first registers can be used to indicate whether the target configuration table is loaded successfully. For example, if the value obtained by combining the values ​​of multiple first registers is the third preset value, such as 01, it indicates that the target configuration table is loaded successfully; if the value obtained by combining the values ​​of multiple first registers is the fourth preset value, such as 10, it indicates that the target configuration table is not loaded successfully.

[0066] Likewise, the number of the second register may be one or more.

[0067] If the number of the second register is 1, it is used to indicate the target processing unit, and it corresponds to N+1 values. These N+1 values ​​include 0 and N specified values. Among them, 0 indicates no update, that is, no configuration switching is required; the specified value is a value corresponding to the processing unit, such as value 1 indicates processing unit 1, value 2 indicates processing unit 2, value 3 indicates processing unit 3, etc. It can be understood that if the value of the second register is any value among multiple specified values, it indicates that the processing unit corresponding to the value needs to be configured. Switching.

[0068] If the number of second registers is more than 1, then the processing unit identification can be represented by the value obtained by combining the values ​​of multiple second registers. For example, if the number of second registers is 3, if the data obtained by combining multiple second registers in sequence is 000, it indicates that no configuration switching is required; if the data obtained by combining multiple second registers in sequence is 001, it indicates processing unit 1; if the data obtained by combining multiple second registers in sequence is 010, it indicates processing unit 2; if the data obtained by combining multiple second registers in sequence is 011, it indicates processing unit 3, and so on.

[0069] In the above embodiment, when the target configuration table is not successfully loaded into the target RAM, the target RAM is refreshed in response to the configuration switching instruction to load the target configuration table into the target RAM, thereby realizing advance preloading. In this way, when the subsequent target processing unit needs to read the target configuration table, it can be read directly from the target RAM, thereby improving the response efficiency.

[0070] In some embodiments, the video processing method includes: reading the value of the first register within the video frame start interruption period of the current video frame; the value of the first register is used to indicate whether the target RAM of the current time is successfully loaded into the target configuration table; if the value of the first register indicates that the loading is successful, then reading the value of the second register, and determining the target processing unit from N processing units according to the value of the second register. Adjusting the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM; reading the target configuration table loaded in the current target RAM pointed to by the target processing unit, and displaying the current video frame according to the target configuration table.

[0071] The video frame start interruption period is an interruption period before the video frame starts to be displayed. For example, it can be the above Figure 1 The duration of interrupt0 in .

[0072] The value of the first register is used to indicate whether the target RAM is successfully loaded into the target configuration table. For example, when the value of the first register is 0, it indicates that the target configuration table is not loaded; when the value of the first register is 1, it indicates that the target configuration table is successfully loaded.

[0073] Specifically, during the display of the current video frame, if the time point of the video frame start interruption is reached, the processor can read the value in the first register. If the value of the first register indicates that the target configuration table has been successfully loaded, the value in the second register can be read; if the value of the first register indicates that the target configuration table has not been successfully loaded, no processing is performed.

[0074] Furthermore, the processor may determine the target processing unit according to the value of the second register, that is, the value of the second register is used to indicate the processing unit. For example, when the value of the second register is 0, it indicates that no update is performed, and when the value of the second register is j, it indicates that the address pointed to by the jth processing unit needs to be updated. Wherein, j is a positive integer greater than 0.

[0075] Furthermore, after the processor determines the target processing unit through the value of the second register, it can send a preset instruction to the processing module to instruct the processing module to adjust the address pointed to by the target processing unit during the video frame start interruption period to point to the target RAM.

[0076] In some embodiments, after adjusting the address pointed to by the target processing unit, the method further includes: adjusting the value of the first register so that the adjusted value of the first register indicates that the loading is not successful. For example, the value of the first register can be adjusted to a second preset value; the second preset value is different from the first preset value. The second preset value is, for example, 0. In this way, it is indicated that the new target RAM can be used to load the new target configuration table.

[0077] In some embodiments, if the target configuration table in the current target RAM is used, the processor may set the value of the second register to 0, so that it can be adjusted when a new configuration switching instruction is received subsequently.

[0078] In the above embodiment, by reading the value of the first register to determine whether the target configuration table has been loaded in the target RAM, and then by reading the value of the second register to determine which processing unit the target configuration table should be used for, the switching of the target configuration table can be achieved conveniently and accurately.

[0079] In one specific embodiment, the video processing method comprises the following steps:

[0080] In response to the configuration switching instruction, the target configuration table is obtained and loaded into the current target RAM. After the loading is successful, the value of the first register is adjusted so that the adjusted value of the first register indicates that the loading is successful.

[0081] The value of the first register is read during the video frame start interruption period of the current video frame; the value of the first register is used to indicate whether the target RAM at that time is successfully loaded into the target configuration table.

[0082] If the value of the first register indicates that the loading is successful, the value of the second register is read, and the target processing unit is determined from the N processing units according to the value of the second register.

[0083] The address pointed to by the target processing unit is adjusted so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM. The value of the first register is adjusted again so that the adjusted value of the first register indicates that the loading is unsuccessful.

[0084] The target configuration table loaded in the current target RAM pointed to by the target processing unit is read, and the video frame is displayed according to the target configuration table.

[0085] The following takes N as 2 and the configuration table as a 3dlut table as an example for description. In a specific embodiment, the video processing method includes the following steps:

[0086] Set the first register = 0\1\2, 0 is the default value, indicating that RAM0 can be updated, 1 indicates that RAM0 has successfully loaded the target configuration, and 2 indicates that RAM0 is loading the target configuration.

[0087] The second register is set to 0\1\2, where 0 is the default value, indicating no update, 1 indicates updating the first processing unit 3DLUT1, and 2 indicates updating the second processing unit 3DLUT2.

[0088] When enabled for the first time, the first processing unit 3DLUT1 and the second processing unit 3DLUT2 each use their own default configured RAM to load the corresponding configuration table. If a video channel needs to update the configuration table, the update task issued by the CPU will be configured in the interrupt1 of the DPU, and the steps are as follows:

[0089] After the frame start interrupt interrupt1 is completed, the DPU starts processing and reads the value of the first register:

[0090] If the value of the first register is 0, it means that the loading is not started or there is no update task; if the value of the first register is 2, it means that the loading is not completed. The first processing unit 3DLUT0 and the second processing unit 3DLUT2 of the DPU each continue to use the original 3dlut table for processing.

[0091] If the value of the first register is 1, the value of the second register is read. If the value of the second register is 1, the first processing unit 3DLUT1 enables the 3dlut table of RAM0, and the positions of RAM0 and RAM1 are swapped, the value of the first register is set to 0, and the value of the second register is set to 0; if the value of the second register is 2, the second processing unit 3DLUT2 enables the 3dlut table of RAM0, and the positions of RAM0 and RAM2 are swapped, the value of the first register is set to 0, and the value of the second register is set to 0; if the value of the second register is 0, the 3DLUT1 and 3DLUT2 of the DPU continue to use the 3dlut table configuration of the previous frame for processing. It should be noted that the swap is only in expression, and the purpose is to simplify the expression for easy understanding, so that the target RAM always corresponds to "RAM0", and in actual implementation, the target RAM rotates among various RAMs.

[0092] In the frame end interrupt interupt2, in response to the configuration switching instruction, the CPU first reads the value of the first register. If it is 0, the second register is configured to be 1 or 2, and the corresponding configured DDR address. During or after the interrupt processing, the CPU configures the first register to be 2, and loads the target configuration table in the DDR to RAM0 according to the configuration. After the loading is successful, the value of the first register is set to 1. Repeat all the above steps.

[0093] It should be noted that, in the case of multi-tasking and multi-threading, for the public resources RAM0, the first register and the second register involved in the above steps, the public resources involved need to be locked during the configuration process. In addition, in addition to responding to the configuration switching instruction in the frame end interrupt interupt2, the configuration switching instruction can also be responded to in interrupt1.

[0094] Exemplarily, the present application also provides a method for implementing the video processing method through a register, as follows:

[0095] In some embodiments, before determining the target processing unit to which the target configuration table loaded into the current target RAM is applicable, the method further includes: in response to a configuration switching instruction, checking the state of the current target RAM; if the state of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, obtaining a corresponding target configuration table and loading the target configuration table into the current target RAM.

[0096] Specifically, the configuration switching instruction may be received during the display process of the previous video frame, or may be received during the display process of the current video frame. When the configuration switching instruction is received at any time, the processor may check the state of the target RAM at that time, specifically, by reading the value in the third register. It is understood that the number of the third registers may be one or more.

[0097] If the state of the target RAM at that time indicates that the data in the target RAM is invalid and needs to be updated, for example, the state is 0, the processor or processing module can obtain the target configuration table from the DDR and load the target configuration table into the target RAM at that time; otherwise, the occupied content of the target RAM can be returned, and the CPU continues to query the state of the target RAM until the state of the target RAM is 0 while executing the refresh action, or the processor thread sleeps and waits for the preset interrupt time to arrive, and then executes the step of adjusting the address pointed to by the target processing unit.

[0098] The preset interruption time may be a video frame start interruption time and / or a video frame end interruption time of any channel of video frames.

[0099] In the above embodiment, the configuration switching instruction can be responded to at any time to load the target configuration table into the target RAM in time.

[0100] In some embodiments, determining the target processing unit to which the target configuration table loaded into the current target RAM is applicable includes: when a preset interruption moment of a video frame of any video channel is reached, checking the state of the current target RAM; if the state of the current target RAM indicates that the data in the target RAM is valid, then determining the target processing unit to which the target configuration table loaded into the current target RAM is applicable based on the state of the current target RAM.

[0101] Specifically, for any video frame of a video channel, when the preset interruption time of the video frame is reached, the processor can check the state of the current target RAM. If the state of the current target RAM indicates that the data in the target RAM is valid, the target processing unit is determined based on the processing unit identifier indicated by the state of the current target RAM.

[0102] For example, when the state is 1, it means that the configuration in processing unit 1 is to be updated, and processing unit 1 is the target processing unit; when the state is 2, it means that the configuration in processing unit 2 is to be updated, and processing unit 2 is the target processing unit.

[0103] Furthermore, within the preset interruption period, the processing module can adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM.

[0104] In some embodiments, the preset interruption time may be the video frame start interruption time, or the video frame end interruption time, or the video frame start interruption time and the video frame end interruption time, which is not limited in the embodiments of the present application. It should be noted that, whether it is the video frame start interruption time or the video frame end interruption time, it refers to the interruption time of the video frame in a certain video channel.

[0105] It can be understood that if the preset interruption moment is the video frame start interruption moment of the current video frame, then the target configuration table can take effect during the display process of the current video frame; if the preset interruption moment is the video frame end interruption moment of the current video frame, then the target configuration table can take effect during the display process of the next video frame of the current video frame.

[0106] Further, after adjusting the address pointed to by the target processing unit, the method further includes: updating the state of the next target RAM so that the state of the next target RAM indicates that the data in the next target RAM is invalid and needs to be updated. For example, setting the state of the next target RAM to 0 indicates that the RAM can be refreshed.

[0107] In the above embodiment, when the preset interruption moment of the video frame of any video channel is reached, the state of the target RAM at that time is checked, and the target processing unit can be determined in time when the preset interruption moment is reached, so that the target processing unit can use the target configuration table in the target RAM in time to achieve the effect of timely effectiveness.

[0108] In some embodiments, the video processing method also includes: in response to a configuration switching instruction, checking the state of the current target RAM; if the state of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, obtaining a corresponding target configuration table and loading the target configuration table into the current target RAM; if the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, determining the target processing unit to which the target configuration table loaded in the current target RAM applies; waiting for a preset interrupt time of a video frame associated with the target processing unit, and when the preset interrupt time of the video frame associated with the target processing unit is reached, adjusting the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM; reading the target configuration table loaded in the current target RAM pointed to by the target processing unit, and displaying the video frame according to the target configuration table.

[0109] Specifically, when receiving a configuration switching instruction at any time, the processor can check the state of the current target RAM, specifically, it can read the value in the third register. If the state of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, for example, the state is 0, the processor or processing module can obtain the target configuration table from the DDR and load the target configuration table into the current target RAM.

[0110] If the state of the current target RAM indicates that the data in the target RAM is valid, then the target processing unit to which the target configuration table loaded in the current target RAM applies is determined based on the state of the current target RAM. For example, when the state is 1, it means that the configuration in processing unit 1 is to be updated, and processing unit 1 is the target processing unit; when the state is 2, it means that the configuration in processing unit 2 is to be updated, and processing unit 2 is the target processing unit.

[0111] Furthermore, the preset interruption moment of the video frame associated with the target processing unit is waited for. When the preset interruption moment of the video frame associated with the target processing unit is reached, the processing module can adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM; then the target configuration table loaded in the current target RAM pointed to by the target processing unit is read, and the video frame associated with the target processing unit is displayed according to the target configuration table.

[0112] Among them, the preset interruption time can be the start interruption time of the video frame, or the end interruption time of the video frame, or the start interruption time of the video frame and the end interruption time of the video frame, which is not limited in the embodiment of the present application.

[0113] In the above embodiment, if the state of the current target RAM indicates that the data in the target RAM is valid, the target processing unit to which the target configuration table loaded in the current target RAM is applicable is determined based on the state of the current target RAM. Then, when the preset interruption time of the video frame associated with the target processing unit is directly waited for to arrive, the address pointed to by the target processing unit is adjusted to perform address adjustment so that the target configuration table can take effect in time.

[0114] Further, after adjusting the address pointed to by the target processing unit, the method further includes: updating the state of the next target RAM so that the state of the next target RAM indicates that the data in the next target RAM is invalid and needs to be updated. For example, setting the state of the next target RAM to 0 indicates that the RAM can be refreshed.

[0115] In a specific embodiment, the video processing method includes the following steps:

[0116] In response to the configuration switching instruction, the processor checks the state of the current target RAM; if the state of the current target RAM is 0, the processor obtains the corresponding target configuration table from the DDR and loads the target configuration table into the current target RAM; and updates the state of the target RAM according to the processing unit identifier carried in the configuration switching instruction. The state is represented by the value of the third register.

[0117] If the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, determine the target processing unit to which the target configuration table loaded in the current target RAM is applicable. Wait for the preset interruption time of the video frame associated with the target processing unit. When the preset interruption time of the video frame associated with the target processing unit is reached, the processor sends a preset instruction to the processing module to instruct the processing module to adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM. And / or, when the preset interruption time of the video frame of any video is reached, the processor checks the state of the current target RAM. If the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, determine the target processing unit to which the target configuration table loaded in the current target RAM is applicable. The processor sends a preset instruction to the processing module to instruct the processing module to adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM.

[0118] The state of the next target RAM is updated so that the state of the next target RAM indicates that the data in the next target RAM is invalid and needs to be updated.

[0119] The processing module reads the target configuration table loaded in the current target RAM pointed to by the target processing unit, and displays the current video frame or the next video frame in the display screen connected to the target processing unit according to the target configuration table.

[0120] It can be understood that if the preset interruption moment is the video frame start interruption moment of the current video frame, then the target configuration table can take effect during the display process of the current video frame; if the preset interruption moment is the video frame end interruption moment of the current video frame, then the target configuration table can take effect during the display process of the next video frame of the current video frame.

[0121] The above video processing method takes 3DLUT as an example. For a 17x17x17 3DLUT, the area of ​​a 3DLUT with 2 RAM chips is 7 square meters under the 12nm process. Reducing 1 RAM chip can reduce 3.5 square meters. The video processing method of the present application saves chip costs by sharing 1 RAM chip, and supports dynamic switching of parameter tables, with the constraint that only 1 configuration table can be switched at the same time. This solution can solve the problem of the need to switch the configuration table and the transition gradient when switching when the scene changes. For example, when the scene change causes the 3dlut table to switch, each frame can be configured and take effect in time, so that the 3DLUT effect, that is, the color gradient is smooth without jumps.

[0122] Please refer to Figure 1 , the following takes N as 2 and the configuration table as 3dlut table as an example to illustrate the video processing method provided by this application:

[0123] In one of the embodiments, RAM0 has four states: 0: data is unavailable and can be refreshed; 1: data is available for the first processing unit 3DLUT1; 2: data is available for the second processing unit 3DLUT2; 3: data is unavailable and in the process of refreshing; the default is 0.

[0124] When enabled for the first time, the first processing unit 3DLUT1 and the second processing unit 3DLUT2 each use their own RAM to load the corresponding configuration table. If a certain video needs to update the configuration table, the following methods will be used to implement it:

[0125] Method 1:

[0126] 1-1. When the user needs to update the configuration table of 3DLUT1 or 3DLUT2 at any time, the CPU queries the status of RAM0:

[0127] 1) If it is equal to 0, the CPU or DPU starts to refresh RAM0 and configures the RAM0 state to 3; after the refresh is successful, RAM0 is set to state 1 or 2, and the refresh success is returned.

[0128] 2) If it is equal to 1 or 2, you can choose the following implementation method.

[0129] The CPU directly returns the RAM0 occupied state. When returning to the RAM0 occupied state, the user continues to issue update requests until the RAM0 state is 0, and enters 1-1 step 1). After the RAM0 is refreshed successfully, the refresh success is returned.

[0130] 3) If it is equal to 3, it means that other users are using RAM0 to load. You can choose the following implementation methods:

[0131] The CPU directly returns the RAM0 occupied state. When returning to the RAM0 occupied state, the user continues to issue update requests until the RAM0 state is 0, and enters step 1). After RAM0 is refreshed successfully, the refresh success is returned.

[0132] 1-2. Before DPU's 3DLUT1 processing, DPU checks RAM0 status:

[0133] 1) If it is equal to 0 or 3, no action is taken, which means that the 3dlut configuration of the previous frame is used;

[0134] 2) If it is equal to 1, swap RAM0 and RMA1, set the RAM0 state to 0, and then 3DLUT1 uses the newly configured 3dlut table to execute;

[0135] 1-3. Before DPU's 3DLUT2 processing, DPU checks RAM0 status:

[0136] 1) If it is equal to 0 or 3, no action is taken, which means that the 3dlut configuration of the previous frame is used;

[0137] 2) If it is equal to 2, swap RAM0 and RMA2, set the RAM0 state to 0, and then 3DLUT2 uses the newly configured 3DLUT table to execute;

[0138] Optionally, 1-2 and 1-3 may perform status checking and swapping operations during frame start interrupt or frame end interrupt processing.

[0139] 1-4. Repeat steps 1-1 to 1-3.

[0140] Method 2:

[0141] 2-1. When the user needs to update the configuration table of 3DLUT1 or 3DLUT2 at any time, the CPU queries the status of RAM0:

[0142] 1) If it is equal to 0, the CPU or DPU starts to refresh RAM0 and configures RAM0 state to 3; after the refresh is successful, the logic sets RAM0 to state 1 or 2;

[0143] 2) If it is equal to 1, the current CPU thread sleeps and waits for interrupt12. In the interrupt12 interrupt processing, RAM1 and RAM0 are swapped, RAM0 is configured to state 0, and the thread is awakened. The current thread enters step 2-1, step 1).

[0144] Optionally, the DPU swaps RAM1 and RAM0 before processing 3DLUT1, and configures the RAM0 state to 0, and then generates an interrupt to the CPU to wake up the thread, or wakes up the thread in the end interrupt interrupt12 of the current frame, or wakes up the thread in the start interrupt interrupt11 of the next frame;

[0145] 3) If it is equal to 2, the current CPU thread sleeps and waits for interrupt12. In the interrupt12 interrupt processing, RAM2 and RAM0 are swapped, RAM0 is configured to state 0, and the thread is awakened. The current thread enters step 2-1, step 1).

[0146] Optionally, the DPU swaps RAM2 and RAM0 before processing 3DLUT2, and configures the RAM0 state to 0, and then generates an interrupt to the CPU to wake up the thread, or wakes up the thread in the end interrupt interrupt22 of the current frame, or wakes up the thread in the start interrupt interrupt21 of the next frame;

[0147] 4) If it is equal to 3, it means that other users are loading the configuration table into RAM0, the CPU current thread is asleep, and RAM0 enters state 1 or 2 under the operation of other users, the same as 2) and 3) in step 2-1.

[0148] 2-2. Repeat step 2-1.

[0149] It should be noted that, in the case of multi-tasking and multi-threading, the public resources RAM0, the first register and the second register involved in the above steps may be locked during the configuration process.

[0150] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0151] Based on the same inventive concept, the embodiment of the present application also provides a video processing device for implementing the above-mentioned video processing method. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above-mentioned method, so the specific limitations in one or more video processing device embodiments provided below can refer to the limitations on the video processing method above, and will not be repeated here.

[0152] In an exemplary embodiment, Figure 4 As shown, a video processing device 400 is provided, which is applied to a video processing chip. The processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0. The device includes:

[0153] The determination module 401 is used to determine the target processing unit applicable to the target configuration table loaded into the current target RAM during the display process of the video frame; the target RAM is the unused RAM in the N+1 RAMs.

[0154] The adjustment module 402 is used to adjust the address pointed to by the target processing unit so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM.

[0155] The reading module 403 is used to read the target configuration table loaded in the current target RAM pointed to by the target processing unit, and display the video frame according to the target configuration table.

[0156] In some embodiments, the determination module is also used to read the value of the first register during the video frame start interrupt period of the current video frame; the value of the first register is used to indicate whether the target RAM at that time is successfully loaded into the target configuration table; if the value of the first register indicates that the loading is successful, the value of the second register is read, and the target processing unit is determined from the N processing units according to the value of the second register.

[0157] In some embodiments, the device also includes a loading module for obtaining a target configuration table in response to a configuration switching instruction, and loading the target configuration table into the current target RAM. After successful loading, the value setting of the first register is adjusted, and the adjusted value of the first register indicates successful loading.

[0158] In some embodiments, the adjustment module is further used to adjust the value of the first register so that the adjusted value of the first register indicates that the loading was not successful.

[0159] In some embodiments, the device also includes a loading module for checking the status of the current target RAM in response to a configuration switching instruction; if the status of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, then obtaining a corresponding target configuration table and loading the target configuration table into the current target RAM.

[0160] In some embodiments, the determination module is also used to check the state of the current target RAM when the preset interruption time of the video frame of any video is reached; if the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, determine the target processing unit applicable to the target configuration table loaded in the current target RAM.

[0161] In some embodiments, the determination module is also used to determine the target processing unit to which the target configuration table loaded into the target RAM is applicable based on the state of the target RAM at that time if the state of the target RAM at that time indicates that the data in the target RAM is valid; the adjustment module is also used to wait for the preset interrupt time of the video frame associated with the target processing unit, and adjust the address pointed to by the target processing unit when the preset interrupt time of the video frame associated with the target processing unit is reached.

[0162] In some embodiments, the adjustment module is further used to update the state of the next target RAM, so that the state of the next target RAM indicates that the data in the next target RAM is invalid and needs to be updated.

[0163] Each module in the above video processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0164] In an exemplary embodiment, a video processing chip is provided, comprising N+1 RAMs and N processing units, wherein any processing unit is respectively connected to the N+1 RAMs via a multi-way switch, where N is a positive integer greater than 0, and the video processing chip is used to implement the video processing method mentioned in the above embodiment.

[0165] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal or a server. The internal structure diagram thereof may be as follows: Figure 5 As shown. The computer device includes a video processing chip, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The video processing chip includes a processor and a processing module. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a video processing method is implemented.

[0166] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0167] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0168] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0169] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0170] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0171] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0172] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0173] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A video processing method, characterized in that: Applied to a video processing chip, the processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0; the method includes: In the display process of the video frame, in response to the configuration switching instruction, the state of the current target RAM is checked; if the state of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, a corresponding target configuration table is obtained and the target configuration table is loaded into the current target RAM; When the preset interruption time of the video frame of any video channel is reached, the state of the current target RAM is checked; if the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, the target processing unit applicable to the target configuration table loaded in the current target RAM is determined; the target RAM is an unused RAM in the N+1 RAMs; the address pointed to by the target processing unit is adjusted so that the target processing unit points to the current target RAM, and the RAM originally pointed to by the target processing unit is updated to the next target RAM; The target configuration table loaded into the current target RAM pointed to by the target processing unit is read, and the video frame is displayed according to the target configuration table.

2. The method according to claim 1, characterized in that The step of determining the target processing unit to which the target configuration table loaded into the target RAM is applicable comprises: Reading the value of the first register during the video frame start interruption period of the current video frame; the value of the first register is used to indicate whether the target RAM at that time is successfully loaded into the target configuration table; If the representation of the first register is loaded successfully, the value of the second register is read, and the target processing unit is determined from the N processing units according to the value of the second register.

3. The method according to claim 2, characterized in that Before determining the target processing unit to which the target configuration table loaded into the target RAM is applicable, the method further includes: In response to the configuration switching instruction, a target configuration table is obtained, and the target configuration table is loaded into the current target RAM. After the loading is successful, the value of the first register is adjusted, and the adjusted value of the first register indicates that the loading is successful.

4. The method according to claim 2, characterized in that: After adjusting the address pointed to by the target processing unit, the method further includes: The value of the first register is adjusted so that the adjusted value of the first register indicates that the loading is unsuccessful.

5. The method according to claim 1, characterized in that The step of determining the target processing unit to which the target configuration table loaded into the target RAM is applicable comprises: If the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, determining the target processing unit to which the target configuration table loaded in the current target RAM is applicable; The adjusting the address pointed to by the target processing unit comprises: Waiting for a preset interruption time of the video frame associated with the target processing unit, and when the preset interruption time of the video frame associated with the target processing unit is reached, adjusting the address pointed to by the target processing unit.

6. The method according to claim 1 or 5, characterized in that: After adjusting the address pointed to by the target processing unit, the method further includes: The state of the next target RAM is updated so that the state of the next target RAM indicates that the data in the next target RAM is invalid and needs to be updated.

7. A video processing device, characterized in that: Applied to a video processing chip, the processing module in the video processing chip includes N+1 RAMs and N processing units, where N is a positive integer greater than 0; the device includes: A determination module, used for checking the state of the current target RAM in response to the configuration switching instruction during the display process of the video frame; if the state of the current target RAM indicates that the data in the target RAM is invalid and needs to be updated, obtaining a corresponding target configuration table and loading the target configuration table into the current target RAM; When the preset interruption time of the video frame of any video channel is reached, the state of the current target RAM is checked; if the state of the current target RAM indicates that the data in the target RAM is valid, then based on the state of the current target RAM, the target processing unit to which the target configuration table loaded in the current target RAM is applicable is determined; the target RAM is an unused RAM in the N+1 RAMs; An adjustment module, used for adjusting the address pointed to by the target processing unit, so that the target processing unit points to the target RAM of the current time, and the RAM originally pointed to by the target processing unit is updated to the target RAM of the next time; The reading module is used to read the target configuration table loaded into the current target RAM pointed to by the target processing unit, and display the video frame according to the target configuration table.

8. A video processing chip, characterized in that: It comprises N+1 RAMs and N processing units, any of the processing units are connected to the N+1 RAMs respectively through a multi-way switch, N is a positive integer greater than 0, and the video processing chip is used to implement the method as described in any one of claims 1 to 6.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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