A memristive ion channel neuromorphic circuit

Abstract

The present invention relates to the field of neuromorphic circuit technology, and in particular to a memristor ion channel neuromorphic circuit, comprising: a voltage-controlled second-order local active memristor W, a DC bias voltage E, a capacitor C M and the sinusoidal excitation signal I ext , a voltage-controlled second-order local active memristor W connected in series with a DC bias voltage E as an ion channel, and a capacitor C M As a neuronal lipid bilayer, it regulates the sinusoidal excitation signal I ext The current amplitude produces periodic six-burst discharge, chaotic spike discharge and periodic four-spike discharge behaviors. The present invention designs a memristive ion channel type neuromorphic circuit, which involves the memristive expression problem of ion channels in biological neurons, and then realizes it through hardware circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of neuromorphic circuits, and in particular to a memristive ion channel type neuromorphic circuit. Background Art

[0002] Neurons are the most basic information processing and integration units of biological nervous systems. They are sensitive to external stimuli and can produce different discharge activities in complex electrophysiological environments, thereby realizing functions such as information transmission and cognitive behavior regulation. So far, the exploration of neuroscience has not been able to accurately analyze the mechanism of brain information processing and cognitive function. Therefore, it is necessary to propose neuromorphic circuits that can effectively simulate the electrophysiological characteristics of neurons.

[0003] Ion channels are protein channels on the neuron membrane, and their switching mechanism is crucial to the electrophysiological process of neurons. Local active memristors have the characteristics of amplifying small fluctuations and inducing action potentials in the local active region, making them natural candidates for building neuromorphic circuits; existing second-order local active memristors are relatively complex and often contain modules such as hyperbolic tangent functions that are not conducive to integration. Summary of the invention

[0004] In view of the shortcomings of existing circuits, the present invention proposes a circuit with a simple structure that only contains partial product terms and addition and subtraction terms, which is used to analyze and simulate the electrical activities of biological neurons in different electrophysiological environments, and to design a memristive ion channel type neuromorphic circuit, which involves the problem of memristive expression of ion channels in biological neurons, and then implements it through hardware circuits.

[0005] The technical solution adopted by the present invention is: a memristor ion channel type neuromorphic circuit comprises: a voltage-controlled second-order local active memristor W, a DC bias voltage E, a capacitor C M and the sinusoidal excitation signal I ext , the second-order local active memristor W is connected in series with the DC bias voltage E and the two ends are connected to the capacitor C M In parallel, the voltage-controlled second-order local active memristor W is connected in series with the DC bias voltage E as the ion channel, and the capacitor C M As a neuronal lipid bilayer, it regulates the sinusoidal excitation signal I ext The current amplitude produces periodic six-burst discharge, chaotic spike discharge and periodic four-spike discharge behaviors.

[0006] As a preferred embodiment of the present invention, the voltage-controlled second-order local active memristor W comprises: a first integral channel, a second integral channel and a floating module, and the first integral channel, the second integral channel and the floating module are electrically connected.

[0007] As a preferred embodiment of the present invention, the first integration channel includes: resistors R1 to R3, an operational amplifier UA , capacitor C1 and multiplier M3, U A The reverse input end is connected to one end of R1, R2, R3, and C1 respectively, and the other end of C1 is connected to U A The output end of R1 is connected to the output end of M3, and the input end of M3 is connected to the other end of R2 and U A The output terminal is connected.

[0008] As a preferred embodiment of the present invention, the second integration channel includes: resistors R4 to R6, an operational amplifier U B , capacitor C2 and multiplier M4, U B The reverse input end is connected to one end of R4, R5, R6, and C2 respectively, and the other end of C2 is connected to U B The output end of R4 is connected to the output end of M4, and the input end of M4 is connected to the other end of R5 and U B The output terminal is connected.

[0009] As a preferred embodiment of the present invention, the floating module includes: operational amplifiers U1 to U4, resistors R W , R W1 , R W2 , R M , multipliers M1, M2 and inverse adder N1, the same-direction input end of U1 is connected to the output end Z of U3, the output end W of U1 is connected to one input end of M2, the other end of R3 and the other end of R6 respectively, the output end Z of U1 is connected to R W1 Connect to ground after connection; the reverse input terminal of U1 and the reverse input terminal of U2 are connected in series with R W , the output terminal Z of U2 and R W2 The same-direction input of U2 is connected to the output terminal Z of U4, and the output terminal W of U2 is connected to the other input terminal of M4 and the other input terminal of M3 respectively; the same-direction input of U3 is connected to the output terminal of M2, and the reverse input terminal of U3 is connected in series with the reverse input terminal of U4. M The other input end of M2 is connected to the output end of the reverse adder N1, and the two input ends of the reverse adder N1 are connected to U B The output end of M1 is connected to the output end of U A The output end of R2, the other end of C1 and the other end of M3 are connected, and the other end of M1 is connected to U B The output end of , the other end of R5, the other end of C2 and the other end of the input of M4 are connected.

[0010] As a preferred embodiment of the present invention, the mathematical expression of the memristive ion channel neuromorphic circuit is:

[0011]

[0012] Where v is the system state variable; C M is the capacitance; C1 and C2 are the integral capacitances; I ext is a sinusoidal excitation signal; R1, R2, R3 are resistors of the first integration circuit; R4, R5, R6 are resistors of the second integration circuit; E is a DC bias voltage; is the internal state variable of the memristor; g1, g2, g3, and g4 are the gains of multipliers M1 to M4 respectively.

[0013] As a preferred embodiment of the present invention, the mathematical expression of the voltage-controlled second-order local active memristor W is:

[0014]

[0015] In the formula, i M and v M are the current flowing through the memristor and the input voltage respectively; g1, g2, g3, and g4 are the gains of multipliers M1 to M4 respectively; is the internal state variable of the memristor; R1, R2, R3 are the resistors of the first integration circuit; R4, R5, R6 are the resistors of the second integration circuit.

[0016] As a preferred embodiment of the present invention, the operational amplifier U 1- The model of U4 is: AD844AN.

[0017] As a preferred embodiment of the present invention, the operational amplifier U A and U B The model is: AD711JN.

[0018] As a preferred implementation of the present invention, the model of the analog multipliers M1-M4 is: AD633JN.

[0019] Beneficial effects of the present invention:

[0020] 1. The circuit structure of the present invention is simple. By adjusting the amplitude of the excitation current, the memristive ion channel neuromorphic circuit can present complex discharge behaviors such as periodic six-burst discharge, chaotic spike discharge and periodic four-spike discharge. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The main circuit structure schematic diagram;

[0022] Figure 2 It is a circuit diagram of a voltage-controlled second-order local active memristor;

[0023] Figure 3 For different parameter settings, about Im Numerical simulation diagram of burst discharge and spike discharge;

[0024] Figure 4 f = 220 Hz, R M =0.5kΩ, I m The experimental verification results at 0.055mA;

[0025] Figure 5 f = 1600Hz, R M =1kΩ, I m The experimental verification results at 0.27mA;

[0026] Figure 6 f = 1600Hz, R M =1kΩ, I m The experimental verification results are shown below when the current is 0.3 mA. DETAILED DESCRIPTION

[0027] The present invention is further described below in conjunction with the accompanying drawings and embodiments. This figure is a simplified schematic diagram, which only illustrates the basic structure of the present invention in a schematic manner, and therefore it only shows the components related to the present invention.

[0028] like Figure 1 As shown, a memristor ion channel type neuromorphic circuit includes: a voltage-controlled second-order local active memristor W, a capacitor C M , a DC bias voltage E and a sinusoidal excitation signal I ext ; The voltage-controlled second-order local active memristor W is connected in series with the DC bias voltage E as a branch, and the capacitor C M As a branch, through the voltage-controlled second-order local active memristor W and capacitor C M The ion channels and lipid bilayer membranes of neurons are characterized separately to simulate the dynamic behavior of memristive ion channel-dependent neurons.

[0029] Figure 1 The main circuit of the memristor ion channel neuromorphic circuit is characterized by connecting a voltage-controlled second-order local active memristor W in series with a DC bias voltage E. Figure 1 The ion channel in the M Characterization Figure 1 The lipid bilayer membrane of neurons ext As an external stimulus, a memristive ion channel type neuromorphic circuit was constructed; Figure 1 Each port is connected in sequence, I ext Input the sinusoidal excitation signal, E selects the appropriate bias voltage, Figure 1 The memristive ion channel-based neuromorphic circuit shown can exhibit complex discharge behaviors.

[0030] like Figure 2 ,The implementation circuit of the voltage-controlled second-order local active memristor includes: two integral channels, four analog multipliers, an inverting adder and a floating ground module constituting the local active memristor;

[0031] Among them, the first integral channel The implementation includes analog multiplier M3 output Operational amplifier U A Output And the voltage output terminal v of the operational amplifier U1 M ; Output of analog multiplier M3 Operational amplifier U A Output and the voltage output terminal v of the operational amplifier U1 M Connect to U through R1, R2, R3 respectively. A The inverting input terminal of the operational amplifier U A The capacitor C1 is connected in parallel between the inverting input and output terminals, the positive input terminal is grounded, and the output terminal is

[0032] Second integration channel The implementation includes analog multiplier M4 output Operational amplifier U B Output And the voltage output terminal v of the operational amplifier U1 M ; Output of analog multiplier M4 Operational amplifier U B Output and the voltage output terminal v of the operational amplifier U1 M Connect to U through R4, R5, R6 respectively B The inverting input terminal of the operational amplifier U B The capacitor C2 is connected in parallel between the inverting input and output terminals, the positive input terminal is grounded, and the output terminal is The two input terminals of the analog multiplier M1 are connected to U A Output and U B Output connected, the analog multiplier M1 outputs at the output The two input terminals of the inverting adder N1 and the output terminal of the analog multiplier M1 and U B Output Connect and output at the output The two input terminals of the analog multiplier M2 and the output terminal v of U1 M and the output of N1 connected, the analog multiplier M2 outputs at the output The two input terminals of analog multiplier M3 and the output terminal of U2 -v M and U A Output Connected, output at the output The two input terminals of analog multiplier M4 are connected to the output terminal of U2 -v M and U B Output Connected, output at the output

[0033] The floating module constituting the local active memristor includes operational amplifiers U1, U2, U3, and U4. The positive input terminal of U1 is connected to the Z terminal of U3, the positive input terminal of U2 is connected to the Z terminal of U4, the positive input terminal of U3 is connected to the output terminal of M2, and the positive input terminal of U4 is grounded; the inverting input terminal of U1 is connected in series with the inverting input terminal of U2 through a resistor R W , a resistor R is connected in series between the inverting input of U3 and the inverting input of U4 M ; U1’s Z terminal passes through resistor R W1 Ground, U1 voltage output W output v M Connect R3, R6 and one input terminal of M3 respectively; the Z terminal of U2 is connected through the resistor R W2 Ground, U2 voltage output W output -v M Connected to one input terminal of M3 and M4 respectively.

[0034] Model building: The present invention uses voltage-controlled second-order local active memristors and capacitors to characterize the ion channels and lipid bilayer membranes of neurons and construct a memristor ion channel type neuromorphic circuit.

[0035] The voltage-controlled second-order local active memristor contains a The capacitances C1 and C2, therefore, the mathematical expression of the second-order local active memristor is:

[0036]

[0037] In the formula, i M and v M are the current flowing through the memristor and the input voltage respectively; g1, g2, g3, and g4 are the gains of multipliers M1 to M4 respectively; is the internal state variable of the memristor.

[0038] exist Figure 1 In the , the memristor neuron circuit mainly has a capacitor and two integral channels. According to Kirchhoff's circuit law and the electrical characteristics of circuit components, Figure 1 The differential equation for the circuit shown can be expressed as:

[0039]

[0040] In the formula, v, and are the three state variables of the system; C M is the capacitance; C1 and C2 are the integral capacitances; I ext is an external sinusoidal excitation signal, which can be described as:

[0041] I ext =I m sin(2πft) (4)

[0042] Among them, the control variable I m represents amplitude and f represents frequency.

[0043] It is worth noting that when the amplitude I m , frequency f and resistance R M Within a reasonable range, model (3) can exhibit complex burst discharge and spike discharge behaviors.

[0044] Numerical simulation: frequency I m As a variable control parameter, the MATLAB ODE45 algorithm is used to conduct numerical research on memristive ion channel neuromorphic circuits; Figure 3 The amplitude I is plotted in different cases. m Discharge timing diagram, when R M =0.5kΩ, f=220Hz, I m =0.055mA shows six bursts of discharge; when R M =1kΩ, f=1600Hz, I m =0.27mA shows chaotic spike discharge; I m =0.3mA shows a periodic four-peak discharge. m Under these circumstances, it was found that the electrical activity of neurons had a significant correlation with external stimuli, which indicates the responsiveness and adaptability of neurons to external stimuli.

[0045] Take C M =100nF; C1=C2=50nF; R1=1kΩ; R2=2kΩ; R3=20kΩ; R4=10kΩ; R5=2kΩ; R6=1kΩ; g1=g3=g2=g4=1V -1 ; R W =R W1 =R W2 =10kΩ; E=0.3V.

[0046] U 1-The model of the precision operational amplifier of U4 is: AD844AN; A and U B The model of the operational amplifier is: AD711JN; the model of the analog multiplier M1-M4 is: AD633JN.

[0047] Hardware implementation and experimental verification: This design uses AD844AN precision operational amplifier, AD711JN operational amplifier and AD633JN analog multiplier with a supply voltage of ±15V. Other discrete components are precision adjustable resistors, chip resistors and through-hole capacitors. During the experiment, a Tektronix TDS 3054C digital phosphor oscilloscope is used to capture the experimental results. For the amplitude I m Adjust the other circuit parameters as shown above. In the hardware circuit experiment, adjust the amplitude of the external signal source I m , when I m When the current is 0.055mA, 0.27mA, and 0.3mA respectively, the timing diagrams of the captured membrane voltage v discharge are as follows Figure 4 , Figure 5 and Figure 6 As shown; ignoring some minor differences between the numerical simulation and the hardware circuit experiment caused by calculation errors and parasitic circuit parameters, the experimental results are basically consistent with the numerical simulation; therefore, a memristive ion channel type neuromorphic circuit constructed by the present invention has a scientific theoretical basis, and the designed analog circuit unit will provide a reference value for the hardware experimental study of the dynamic behavior of memristive ion channel type neurons.

[0048] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A memristive ion channel neuromorphic circuit, characterized in that: include: Voltage-controlled second-order local active memristor W, DC bias voltage E, capacitor C M and the sinusoidal excitation signal I ext , a voltage-controlled second-order local active memristor W connected in series with a DC bias voltage E as an ion channel, and a capacitor C M As a neuronal lipid bilayer, it regulates the sinusoidal excitation signal I ext The current amplitude produces periodic six-burst discharge, chaotic spike discharge and periodic four-spike discharge behaviors; The voltage-controlled second-order local active memristor W comprises: a first integral channel, a second integral channel and a floating module, wherein the first integral channel, the second integral channel and the floating module are electrically connected; The first integration channel includes: resistors R1 to R3, operational amplifier U A , capacitor C1 and multiplier M3, U A The reverse input end is connected to one end of R1, R2, R3, and C1 respectively, and the other end of C1 is connected to U A The output end of R1 is connected to the output end of M3, and the input end of M3 is connected to the other end of R2 and U A The output terminal connection of The second integration channel includes: resistors R4 to R6, operational amplifier U B , capacitor C2 and multiplier M4, U B The reverse input end is connected to one end of R4, R5, R6, and C2 respectively, and the other end of C2 is connected to U B The output end of R4 is connected to the output end of M4, and the input end of M4 is connected to the other end of R5 and U B The output terminal connection of The floating module includes: operational amplifiers U1 to U4, resistors R W , R W1 , R W2 , R M , multipliers M1, M2 and inverse adder N1, the same-direction input end of U1 is connected to the output end Z of U3, the output end W of U1 is connected to one input end of M2, the other end of R3 and the other end of R6 respectively, the output end Z of U1 is connected to R W1 Connect to ground after connection; the reverse input terminal of U1 and the reverse input terminal of U2 are connected in series with R W , the output terminal Z of U2 and R W2 The same-direction input of U2 is connected to the output terminal Z of U4, and the output terminal W of U2 is connected to the other input terminal of M4 and the other input terminal of M3 respectively; the same-direction input of U3 is connected to the output terminal of M2, and the reverse input terminal of U3 is connected in series with the reverse input terminal of U4. M The other input end of M2 is connected to the output end of the reverse adder N1, and the two input ends of the reverse adder N1 are connected to U B The output end of M1 is connected to the output end of U A The output end of R2, the other end of C1 and the other end of M3 are connected, and the other end of M1 is connected to U B The output end of , the other end of R5, the other end of C2 and the other end of the input of M4 are connected.

2. The memristive ion channel neuromorphic circuit according to claim 1, characterized in that: The mathematical expression of the memristive ion channel neuromorphic circuit is: Where v is the system state variable; C M is the capacitance; C1 and C2 are the integral capacitances; I ext is a sinusoidal excitation signal; R1, R2, R3 are resistors of the first integration circuit; R4, R5, R6 are resistors of the second integration circuit; E is a DC bias voltage; is the internal state variable of the memristor; g1, g2, g3, and g4 are the gains of multipliers M1 to M4 respectively.

3. The memristive ion channel neuromorphic circuit according to claim 1, characterized in that: The mathematical expression of the voltage-controlled second-order local active memristor W is: In the formula, i M and v M are the current flowing through the memristor and the input voltage respectively; g1, g2, g3, and g4 are the gains of multipliers M1 to M4 respectively; is the internal state variable of the memristor; R1, R2, R3 are the resistors of the first integration circuit; R4, R5, R6 are the resistors of the second integration circuit.

4. The memristive ion channel neuromorphic circuit according to claim 1, characterized in that: Operational amplifier U A and U B The model is: AD711JN.

5. The memristive ion channel neuromorphic circuit according to claim 1, characterized in that: Operational amplifier U 1- The model of U4 is: AD844AN.

6. The memristive ion channel neuromorphic circuit according to claim 1, characterized in that: The model of the analog multiplier M1-M4 is: AD633JN.

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