Vehicle instrument image display test system, method, device and electronic equipment

Abstract

The present disclosure relates to an image testing system and method for vehicle instruments, which are applied to vehicles. The system includes a host computer, an instrument electronic control unit, and an image acquisition card. The host computer sends a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case. The host computer is connected to the image acquisition card via a data connection line, which is used to send an acquisition instruction to the image acquisition card so that the image acquisition card acquires the image of the test case from the instrument to be tested based on the acquisition instruction and sends it to the host computer. The host computer compares the image of the test case acquired by the image acquisition card with the template image of the test case, and obtains the test result of the image display function of the instrument to be tested based on the comparison result. The present disclosure can improve the accuracy and efficiency of the image display test of vehicle instruments.

Description

Technical Field

[0001] The present disclosure relates to the field of vehicle testing technology, and in particular to an instrument image display testing system, method, device and electronic equipment. Background Art

[0002] Vehicle instruments are used to display vehicle status information and can also be used to display icons and pages for human-computer interaction. Before a vehicle leaves the factory, the image display function of the vehicle instrument needs to be tested. Usually, the test case is sent to the instrument electronic control unit to trigger the instrument screen to display the corresponding image. Then the tester manually compares the image displayed on the instrument screen with the preset template image to determine whether the instrument's image display function is normal.

[0003] However, the above test methods are too dependent on manual judgment, which is highly subjective and prone to errors, resulting in a low test accuracy. In addition, in the case of a large test workload, manually comparing a large number of images will result in a long test cycle and low efficiency. Summary of the invention

[0004] The embodiment of the present disclosure provides an image display test system for a vehicle instrument, which can improve the accuracy and efficiency of testing the image display function of the vehicle instrument, so as to at least partially solve the above technical problems.

[0005] In order to achieve the above-mentioned object, according to a first aspect of the present disclosure, there is provided an image display test system for a vehicle instrument, which is applied to a vehicle and includes a host computer, an instrument electronic control unit, and an image acquisition card, wherein:

[0006] The host computer is connected to the instrument electronic control unit through the vehicle bus, and the instrument electronic control unit is connected to the instrument to be tested. The host computer is used to send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case;

[0007] The host computer is connected to the image acquisition card via the data connection line, and is used to send an acquisition instruction to the image acquisition card;

[0008] The image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction, and sends it to the host computer;

[0009] The host computer compares the image of the test case acquired by the image acquisition card with the template image of the test case, and obtains the test result of the image display function of the instrument to be tested according to the comparison result.

[0010] Optionally, the image acquisition card includes an FPGA unit, wherein the FPGA unit is used to acquire the image of the test case from the instrument under test, and upload the acquired image of the test case to the host computer.

[0011] Optionally, the FPGA unit includes a communication module, a data frame processing module, a data parsing module, a scheduling module, a packaging module and a display cache module, wherein:

[0012] The communication module is used to receive the acquisition instruction of the host computer, and send the data frame of the image of the test case to the host computer;

[0013] The data frame processing module is used to verify the data frame, send the successfully verified data frame to the data analysis module, and send the verification error information of the failed verification to the encapsulation module;

[0014] The data parsing module is used to parse the valid information of the data frame and send the valid information of the data frame to the display buffer module;

[0015] The display cache module is used to parse the valid information of the data frame, sample the data frame and cache it in an asynchronous queue, read and encapsulate the data frame of the asynchronous queue and send it to the scheduling module;

[0016] The data encapsulation module is used to encapsulate the version information of the FPGA unit, the verification error information, and the response information of the host computer to obtain encapsulation information, and send the encapsulation information to the scheduling module;

[0017] The scheduling module is used to sort out the encapsulation information sent by the encapsulation module and the data frames of the asynchronous queue sent by the display cache module to obtain a data set, and send the data set to the communication module.

[0018] Optionally, the FPGA unit further includes a clock management module, and the clock management module is used to manage the first clock, the second clock and the pixel clock, wherein:

[0019] The first clock is a clock shared by the communication module, the data frame processing module, the scheduling module, the encapsulation module and the display buffer module;

[0020] The second clock is a clock for synchronizing the FPGA unit with the host computer; the second clock is obtained by reverse processing of the first clock;

[0021] The pixel clock is a clock sent by the instrument electronic control unit to the display cache module and the data analysis module of the FPGA unit, so that the FPGA unit collects the image displayed by the instrument under test based on the pixel clock.

[0022] Optionally, the vehicle instrument image display test system further includes a power supply, and the power supply supplies power to the instrument electronic control unit and the image acquisition card.

[0023] According to a second aspect of the present disclosure, there is provided a vehicle instrument image display test method, which is applied to the host computer as described above, and the method comprises:

[0024] Sending a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument to be tested to display an image of the test case;

[0025] Sending an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument to be tested based on the acquisition instruction;

[0026] Receive the image of the test case and compare it with the template image of the test case to obtain the test result of the image display function of the instrument under test. According to the third aspect of the present disclosure, a maximum exclusive right of the protected subject is also provided, including the second minimum exclusive right of the protected subject as described above.

[0027] Optionally, the receiving the image of the test case and comparing it with the template image of the test case to obtain the test result of the image display function of the instrument under test includes:

[0028] Acquire a first pixel of the image of the test case;

[0029] Acquire a second pixel of the template image of the test case;

[0030] The pixel information of each of the first pixels is compared with the pixel information of each of the second pixels, and the test result is determined according to the comparison result of the pixel information of the first pixels and the pixel information of the second pixels.

[0031] Optionally, the method further comprises:

[0032] Sending a basic clock signal to the image acquisition card, so that a phase-locked loop circuit of the image acquisition card receives and processes the basic clock signal, and outputs a first clock and a second clock that are opposite to each other;

[0033] The electronic control unit of the instrument is controlled to send a pixel clock signal to the image acquisition card, so that the global clock buffer of the image acquisition card receives and processes the pixel clock signal and outputs a pixel clock of a preset frequency.

[0034] According to a third aspect of the present disclosure, there is provided an image display test device for a vehicle instrument, which is applied to a host computer of the image display test system for the vehicle instrument as described above, and the device comprises:

[0035] A test request unit, used for sending a test case to the instrument electronic control unit, so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card, so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case;

[0036] An image acquisition unit, used for sending an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction;

[0037] The instrument testing unit is used to receive the image of the test case and compare it with the template image of the test case to obtain the test result of the image display function of the instrument to be tested.

[0038] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a memory on which a computer program is stored; and a processor for executing the computer program in the memory to implement the steps of the image display test method for a vehicle instrument as described above.

[0039] In the image display test system of the vehicle instrument of the disclosed embodiment, through the above-mentioned technical scheme, it is possible to use an image acquisition card to acquire the image of the test case sent by the instrument electronic control unit from the instrument to be tested, and then send the acquired image of the test case to the host computer, and compare the image of the test case with the template image pixel by pixel. The entire test process does not require manual image comparison, which not only improves the degree of automation of the test, but also eliminates the subjective factors of manual image comparison, thereby improving the accuracy and efficiency of testing the image display function of the vehicle instrument.

[0040] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0042] In order to more completely understand the present disclosure and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0043] Figure 1 It is a schematic diagram of an instrument image display test system of an existing vehicle;

[0044] Figure 2 is a structural schematic diagram of a vehicle instrument image display test system provided in an exemplary embodiment of the present disclosure;

[0045] Figure 3 is a schematic diagram of data interaction between a host computer and an FPGA unit provided in an exemplary embodiment of the present disclosure;

[0046] Figure 4 is a schematic diagram of the structure of a top-level module of an FPGA unit provided in an exemplary embodiment of the present disclosure;

[0047] Figure 5 is a schematic diagram of a clock network of an FPGA unit provided in an exemplary embodiment of the present disclosure;

[0048] Figure 6 is a flow chart of a vehicle instrument image display test method provided in an exemplary embodiment of the present disclosure;

[0049] Figure 7 is another flowchart of a vehicle instrument image display test method provided in an exemplary embodiment of the present disclosure;

[0050] Figure 8 is a structural schematic diagram of an image display testing device for a vehicle instrument provided in an exemplary embodiment of the present disclosure;

[0051] Fig. 9 is a structural block diagram of an electronic device provided in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0053] In the related art, the image display function of the vehicle instrument needs to be tested before the vehicle leaves the factory. Figure 1 As shown in the figure, the existing test process is usually that the host computer first sends the test case to the instrument electronic control unit (ECU) connected to the instrument to be tested, triggering the screen of the instrument to be tested to display the corresponding image. Then, the tester manually compares whether the image displayed on the instrument screen is consistent with the preset template image to determine whether the image display function of the instrument is normal. However, the above test process is completely manually operated by the tester, and the image comparison is too dependent on manual judgment, which is highly subjective and prone to errors. For example, the human eye cannot compare each pixel in the image. For example, when the instrument to be tested displays different pictures, the human eye cannot track the switching and subtle changes of the picture in time, resulting in a low test accuracy. In addition, in the face of a large test workload, the manual comparison of a large number of images is slow, which will lead to a long cycle, low efficiency, and high labor costs for the entire test.

[0054] In view of this, the embodiments of the present disclosure provide an image display test system, method, device and electronic device for a vehicle instrument, which can use an image acquisition card to acquire images of test cases sent by an electronic control unit of the instrument to be tested, and then send the acquired images of the test cases to a host computer, which compares the images of the test cases with the template image pixel by pixel. The entire test process does not require manual image comparison, which not only improves the degree of automation of the test, but also eliminates the subjective factors of manual image comparison, thereby improving the accuracy and efficiency of testing the image display function of the vehicle instrument. The present disclosure is explained in conjunction with specific embodiments below.

[0055] See also Figure 2 , Figure 2 The schematic diagram of the structure of the instrument image display test system of the vehicle provided in the exemplary embodiment of the present disclosure is shown in FIG. The instrument image display test system of the vehicle is applied to the vehicle and includes a host computer, an instrument electronic control unit, and an image acquisition card.

[0056] The host computer refers to a computer or related equipment used for data processing, analysis, display and control. In the image test scene of the vehicle instrument in the embodiment of the present disclosure, the host computer can run software programs, send instructions and messages, and interact and communicate with various hardware devices in the scene.

[0057] The instrument electronic control unit is a key component for controlling and managing electronic systems on automobiles or other devices. In the image test scenario of the vehicle instrument in the embodiment of the present disclosure, the instrument electronic control unit can achieve precise control of the device by processing input signals and outputting control signals. For example, the instrument electronic control unit can receive an image generation instruction from a host computer, and then send an image signal corresponding to the image generation instruction to the screen of the vehicle instrument to generate a corresponding image on the screen of the vehicle instrument.

[0058] The image acquisition card is used to capture and digitize external image signals and generate image data that can be processed and stored by a computer or other processing device. In the image test scenario of the vehicle instrument in the embodiment of the present disclosure, the image acquisition card can receive and process the image signal sent by the instrument electronic control unit, and can also collect image data and upload it to the host computer for analysis.

[0059] In some embodiments, the host computer can be connected to the instrument electronic control unit through the vehicle bus, the instrument electronic control unit can be connected to the instrument to be tested, and the host computer can be used to send test cases to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case and sends the image signal to the image acquisition card, so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case.

[0060] Among them, the automotive bus refers to a data communication line based on a specific communication protocol specifically used for communication between electronic control units inside the vehicle, which can achieve fast and reliable data transmission. For example, the automotive bus can be a CAN bus, LIN bus, etc.

[0061] The instrument under test refers to the instrument equipment that needs to be tested for image display, usually the display instrument used for vehicle status data display, human-computer interaction and other functions. During the test, the electronic control unit can transmit the generated image signal to the instrument under test through the image acquisition card to drive the instrument under test to display the corresponding image.

[0062] Among them, the test case is the instruction and data used to verify the display function of the instrument under test. In the scenario disclosed in the present invention, the host computer can send test cases related to the operating status of the vehicle to the instrument electronic control unit. For example, the test case can be used to instruct the instrument electronic control unit to generate and display "an image of a speed of 60 km / h", "an image of a full fuel gauge", "an image of an engine fault indicator light", etc.

[0063] In some embodiments, the instrument electronic control unit can generate corresponding image signals according to the test cases sent by the host computer, and send the image signals to the image acquisition card. For example, the image signals can be RGB888, RGB666 and other signals. In some embodiments, after receiving the image signal from the instrument electronic control unit, the image acquisition card can digitize the image signal and perform necessary processing, and then transmit the processed image signal to the instrument under test through the image acquisition card, so that the instrument under test displays the corresponding test case image.

[0064] In some embodiments, the host computer may be connected to the image acquisition card via a data connection line to send acquisition instructions to the image acquisition card.

[0065] The data connection line can be USB3.0, Ethernet, dedicated data line, etc. The acquisition instruction is a command sent by the host computer to the image acquisition card to control the image acquisition card to perform a specific image acquisition task. The acquisition instruction can include starting or stopping image acquisition, setting acquisition parameters, etc.

[0066] In the specific implementation, the host computer can send specific acquisition instructions to the image acquisition card as needed. For example, the host computer can send an instruction to require the image acquisition card to start acquiring image signals from the instrument electronic control unit. The instruction can be transmitted to the image acquisition card through the data connection line. After receiving the acquisition instruction from the host computer, the image acquisition card starts to execute the corresponding image acquisition task, and the acquired image signal will be processed and converted into a format that can be read and analyzed by the host computer.

[0067] In some embodiments, the image acquisition card acquires the image of the test case from the instrument to be tested based on the acquisition instruction and sends it to the host computer. It can be understood that the display screen of the instrument to be tested can display the image of the test case generated by the instrument electronic control unit. In some embodiments, the image acquisition card can receive an image signal from the instrument to be tested and capture the image data displayed by the instrument to be tested. The image data can be a specific image, indicator or symbol on the display screen, such as the image of the vehicle speed mentioned above, the image of the fuel gauge status, etc. The image acquisition card processes and converts the acquired image signal, which can be converted into a digital format, and performs necessary preprocessing, such as denoising, enhancement, etc., to ensure the clarity and integrity of the image data. The processed image data is transmitted back to the host computer via a data connection line, so that the acquired high-quality image data can be quickly transmitted to the host computer for further processing and analysis.

[0068] In some embodiments, the host computer can compare the image of the test case collected by the image acquisition card with the template image of the test case, and obtain the test result of the image display function of the instrument to be tested according to the comparison result. For example, after the image acquisition card collects the image of the test case from the instrument to be tested, the image data can be transmitted to the host computer through the data connection line. After the host computer receives the image of the test case, it can store and process it. For example, the processing of the image may include, but is not limited to, format conversion, denoising, image enhancement, etc., to ensure the clarity and comparability of the image data.

[0069] Before image comparison, the host computer can load a pre-stored template image of the test case. The template image is a pre-defined correct display image for comparison with the acquired image. When performing image comparison, the host computer can compare the acquired image with the template image at the pixel level. For example, the pixel information such as the pixel value, color, brightness, and position of each pixel can be checked to determine the consistency of the two images. Based on the comparison results, the host computer can analyze the difference between the acquired image and the template image. For example, the host computer receives an image with a display speed of 60 km / h transmitted by the image acquisition card, and compares it with the pre-stored 60 km / h template image loaded by the host computer. If the image comparison results are consistent, it means that the image display function of the instrument to be tested is normal; if there is a difference in the image comparison results, it means that there may be a problem with the image display function of the instrument to be tested.

[0070] Through the above method, the host computer of the vehicle image display test system disclosed in the present invention can accurately and efficiently test and verify the image display function of the instrument under test by comparing the test case image captured by the image acquisition card with the template image, without the need for testers to perform manual comparison. The comparison result directly reflects whether the display of the instrument under test is normal, and can also provide reliable data support and analysis basis for system testing and improvement.

[0071] In some embodiments, the image acquisition card may include an FPGA unit, wherein the FPGA unit is used to acquire images of test cases from the instrument under test, and upload the acquired images of the test cases to a host computer.

[0072] In some embodiments, the FPGA unit can receive an image signal from the instrument to be tested. For example, the image signal can be visual information such as an image displayed by the instrument to be tested, the status of an indicator light, etc. In some embodiments, the FPGA unit can process the received image signal, such as decoding, filtering, denoising, etc., to ensure the clarity and stability of the signal. In some embodiments, the FPGA unit can convert the processed image signal into a digital format that can be recognized and processed by the host computer. In some embodiments, the FPGA unit can upload the collected image data to the host computer through the interface of the image acquisition card (such as USB, Ethernet, etc.).

[0073] like Figure 3 As shown, the FPGA unit may include a communication module, a data frame processing module, a data parsing module, a scheduling module, a packaging module and a display cache module.

[0074] Among them, the communication module can be a GPIF interface (General Purpose Interface) communication module, which is responsible for data communication between the FPGA unit and the external device. In some embodiments, the communication module can be used to receive the acquisition instructions of the host computer and send the data frame of the image of the test case to the host computer. Specifically, the host computer can be connected to the image acquisition card through a USB3.0 data connection line, and the communication module is used to realize the transmission and reception of instructions. For example, the instructions may include, but are not limited to, starting image acquisition, stopping acquisition, querying system status, etc. The communication module can be responsible for parsing and executing these instructions to control the operation of the image acquisition card. Once the image acquisition card acquires image data from the instrument display screen according to the acquisition instruction, the communication module can send the data frames of these images to the host computer, and the data frames can be encapsulated in a specific format and protocol to ensure integrity and accuracy during the transmission process.

[0075] like Figure 3As shown, the communication between the host computer and the FPGA unit is completed through the USB3.0 interface. As an example, the communication process can rely on the PHY chip of the CYUSB3014 of the host computer. The CYUSB3014 and the FPGA unit are connected through the GPIF interface of the communication module. The key tasks of the entire communication module can be divided into two parts. First, the host computer sends instructions to the CYUSB3014 chip through the USB. These instructions are received by the CYUSB3014 chip and passed to the FPGA through its slave FIFO (slave queue). The FPGA sends the pre-prepared data frame to the CYUSB3014 through the slave FIFO of the CYUSB3014, and finally transmits it to the connected host computer through the USB interface of the communication module. Through this structure, high-speed and reliable data transmission can be ensured, so that the host computer can effectively control and receive data from the FPGA unit.

[0076] Among them, the data frame processing module is a module that performs frame processing on the collected image data. For example, the frame processing may include frame division, frame synchronization and frame buffering of the image data. In some embodiments, the data frame processing module is used to verify the data frame, send the successfully verified data frame to the data parsing module, and send the verification error information of the failed verification to the encapsulation module. Specifically, the host computer instruction data frame received by the communication module can be subjected to frame header verification and CRC verification by the data frame processing module. If the verification is successful, the UOP / UID of the data part and the corresponding CRC verification correct flag can be sent to the encapsulation module, and the data frame part in the host computer can be written into the asynchronous queue, and the data frame in the asynchronous queue can be transmitted to the data parsing module for processing; if the verification fails, the data frame in the asynchronous queue can be cleared, and the error flag can be reported to the encapsulation module. Among them, the asynchronous queue can be an asynchronous FIFO (First In First Out) queue.

[0077] Among them, the data parsing module is a module that parses the data frame transmitted by the frame processing module. For example, data parsing may include decoding of image data, format conversion, and data extraction. In some embodiments, the data parsing module is used to parse the valid information of the data frame and send the valid information of the data frame to the display cache module. Specifically, the data parsing module can extract valid information such as UOP (operation code), UID (unique identifier), and UD (data) of the data frame. When an image acquisition instruction (UID=2) is detected, the corresponding display cache enable flag can be set, and the number of image frames and the interval time can be transmitted to the display cache module for further processing and use by the display cache module.

[0078] The display cache module is a module that caches and manages display-related data, such as image data cache, display control, and data update. In some embodiments, the display cache module is used to parse valid information of data frames, sample data frames and cache them in asynchronous queues, read and encapsulate data frames in asynchronous queues and send them to the scheduling module.

[0079] Among them, the data encapsulation module encapsulates the parsed image data and prepares to upload it to the host computer. For example, it may include encapsulation operations such as data packaging, adding header information and checksums. In some embodiments, the data encapsulation module is used to encapsulate the version information of the FPGA unit, the check error information, and the response information of the host computer to obtain the encapsulation information, and send the encapsulation information to the scheduling module. In some embodiments, the encapsulation module can receive instructions sent by the host computer and generate corresponding responses according to the content of the instructions. The instructions may include starting image acquisition, stopping acquisition, querying status, etc. The encapsulation module can ensure the accuracy and timeliness of the response so that the host computer can obtain feedback information that the system correctly executes the instructions.

[0080] Among them, the scheduling module is a module responsible for the task scheduling and resource management of the entire FPGA unit, for example, including the coordination between various modules and the management of data flows. In some embodiments, the scheduling module is used to organize the encapsulation information sent by the encapsulation module and the data frames of the asynchronous queue sent by the display cache module, obtain a data set, and send the data set to the communication module. Specifically, the scheduling module can receive data frames from two USBs, and the data frames of different channels come from different sources, for example, from the display cache module and the encapsulation module respectively.

[0081] The scheduling module is responsible for integrating and converging these data frames from different sources to ensure that they can be sent to the next processing stage in an orderly and correct manner, that is, output to the host computer or other required modules. It can be understood that since the two USBs may have different data transmission rates or data formats, the scheduling module can handle these differences to ensure that the data will not be lost or errors will occur during the transmission process. The scheduling module can buffer or adjust the order of the received data frames so that the subsequent processing modules can correctly process the data. Through the scheduling module, the overall performance and efficiency of the system can be optimized, data conflicts and blockages can be avoided, and smooth and stable data transmission can be ensured.

[0082] like Figure 4 As shown, Figure 4 is a schematic diagram of the structure of the top-level module of the FPGA unit provided in the exemplary embodiment of the present disclosure. It can be understood that since the FPGA unit of the image acquisition card can generally include multiple levels, such as the top level, the second level under the top level, the third level, and the bottom level, etc. For the top level, the top-level module can include multiple sub-modules, such as Figure 4 The USB data encapsulation module and the 32-bit CRC check module are both sub-modules of the encapsulation module. The data interaction flow of each sub-module in the top-level module of the FPGA unit is introduced below.

[0083] like Figure 4 As shown, the GPIF control module transmits the instruction information sent by the host computer to the image acquisition card. The instruction information may include the frame header, UOP / UID / valid length, UD data segment and CRC check part. Then the USB receiving top-level module is responsible for parsing the frame header and completing the CRC check, and passing the valid information of UOP / UID / UD to the USB data parsing module. Then the USB data parsing module passes the number of collected frames and interval configuration to the sample cache upload module according to the information in the UD, and passes the UOP information to the USB data encapsulation module. The USB data encapsulation module is responsible for completing the encapsulation response of the instruction, which means that the bottom layer has received the instruction, and the sample cache upload module can encapsulate and upload the image data collection. The above two data are gathered in the scheduling control top-level module, and then the scheduling control top-level module performs scheduling processing to convert the two data into one stream back to the GPIF control module.

[0084] like Figure 5 As shown, in some embodiments, the FPGA unit may further include a clock management module, which is used to manage the first clock, the second clock and the pixel clock. The clock management module is also called an OSC module or local_pll.

[0085] In some embodiments, the first clock may be a clock shared by the communication module, the data frame processing module, the scheduling module, the encapsulation module, and the display buffer module. Specifically, the first clock may be a high-frequency clock (e.g., clk_100m) with a frequency of 100 MHz, which is used as a shared clock for the communication module, the data frame processing module, the scheduling module, the encapsulation module, and the display buffer module.

[0086] In the specific implementation, the communication module can use the clk_100m clock as the clock signal for its operation, ensuring stable and high-speed communication with the host computer. The data frame processing module can use the clk_100m clock to synchronously receive and process data frames from the communication module, such as frame header verification, CRC verification and other operations. The scheduling module can use the clk_100m clock to coordinate and manage data streams from different modules to ensure the orderly convergence and transmission of data. The encapsulation module can use the clk_100m clock to generate and manage the response and status information of the system, including the response to the host computer instructions and the upload of global status information. The display cache module can use the clk_100m clock to process and store the image data obtained from the image acquisition module, as well as cache and output the image data according to system requirements.

[0087] In some embodiments, the second clock may be a clock (eg, clk_100m_180) for synchronizing the FPGA unit with the host computer, and the second clock is obtained by reverse processing of the first clock.

[0088] The reverse processing generally refers to the phase reversal of the first clock to generate a new clock signal. In the actual application of the scenario disclosed herein, the second clock clk_100m_180 can be used to synchronize data transmission, for example, in a system requiring high speed and precise timing control, to ensure that the operation of each component of the system is performed at a predetermined timing and frequency, thereby avoiding data loss or timing conflict problems.

[0089] In some embodiments, the pixel clock is a clock (eg, pclk_30m) sent by the instrument electronic control unit to the display cache module and the data analysis module of the FPGA unit, so that the FPGA unit collects the image displayed by the instrument under test based on the pixel clock.

[0090] The pixel clock pclk_30m may be a clock signal output from the instrument electronic control unit, with a frequency of 30 MHz, and its function is to provide a time reference for the FPGA unit to ensure accurate acquisition and processing of the display image of the instrument to be tested.

[0091] like Figure 5 As shown, the FPGA unit can input the 25MHz crystal oscillator clock fpga_clk25m as the basic clock signal, and through the PLL_100M phase-locked loop circuit, the basic clock signal generates the first clock and the second clock. The first clock clk_100m is the main clock of the system and is supplied to multiple modules, including the GPIF control module, the USB data encapsulation module, the 32-bit CRC check module, the scheduling control top-level module, the sample cache upload module and the USB receiving top-level module. The above modules use clk_100m to synchronize their operations to ensure that the system works together under the same time reference.

[0092] The second clock clk_100m_180 is a clock signal obtained by reverse processing the first clock clk_100m, and is output to the outside as the synchronization clock of the CYUSB3014 chip of the host computer, and is used for communication synchronization with the host computer, ensuring the correctness and stability of the timing and avoiding clock conflicts and data transmission errors.

[0093] In some embodiments, the pixel clock signal output by the instrument electronic control unit is processed by the global clock buffer (BUFG) to generate the pixel clock pclk_30m, which can be used in the data frame processing module and the display buffer module to synchronize and process the image data from the instrument. The global clock buffer can be used to ensure the stability and reliability of the pclk_30m signal to facilitate subsequent data processing and display.

[0094] It can be understood that since there are signals from different clock sources in the system (such as the first clock clk_100m and the pixel clock pclk_30m), when cross-clock domain processing is required between modules, asynchronous queues can be used to implement data interaction to ensure safe and reliable data transmission between different clock domains. Asynchronous queues can solve the problem of data instability or misalignment that may be caused by clock differences, and ensure the correct transmission and synchronization of data between different clock domains.

[0095] In some embodiments, the image display test system of the vehicle instrument may further include a power supply, which supplies power to the instrument electronic control unit and the image acquisition card. In the image display test scenario of the vehicle instrument disclosed in the present invention, the power supply can provide a stable power supply to the instrument electronic control unit and the image acquisition card to ensure the normal operation of the system and accurate image display testing.

[0096] Figure 6 is a schematic diagram of an image display test method for a vehicle instrument provided by an embodiment of the present disclosure, which is applied to the aforementioned host computer, such as Figure 6 As shown, the method may include the following steps:

[0097] Step S101: Send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument under test to display the image of the test case.

[0098] In some embodiments, the host computer can be connected to the instrument electronic control unit via a CAN bus and send test cases of CAN messages to the instrument electronic control unit. The CAN messages contain specific control information, such as instructions requiring the instrument under test to display a specific image or perform a specific operation.

[0099] In some embodiments, after receiving the CAN message sent from the host computer, the instrument electronic control unit can perform corresponding operations according to the instructions in the message. In the image display test, the instrument electronic control unit can generate corresponding image signals, such as RGB888, RGB666 signals, etc. according to the received instructions, and send the above image signals to the display screen of the instrument to display the image of the expected test case.

[0100] In some embodiments, once the image of the test case is displayed on the meter, the image acquisition card can capture the image data displayed on the meter. Typically, the image acquisition card can use a dedicated interface and acquisition technology, such as FPC cable connection, to obtain the RGB signal or other image data displayed by the meter.

[0101] In some embodiments, the image acquisition card can transmit the acquired image data to a host computer for further processing and analysis, such as comparison with a preset template image to verify the accuracy and quality of the instrument display. If the image data does not match expectations, the system can determine that the instrument is faulty or has a display problem.

[0102] Step S102: sending an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction.

[0103] In some embodiments, the host computer can be connected to the image acquisition card via a USB 3.0 data cable. In the test preparation stage, the host computer can send a specific acquisition instruction to the image acquisition card, and the acquisition instruction can include specific parameters and settings for the image acquisition, such as the number of frames to be acquired, the interval time, etc.

[0104] In some embodiments, after the image acquisition card receives an acquisition instruction from the host computer, the FPGA unit inside the image acquisition card can parse and process the received instruction and set corresponding image acquisition parameters according to the acquisition instruction.

[0105] In some embodiments, once the image acquisition card is configured and begins to communicate with the instrument under test through the connected FPC cable, the image acquisition card can communicate with the instrument display screen to capture image data displayed on the instrument screen. During the image acquisition process, the image acquisition card can periodically obtain image data from the instrument display screen according to a preset acquisition frequency and settings, such as an RGB signal or other types of image information displayed on the screen.

[0106] In some embodiments, the image acquisition card can process and cache the images of the test cases collected, and transmit them back to the host computer through the USB3.0 interface. The host computer can subsequently receive and process these image data, perform image quality analysis, compare with preset template images, and other operations.

[0107] Step S103: receiving the image of the test case, and comparing it with the template image of the test case to obtain the test result of the image display function of the instrument under test.

[0108] In some embodiments, the image acquisition card can capture real-time image data from the display screen of the instrument under test, and the image data can be an image of a test case. The received image data can be transmitted back to the host computer, where the image data is compared with a template image of a predefined test case, and the template image is an expected standard image, representing the image that the instrument should display correctly under ideal circumstances.

[0109] In some embodiments, the RGB values ​​or other image features of each pixel may be compared, and image processing algorithms may be applied to evaluate the similarity or difference of the images. The host computer can analyze the comparison results to determine whether the actual collected image matches the template image. If the image meets expectations, the system considers that the image display function of the instrument is normal. For example, if the collected image matches 99% of the pixels in the template image, the image display function test of the instrument is considered normal. If the image comparison results do not meet expectations, the system can record the test problems for subsequent analysis and debugging of the instrument.

[0110] In some embodiments, step S103 may include:

[0111] First, a first pixel of the image of the test case is obtained;

[0112] Next, obtaining a second pixel of the template image of the test case;

[0113] Finally, the pixel information of each of the first pixels is compared with the pixel information of each of the second pixels, and the test result is determined according to the comparison result of the pixel information of the first pixels and the pixel information of the second pixels.

[0114] In some embodiments, the system can obtain information about the first pixel from the collected test case image data, such as a color value (such as an RGB value) or other specific image features. Then, the system can obtain information about the second pixel at the corresponding position from a predefined template image. The template image is a predefined standard image of the test case for comparison with the actual collected image.

[0115] In some embodiments, the first pixel information of the acquired test case image can be compared with the second pixel information of the template image, and based on the pixel-level comparison, the difference in RGB values ​​or other image features between the two images can be compared, and the system will determine the test result based on the comparison result of the pixel information. It can be understood that if the information of the first pixel matches or is close to the information of the second pixel, for example, more than 99% of the pixels in the two images match, the system can determine that the image display test of the instrument has passed. If there are significant differences in the image comparison results or a large number of pixels do not match, the system can record that the test has failed, indicating that there is a problem with the image display function of the instrument or it does not meet expectations.

[0116] In some embodiments, the present disclosure may also include:

[0117] First, a basic clock signal is sent to the image acquisition card, so that a phase-locked loop circuit of the image acquisition card receives and processes the basic clock signal and outputs a first clock and a second clock that are opposite to each other;

[0118] Then, the instrument electronic control unit is controlled to send a pixel clock signal to the image acquisition card, so that the global clock buffer of the image acquisition card receives and processes the pixel clock signal and outputs a pixel clock with a preset frequency.

[0119] In some embodiments, the host computer can send a basic clock signal to the image acquisition card. This basic clock signal can be a fixed frequency signal, such as fpga_clk25m, which is used to synchronize and drive the phase-locked loop circuit (PLL) inside the image acquisition card. The phase-locked loop circuit inside the image acquisition card can receive and process input from the basic clock signal, and can adjust and stabilize the received basic clock signal through the phase-locked loop circuit to generate the first clock and the second clock that are opposite to each other required by the system.

[0120] In some embodiments, after being processed by a phase-locked loop circuit, the image acquisition card can output two mutually opposite first clocks and second clocks, the first clock and the second clock exist at different frequencies or phases, and are used to control various stages and timings in the image acquisition process. At the same time, the system can control the instrument electronic control unit to send a pixel clock signal to the image acquisition card, and the pixel clock signal is a clock signal generated by the instrument electronic control unit and output through the global clock buffer.

[0121] In some embodiments, the global clock buffer of the image acquisition card can receive and process the pixel clock signal from the instrument electronic control unit. The global clock buffer can stabilize and adjust the frequency of the pixel clock signal to ensure that the collected image data is sampled and processed at a preset frequency. After being processed by the global clock buffer, the image acquisition card can output a pixel clock signal with a preset frequency, and the pixel clock signal can be used to synchronize data sampling and timing control during the image acquisition process to ensure the accuracy and integrity of the image data.

[0122] like Figure 7 As shown, the specific execution process of the image display test method of the vehicle instrument disclosed in the present invention can be described.

[0123] In some embodiments, a complete platform including the vehicle instrument image display test system disclosed in the present invention can be established first. The power supply voltage is set to 12V and the current limit is 1A to supply power to the image acquisition card and the instrument electronic control unit to ensure successful power-on.

[0124] Next, the host computer can send a request through the data connection line according to the defined instruction protocol to query the version information of the FPGA unit on the image acquisition card to confirm that the FPGA unit has been loaded.

[0125] Then, the host computer can determine whether the image display test is required according to the preset conditions, and end the test operation if it is not required.

[0126] Then, the host computer can send the CAN message of the test case to the instrument electronic control unit through the CAN bus.

[0127] Furthermore, the host computer can send an acquisition instruction to the image acquisition card through the data connection line, and the FPGA unit of the image acquisition card receives and parses the instruction and starts to acquire image data according to the requirements of the acquisition instruction.

[0128] Then, the host computer can receive the image data collected by the image acquisition card through the data connection line.

[0129] Finally, the host computer can compare the received image data with the preset template image pixel by pixel to determine whether the image of the test case output by the instrument electronic control unit meets the expectations. If so, the RGB data of the image signal is converted into a picture and displayed on the host computer interface. If not, the system reports that the instrument is faulty.

[0130] Through the above technical scheme, the present invention can first use the image acquisition card to acquire the image of the test case sent by the instrument electronic control unit from the instrument to be tested, and then send the acquired image of the test case to the host computer, and compare the image of the test case with the template image pixel by pixel. The entire test process does not require manual image comparison, which not only improves the degree of automation of the test, but also eliminates the subjective factors of manual image comparison, thereby improving the accuracy and efficiency of testing the image display function of the vehicle instrument.

[0131] Figure 8 is a structural schematic diagram of an image display test device for a vehicle instrument provided by an embodiment of the present disclosure, such as Figure 8 As shown, the device may include:

[0132] The test request unit 201 is used to send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case;

[0133] The image acquisition unit 202 is used to send an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction;

[0134] The instrument testing unit 203 is used to receive the image of the test case and compare it with the template image of the test case to obtain the test result of the image display function of the instrument to be tested.

[0135] Through the image display test device for vehicle instruments provided by the embodiment of the present disclosure, it is possible to first use an image acquisition card to acquire an image of a test case sent by an instrument electronic control unit from the instrument to be tested, and then send the acquired image of the test case to a host computer, and compare the image of the test case with the template image pixel by pixel. The entire test process does not require manual image comparison, which not only improves the degree of automation of the test, but also eliminates the subjective factors of manual image comparison, thereby improving the accuracy and efficiency of testing the image display function of the vehicle instrument.

[0136] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0137] Fig. 9 FIG. 1 is a block diagram of an electronic device 300 according to an exemplary embodiment. Fig. 9As shown, the electronic device 300 may include: a processor 301 and a memory 302. The electronic device 300 may also include one or more of a multimedia component 303, an input / output (I / O) component 304, and a communication component 305.

[0138] The processor 301 is used to control the overall operation of the electronic device 300 to complete all or part of the steps in the above-mentioned vehicle instrument image display test method. The memory 302 is used to store various types of data to support the operation of the electronic device 300, and these data may include, for example, instructions for any application or method used to operate on the electronic device 300, and application-related data, such as contact data, sent and received messages, pictures, audio, video, etc. The memory 302 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, referred to as EPROM), programmable read-only memory (Programmable Read-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic memory, flash memory, magnetic disk or optical disk. The multimedia component 303 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 302 or sent through the communication component 305. The audio component also includes at least one speaker for outputting audio signals. The I / O component 304 provides an interface between the processor 301 and other interface modules, and the above-mentioned other interface modules may be keyboards, mice, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 305 is used for wired or wireless communication between the electronic device 300 and other devices. Wireless communication, such as WiFi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or a combination of one or more of them, is not limited here. Therefore, the corresponding communication component 305 may include: WiFi module, Bluetooth module, NFC module, etc.

[0139] In an exemplary embodiment, the electronic device 300 can be implemented by one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), controllers, microcontrollers, microprocessors or other electronic components to execute the above-mentioned vehicle instrument image display test method.

[0140] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, and when the program instructions are executed by a processor, the steps of the above-mentioned vehicle instrument image display test method are implemented. For example, the computer-readable storage medium may be the above-mentioned memory 302 including program instructions, and the above-mentioned program instructions may be executed by the processor 301 of the electronic device 300 to complete the following steps:

[0141] Acquire a first pixel of the image of the test case;

[0142] Acquire a second pixel of the template image of the test case;

[0143] The pixel information of each of the first pixels is compared with the pixel information of each of the second pixels, and the test result is determined according to the comparison result of the pixel information of the first pixels and the pixel information of the second pixels.

[0144] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0145] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0146] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A vehicle instrument image display test system, characterized in that: Applied to vehicles, including host computer, instrument electronic control unit, image acquisition card, among which: The host computer is connected to the instrument electronic control unit through a vehicle bus, and the instrument electronic control unit is connected to the instrument to be tested. The host computer is used to send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card, so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case; the image acquisition card includes an FPGA unit, wherein the FPGA unit is used to collect the image of the test case from the instrument to be tested, and upload the collected image of the test case to the host computer; the FPGA unit includes a communication module, a data frame processing module, a data parsing module, a scheduling module, a packaging module and a display cache module, wherein: the communication module is used to receive the acquisition instruction of the host computer, and send the data frame of the image of the test case to the host computer; The data frame processing module is used to verify the data frame, send the data frame that has been successfully verified to the data analysis module, and send the verification error information of the failed verification to the encapsulation module; the data analysis module is used to parse the valid information of the data frame, and send the valid information of the data frame to the display cache module; the display cache module is used to parse the valid information of the data frame, sample the data frame and cache it to the asynchronous queue, read and encapsulate the data frame of the asynchronous queue and send it to the scheduling module; the encapsulation module is used to encapsulate the version information of the FPGA unit, the verification error information, and the response information of the host computer to obtain the encapsulation information, and send the encapsulation information to the scheduling module; the scheduling module is used to organize the encapsulation information sent by the encapsulation module and the data frames of the asynchronous queue sent by the display cache module to obtain a data set, and send the data set to the communication module; The host computer is connected to the image acquisition card via a data connection line, and is used to send an acquisition instruction to the image acquisition card; The image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction, and sends it to the host computer; The host computer compares the image of the test case acquired by the image acquisition card with the template image of the test case, and obtains the test result of the image display function of the instrument to be tested according to the comparison result.

2. The image display test system for vehicle instruments according to claim 1, characterized in that: The FPGA unit further includes a clock management module, and the clock management module is used to manage the first clock, the second clock and the pixel clock, wherein: The first clock is a clock shared by the communication module, the data frame processing module, the scheduling module, the encapsulation module and the display buffer module; The second clock is a clock for synchronizing the FPGA unit with the host computer; the second clock is obtained by reverse processing of the first clock; The pixel clock is a clock sent by the instrument electronic control unit to the display cache module and the data analysis module of the FPGA unit, so that the FPGA unit collects the image displayed by the instrument under test based on the pixel clock.

3. The image display test system for vehicle instruments according to claim 1, characterized in that: The vehicle instrument image display test system further comprises a power supply, which supplies power to the instrument electronic control unit and the image acquisition card.

4. A vehicle instrument image display test method, applied to a host computer of a vehicle instrument image display test system according to any one of claims 1 to 3, characterized in that: The method comprises: Send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card, so that the image acquisition card sends the image signal to the instrument under test to display the image of the test case; the image acquisition card includes an FPGA unit, wherein the FPGA unit is used to acquire the image of the test case from the instrument under test, and upload the acquired image of the test case to the host computer; the FPGA unit includes a communication module, a data frame processing module, a data parsing module, a scheduling module, a packaging module and a display cache module, wherein: the communication module is used to receive the acquisition instruction of the host computer, and send the data frame of the image of the test case to the host computer; the data frame processing module is used to verify the data frame, and upload the verified data frame to the host computer The frame is sent to the data analysis module, and the verification error information of the verification failure is sent to the encapsulation module; the data analysis module is used to parse the valid information of the data frame, and send the valid information of the data frame to the display cache module; the display cache module is used to parse the valid information of the data frame, sample the data frame and cache it to the asynchronous queue, read and encapsulate the data frame of the asynchronous queue and send it to the scheduling module; the encapsulation module is used to encapsulate the version information of the FPGA unit, the verification error information, and the response information of the host computer to obtain the encapsulation information, and send the encapsulation information to the scheduling module; the scheduling module is used to sort out the encapsulation information sent by the encapsulation module and the data frame of the asynchronous queue sent by the display cache module, obtain a data set, and send the data set to the communication module; Sending an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument to be tested based on the acquisition instruction; An image of the test case is received and compared with a template image of the test case to obtain a test result of the image display function of the instrument to be tested.

5. The image display test method of a vehicle instrument according to claim 4, characterized in that: The receiving the image of the test case and comparing it with the template image of the test case to obtain the test result of the image display function of the instrument under test includes: Acquire a first pixel of the image of the test case; Acquire a second pixel of the template image of the test case; The pixel information of each of the first pixels is compared with the pixel information of each of the second pixels, and the test result is determined according to the comparison result of the pixel information of the first pixels and the pixel information of the second pixels.

6. The image display test method of a vehicle instrument according to claim 4, characterized in that: The method further comprises: Sending a basic clock signal to the image acquisition card, so that a phase-locked loop circuit of the image acquisition card receives and processes the basic clock signal, and outputs a first clock and a second clock that are opposite to each other; The electronic control unit of the instrument is controlled to send a pixel clock signal to the image acquisition card, so that the global clock buffer of the image acquisition card receives and processes the pixel clock signal and outputs a pixel clock of a preset frequency.

7. A vehicle instrument image display test device, applied to a host computer of a vehicle instrument image display test system according to any one of claims 1 to 3, characterized in that: The device comprises: A test request unit is used to send a test case to the instrument electronic control unit so that the instrument electronic control unit generates an image signal of the test case, and sends the image signal to the image acquisition card so that the image acquisition card sends the image signal to the instrument to be tested to display the image of the test case; the image acquisition card includes an FPGA unit, wherein the FPGA unit is used to collect the image of the test case from the instrument to be tested, and upload the collected image of the test case to the host computer; the FPGA unit includes a communication module, a data frame processing module, a data parsing module, a scheduling module, a packaging module and a display cache module, wherein: the communication module is used to receive the acquisition instruction of the host computer, and send the data frame of the image of the test case to the host computer; the data frame processing module is used to verify the data frame, and the verified image The data frame of successful verification is sent to the data analysis module, and the verification error information of failed verification is sent to the encapsulation module; the data analysis module is used to parse the valid information of the data frame, and send the valid information of the data frame to the display cache module; the display cache module is used to parse the valid information of the data frame, sample the data frame and cache it to the asynchronous queue, read and encapsulate the data frame of the asynchronous queue and send it to the scheduling module; the encapsulation module is used to encapsulate the version information of the FPGA unit, the verification error information, and the response information of the host computer to obtain the encapsulation information, and send the encapsulation information to the scheduling module; the scheduling module is used to sort out the encapsulation information sent by the encapsulation module and the data frame of the asynchronous queue sent by the display cache module, obtain a data set, and send the data set to the communication module; An image acquisition unit, used for sending an image acquisition instruction to the image acquisition card, so that the image acquisition card acquires the image of the test case from the instrument under test based on the acquisition instruction; The instrument testing unit is used to receive the image of the test case and compare it with the template image of the test case to obtain the test result of the image display function of the instrument to be tested.

8. An electronic device, characterized in that: include: a memory having a computer program stored thereon; A processor is used to execute the computer program in the memory to implement the steps of the image display test method of the vehicle instrument according to any one of claims 4 to 6.

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