A method for arranging through-holes between layers of a 3D chip

Abstract

The present invention relates to the field of electronic design automation, and specifically to a method for arranging interlayer vias of 3D chips. The present invention models the deployment of interlayer vias in 3D-IC design, and models it as an optimal transmission problem for double-layer 3D-IC, and first models it as an IMCMC problem for multi-layer 3D-IC. The GPU uses the shortest path algorithm to solve the shortest paths between all source points and sink points in the IMCMC problem in parallel, and obtains a layout scheme to be adjusted that satisfies the optimal line length. The adjustment of the layout scheme to be adjusted is further modeled as an optimal transmission problem to meet the grid capacity limit, and finally the optimal transmission problem is solved to obtain the final interlayer via deployment scheme. The present invention greatly improves the computational efficiency of the layout scheme of interlayer vias in high integration density 3D-IC by decomposing the interlayer via deployment problem in multi-layer 3D-IC into the shortest path calculation that can be processed in parallel.

Description

Technical Field

[0001] The invention relates to the field of electronic design automation, and in particular to a method for arranging through holes between layers of a 3D chip. Background Art

[0002] In recent years, 3D-IC (three-dimensional integrated circuit) technology has attracted a lot of attention due to its advantages in chip design. Compared with traditional 2D-IC (two-dimensional integrated circuit), 3D-IC can provide higher integration density, shorter wire length and better energy efficiency. To realize 3D-IC design, a key factor to consider is signal transmission between different layers. Signal transmission can be carried out through interlayer vias, such as TSV (through silicon via) and MIV (monolithic interlayer via). TSV is a relatively large vertical via with a diameter of about 5 microns, which penetrates the silicon substrate and connects to multiple chip layers. Recently, M3D (monolithic three-dimensional integrated circuit) technology has emerged as a cutting-edge method that provides higher integration density compared to TSV-based 3D-IC; the MIV used by M3D has a diameter of less than 100 nanometers, which is much smaller than TSV, such as Figure 1 M3D can provide smaller 3D contact pitch and higher integration density, which is very helpful for developing compact 3D integration solutions. At the same time, high integration density also brings challenges to the efficiency of interlayer through-hole arrangement algorithms.

[0003] Among the existing methods for solving the via placement problem, the via placement problem in 3D-IC chips is modeled as an IMCMC (minimum cost multi-commodity flow) model, and a heuristic method is used to solve the IMCMC problem. When solving the via placement problem, the heuristic method first defines a set of rules or heuristic algorithms, which are based on the understanding of the problem structure and specific design experience. For example, the key vias with strict timing requirements or high signal integrity requirements can be arranged first, and then other vias can be arranged. In addition, in order to solve resource allocation conflicts and reduce interference between vias, a hierarchical approach may be adopted to optimize layer by layer, and global optimization techniques such as simulated annealing and genetic algorithms may also be considered to search for potential layout space. These heuristic methods usually require continuous adjustment of parameters in an iterative process to gradually approach a cost-effective solution.

[0004] However, heuristic methods often require multiple iterations and adjustments for each specific case, which may greatly increase the calculation time and reduce the overall solution efficiency when faced with tight design cycles and complex design requirements. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a method for arranging inter-layer vias of a 3D chip.

[0006] The method includes:

[0007] Step 1: Define the i-th network among all n networks that need to be connected in the target chip of layer D as nt i , the i-th network nt i The corresponding interlayer via set is Gri i , the jth grid in the cth layer chip is The goal of inter-layer via placement is to minimize the cost function Cost;

[0008] Step 2: When the 3D chip is a two-layer chip, the interlayer through-holes required by each network are used as supply nodes, and the grids with blank areas are used as demand nodes. The supply quantity of each supply node, the demand quantity of each demand node, and the cost from each demand node to each resource node are defined to construct the optimal transmission model.

[0009] Step 3: When the 3D chip is a chip with at least three layers, the source point of the network is used as the supply node, the sink point of the network is used as the demand node, the grid is used as the transit node, and the interlayer via is used as the commodity. The capacity and cost of the edges connecting various nodes and the capacity of each node are defined to construct an integer minimum cost multi-commodity flow model; the integer minimum cost multi-commodity flow model is solved to obtain the layout scheme to be adjusted; the interlayer via of each layer in the layout scheme to be adjusted is used as the supply node, and the grid with blank area of ​​the layer is used as the demand node, and the optimal transmission model of each layer is constructed to fine-tune the layout scheme to be adjusted so that each node meets the capacity constraint;

[0010] Step 4: After introducing the entropy regularization term into the objective function of the optimal transmission model, the transportation plan matrix of the optimal transmission model is solved by Sinkhorn's matrix scaling algorithm as the layout plan of the interlayer vias of the target chip.

[0011] Furthermore, the cost function Cost in step 1 is:

[0012]

[0013] in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i The set of inter-layer vias that need to be arranged on the c-th layer is connected. For network nt i Crossing the bottom, For network nt i At the top level, HPWL() stands for the half-perimeter line length calculation function. Represents network nt iThe half perimeter line length of the 2D bounding box of the inter-layer via that needs to be arranged to connect the subnet of the cth layer to this subnet.

[0014] Furthermore, step 2 specifically refers to constructing an optimal transmission model in the following manner when the 3D chip is a two-layer chip:

[0015] An interlayer via required by each network is taken as a supply node, and the supply quantity of each supply node is set to 1;

[0016] Each grid with blank area is regarded as a demand node, and the demand of each demand node is set to the capacity of the grid represented by the demand node;

[0017] Supply node p i To the demand node q j The price of A i,j Let nt be the i-th network i The required inter-layer via is arranged on the jth blank grid and the line length cost A is i,j :

[0018]

[0019] in, represents the jth blank grid in the first layer of the chip, Represents the i-th network nt i In the subnet at layer zero, Represents the i-th network nt i Subnet at the first level.

[0020] Furthermore, when the 3D chip is a two-layer chip, a virtual supply node is introduced into the constructed optimal transmission model. The supply quantity of the virtual supply node is set to the difference between the demand quantity of all demand nodes and the supply quantity of all supply nodes, and the cost from the virtual supply node to each demand node is set to the same constant.

[0021] Furthermore, in step 3, the source point of the network is used as the supply node, the sink point of the network is used as the demand node, the grid is used as the transit node, and the interlayer through hole is used as the commodity. The capacity and cost of the edges connecting various nodes and the capacity of each node are defined to construct an integer minimum cost multi-commodity flow model. Specifically, a directed graph of the cost multi-commodity flow model is constructed in the following way:

[0022] Construct a directed graph G(V,E) where the point set V includes the source point Meeting Point and non-zero blank grid points s i Represents the i-th network nt i The source point, t iRepresents the i-th network nt i The meeting point, Represents the jth grid in the cth layer of the target chip. The connection scheme between a source node and a sink node represents the inter-layer via arrangement scheme of a network;

[0023] The edge set includes {S→V g}, represents the edge of the source point pointing to a non-zero blank grid point; {V g →V g}, represents the edge of a non-zero blank grid point pointing to another non-zero blank grid point; {V g →T}, represents the edge of a non-zero blank grid point pointing to the sink;

[0024] The capacity of non-zero blank grid points is set to the number of inter-layer vias that its corresponding grid can actually accommodate, and the capacity of other types of points is set to infinity;

[0025] For the edge from the source point to the non-zero blank grid point, and the edge from the non-zero blank grid point to the sink point, its capacity is defined as 1, and the capacity of other types of edges is set to infinity;

[0026] For the edge pointing to the sink from a non-zero blank grid point, its cost is set to 0. For the edge pointing to the jth grid in the cth layer, If the i-th network nt i If an interlayer via is required on layer c, then point to The cost of the edge for:

[0027]

[0028] in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i A set of inter-layer vias that need to be arranged on the c-th layer are connected.

[0029] Furthermore, the step 3 of solving the integer minimum cost multi-commodity flow model to obtain the layout plan to be adjusted specifically includes:

[0030] Use the shortest path algorithm to solve the shortest paths between all source and sink nodes in graph G in parallel;

[0031] Among them, for the i-th network nt i The set of grid cells traversed on the shortest path obtained by the shortest path algorithm is the network nt i The layout plan to be adjusted The shortest paths to be adjusted of all networks constitute the arrangement plan of the inter-layer vias to be adjusted.

[0032] Furthermore, in step 3, the interlayer through holes of each layer in the arrangement scheme to be adjusted are used as supply nodes, and the grids with blank areas of the layer are used as demand nodes to construct an optimal transmission model, which specifically includes:

[0033] Define the layout to be adjusted The final layout after fine-tuning is

[0034] The optimization goal for fine-tuning the layout to be adjusted is:

[0035]

[0036] Among them, T c represents the set of nets that need to have vias placed on layer c, Represents T c The interlayer vias in the layout to be adjusted To the final layout plan The sum of the Manhattan distances of ;

[0037] Each As an independent optimal transportation example, the problem of fine-tuning the layout scheme to be adjusted is modeled as an optimal transmission model, where for layer c, the interlayer through holes passing through the layer are the supply nodes, and the grids with blank areas in the layer are the demand nodes. The supply of each supply node is set to 1, and the demand of each demand node is set to the capacity of the grid corresponding to the demand node. The unit cost is set to

[0038] Furthermore, the entropy regularization term is introduced into the objective function of the optimal transmission model in step 4, specifically including:

[0039] The objective function of defining the optimal transmission model is:

[0040]

[0041] h(F)=-∑ i,j F i,j logF i,j ;

[0042] Among them, A i,j Represents the supply node p i To the demand node q j The cost of supplying node p i To the demand node q j The transport volume F i,j Represents the optimal transmission problem corresponding to the current layer, the i-th network nt iThe number of through holes corresponding to the inter-layer through holes assigned to the j-th blank grid, F represents the transport volume F i,j The transportation planning matrix composed of , λ is the positive regularization parameter, and h(F) is the entropy of the transportation planning matrix F.

[0043] Furthermore, the transport planning matrix of the optimal transport model is solved by Sinkhorn's matrix scaling algorithm in step 4, specifically including:

[0044] The supply nodes, demand nodes, cost matrix and regularization parameter λ of the optimal transport model are used as function inputs in the Python library POT to solve the transport planning matrix F and obtain an approximate solution transport planning matrix F ′ .

[0045] Furthermore, we get the approximate solution transportation planning matrix F ′ Then, optimize as follows:

[0046] The approximate solution of the transportation planning matrix F ′ is regarded as a probability matrix, where each element represents the probability of the corresponding inter-layer via being assigned to the corresponding grid;

[0047] The inter-layer vias are sorted based on the size of the bounding box corresponding to a network. The smaller the area of ​​the bounding box of a network, the higher its priority;

[0048] The interlayer vias of the network with high priority are placed first, and then the interlayer vias of the network with low priority. When placing the interlayer vias, the grids with the highest probability and meeting the grid capacity requirements in the approximate solution transportation plan matrix F′ are given priority until the final interlayer via deployment plan is obtained.

[0049] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0050] The present invention models the deployment of interlayer vias in 3D-IC design. For a double-layer 3D-IC, it is modeled as an optimal transmission problem. For a multi-layer 3D-IC, it is first modeled as an IMCMC problem. The GPU uses the shortest path algorithm to solve the shortest paths between all source points and sink points in the IMCMC problem in parallel to obtain a layout scheme to be adjusted that satisfies the optimal line length. The adjustment of the layout scheme to be adjusted is further modeled as an optimal transmission problem to meet the grid capacity limit. Finally, the optimal transmission problem is solved to obtain the final interlayer via deployment scheme. By decomposing the interlayer via deployment problem in a multi-layer 3D-IC into a shortest path calculation that can be processed in parallel, the computational efficiency of the layout scheme of interlayer vias in a high integration density 3D-IC is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A comparison diagram of MIV and TSV in 3D-IC provided as the background technology of the present invention;

[0052] Figure 2 A schematic diagram of a three-layer 3D-IC layout provided by an embodiment of the present invention;

[0053] Figure 3 A relationship diagram between the HPWL line length cost of a network in a two-layer 3D-IC and the arrangement position of inter-layer vias provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of an optimal transmission model corresponding to a two-layer 3D-IC provided in an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of an IMCMC model of a four-layer layout provided in an embodiment of the present invention;

[0056] Figure 6 This is a performance comparison chart of various algorithms in the case of multi-layer layout provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. Before describing in detail the technical solutions of each embodiment of the present invention, the nouns and terms involved are explained. In this specification, components with the same name or the same number represent similar or identical structures and are only for illustrative purposes.

[0058] 1. Definition of inter-layer via layout model

[0059] For a 3D-IC that needs to be laid out with interlayer vias, it is defined as a target chip, the number of layers C of which has been determined, and the layout information of each layer of chips has also been determined. The layout information of each layer of chips refers to which areas of the chip layer are modules and which areas are blank areas. A module refers to a circuit component with a specific function. Interlayer vias cannot be arranged in the area occupied by a module. Its function is to enable the network to span different layers in the target chip. In the present invention, a network refers to a conductive path connecting a group of pins so that signals can be transmitted between all pins in the group. In the present invention, the area occupied by the interlayer vias in the same chip is the same.

[0060] For a target chip with D layers, each layer is assigned a number, 0, 1, ..., D-1 from bottom to top. ⊥ Layer spans to Layer network, Need to be at layer Interlayer vias are arranged on top.

[0061] All n networks in the target chip that need to be connected form a network list NetL = {nt1 ,…,nt i ,…,nt n}, where 1≤i≤n, the i-th network nt i The lowest level across The top layer spanned is

[0062] Divide each layer of the target chip into J grids of the same size. Figure 2 A three-layer 3D-IC is shown, Figure 2 The blue area in the figure represents the module, and the interlayer vias can only be arranged in Figure 2 In the blank area represented by the white area, Figure 2 Each smallest square formed by the dotted lines in the image is the divided grid. The jth grid in the cth layer of the target chip is Grid Capacity for:

[0063]

[0064] in, Representative Grid The area of ​​the blank area in the graph, τ represents the area occupied by an interlayer through hole, Represents a floor operation. Capacity Representative Grid The number of inter-layer vias that can be accommodated in the circuit.

[0065] Each network in the network list NetL corresponds to a set of inter-layer through holes, where the i-th network nt i The corresponding interlayer through hole set Gri i for:

[0066]

[0067] in, Represents the i-th network nt i The interlayer via in the cth layer of the target chip, Represents the i-th network nt i The lowest level across The highest level crossed is But the network nt i The required interlayer vias only need to be arranged in Layer to layer.

[0068] The cost of the overall layout solution of the target chip is composed of the cost of each network, and the cost of each network is determined by the subnet of the network in each layer and the location of the interlayer vias. Based on this, the goal of interlayer via placement is to minimize the cost function Cost:

[0069]

[0070] in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i The set of interlayer vias that need to be arranged in the cth layer is connected. When the cth layer is in the network nt i When the layer being crossed is an intermediate layer, Because the subnet border of the middle layer will be affected by the position of the interlayer through-holes of the current layer and the previous layer. HPWL() stands for the half-perimeter line length calculation function. Represents network nt i The half perimeter line length of the 2D bounding box of the inter-layer via that needs to be arranged to connect the subnet of the cth layer to this subnet.

[0071] 2. Modeling when the target chip has two layers

[0072] When the target chip has two layers, the present invention models the layout problem of interlayer vias as an optimal transportation problem. The optimal transportation problem is to find a resource allocation scheme to minimize the total cost of transferring resources from multiple supply nodes to multiple demand nodes. In a given cost matrix, each element represents the cost of transferring a unit resource from a supply node to a demand node. The goal of solving the optimal transportation problem is to determine a transportation scheme, i.e., a transportation plan matrix, so that the total cost is minimized while satisfying the supply constraints of the supply nodes and the demand of the demand nodes.

[0073] like Figure 3 As shown, the target chip has a two-layer structure, with two pins p on the bottom layer. 0 and p 1 , the top layer has two pins p 2 and p 3 , when the layout position of the interlayer vias is determined, the HPWL line length cost of the network is determined. Figure 3 Connect pin p 0 、p 1 、p 2 and p 3 If the layout of the interlayer through holes is Via 1 The HPWL line length cost of the network is Figure 3The sum of the semi-perimeter of the red rectangular frame of the two layers; if the layout of the interlayer through hole is Via′ 1 The HPWL line length cost of the network is Figure 3 The sum of the semi-perimeter of the two blue rectangular boxes in the middle.

[0074] When the target chip has two layers, the layout of the interlayer vias is modeled as follows: Figure 4 As shown, Figure 4 Middle left p 1 to p n are the supply nodes in the optimal transmission problem. Each supply node represents an inter-layer via required by each network, and the supply quantity of each supply node is set to 1. Figure 4 Middle right q 1 to q N is the demand node in the optimal transmission problem. Each demand node represents a grid with blank areas, and the demand of each demand node is set to the capacity of the grid represented by the demand node.

[0075] Supply node p i To the demand node q j The price of A i,j Let nt be the i-th network i The line length cost of the required inter-layer vias arranged on the j-th blank grid is:

[0076]

[0077] in, represents the jth blank grid in the first layer of the chip, Represents the i-th network nt i In the subnet at layer 0, Represents the i-th network nt i Subnet at layer 1;

[0078] In order to make the total supply equal to the total demand, a virtual supply node p is introduced in the supply node. n+1 , the supply quantity of the virtual supply node is set to ∑q j -∑p i , set the cost from the virtual supply node to each demand node to the same constant.

[0079] Solving this optimal transmission problem can satisfy the minimization of the cost function Cost.

[0080] 3. IMCMC modeling when the target chip is multi-layer

[0081] In the present invention, multi-layer refers to more than two layers. The present invention provides a method combining the IMCMC (minimum cost multi-commodity flow) model with the optimal transmission model for parallel planning to solve the minimum cost problem of inter-layer through-hole arrangement when the target chip is multi-layer, which is an NP-complete problem.

[0082] The integer minimum cost multi-commodity flow problem is to find the lowest cost flow configuration for transporting multiple commodities simultaneously in a network, where the flow must be integer-valued. Each commodity flows from a specified supply node to a demand node, and each edge has a fixed transportation cost and capacity constraint. The goal is to minimize the total transportation cost of the entire network under these constraints while ensuring that each commodity satisfies its respective supply and demand balance.

[0083] When the target chip is multi-layer, the constructed IMCMC model is as follows Figure 5 As shown, Figure 5 All the nodes and edges in the graph form a directed graph G(V,E), where the point set V includes the source point Meeting Point and non-zero blank grid points s i Represents the i-th network nt i The source point, t i Represents the i-th network nt i The meeting point, represents the jth grid in the cth layer of the target chip. The connection scheme between a source node and a sink node represents the inter-layer via arrangement scheme of a network. The edge set includes {S→V g}, represents the edge of the source point pointing to a non-zero blank grid point, {V g →V g}, represents the edge of a non-zero blank grid point pointing to another non-zero blank grid point, {V g →T}, represents the edge from a non-zero blank grid point to a sink. The capacity of a non-zero blank grid point is set to the number of inter-layer vias that its corresponding grid can actually accommodate, and the capacity of other types of points is set to infinity. For the edge from the source point to a non-zero blank grid point, and the edge from a non-zero blank grid point to a sink, its capacity is defined as 1, and the capacity of other types of edges is set to infinity.

[0084] Each edge of the graph G may have multiple cost values. For the edge pointing to the sink from a non-zero blank grid point, its cost is set to 0. For the edge pointing to the jth grid in the cth layer, If the i-th network nt i If an interlayer via is required on layer c, then point to The cost of the edge for:

[0085]

[0086] in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i A set of inter-layer vias that need to be arranged on the c-th layer are connected.

[0087] The sum of the costs of the connections between all source and sink nodes in Figure G corresponds to the total bus length cost in the multi-layer 3D-IC inter-layer via design.

[0088] 4. Solve the shortest path of the IMCMC model when the target chip is multi-layer

[0089] The shortest paths between different source points and sink points in the graph G are independent of each other. The present invention solves the shortest paths between all source points and sink points in the graph G in parallel.

[0090] For every pair of source points s i With the meeting point i , based on the definition of the cost of each type of edge in the graph G, calculate the cost from the source point s i To the meeting point i The shortest path is the path with the minimum cost. A classic algorithm for solving the shortest path can be used to solve all the shortest paths in parallel using a GPU. The present invention uses the Dijkstra algorithm.

[0091] For the i-th network nt i The set of grid cells traversed on the shortest path obtained by the shortest path algorithm is the network nt i The shortest path to be adjusted The shortest paths to be adjusted of all networks constitute the arrangement plan of the inter-layer vias to be adjusted.

[0092] This step does not take into account the capacity limit of each node. Some nodes in graph G may exceed their capacity limit. Therefore, the shortest path set solved in this step is only the layout plan to be adjusted.

[0093] 5. Constructing the optimal transmission model of multi-layer 3D-IC based on the layout scheme to be adjusted

[0094] In the design of 3D-IC, the line length depends on the layout position of the interlayer vias. Based on the layout scheme to be adjusted, the interlayer vias are slightly moved to make the layout scheme to be adjusted meet the capacity constraints of all nodes while minimizing the impact on the total line length.

[0095] In the layout adjustment scheme, the Manhattan distance between the current overloaded node and the grid with blank areas around it is evaluated, and the overloaded node is fine-tuned. The optimal transmission algorithm is used to move some interlayer through holes of the overloaded node to the nodes with blank areas around it without significantly increasing the line length.

[0096] Define the layout to be adjusted After fine-tuning, the final layout is obtained Fine-tuning requires achieving the optimization goal while satisfying the grid capacity constraints:

[0097]

[0098] Among them, Manh() represents the Manhattan distance calculation function.

[0099] The number of interlayer vias in each layer of the target chip is the same as the number of networks crossing the layer. The network set that needs to place interlayer vias in layer c is defined as T c , then under the premise of complying with the grid capacity limit, T c The inter-layer vias in the can be placed in the same grid.

[0100] Therefore, the optimization goal for fine-tuning the layout to be adjusted can be redefined as:

[0101]

[0102] in, Represents T c The interlayer vias in the To the final position The sum of the Manhattan distances.

[0103] Each As an independent optimal transportation example, the problem of fine-tuning the layout scheme to be adjusted is modeled as an optimal transportation problem. Taking layer c as an example, the interlayer through holes passing through the layer are the supply nodes, and the grids with blank areas in the layer are the demand nodes. The supply of each supply node is set to 1, and the demand of each demand node is set to the capacity of the grid corresponding to the demand node. The unit cost is set to Referring to the relevant steps when the target chip is a double-layer, the problem of fine-tuning the arrangement scheme to be adjusted is modeled as an optimal transmission problem, which will not be repeated here.

[0104] 6. Solve the optimal transmission problem of interlayer via arrangement

[0105] There are many ways to solve the optimal transmission problem. One common way is to transform it into a linear programming problem and solve it using the classic network simplex method. The present invention introduces an entropy regularization term into the objective function of the optimal transmission problem of interlayer via arrangement to make it smooth:

[0106]

[0107] h(F)=-∑ i,j F i,j logF i,j ;

[0108] Among them, A i,j Represents the supply node p i To the demand node q j The cost of supplying node p i To the demand node q j The transport volume F i,j Represents the optimal transmission problem corresponding to the current layer, the i-th network nt i The number of through holes corresponding to the inter-layer through holes assigned to the j-th blank grid, F represents the transport volume F i,j The transportation planning matrix composed of , λ is the positive regularization parameter, and h(F) is the entropy of the transportation planning matrix F.

[0109] Solving this regularized problem can be achieved through Sinkhorn's matrix scaling algorithm. In specific implementation, the supply node, demand node, cost matrix and regularization parameter λ can be used as function input in the python library POT to solve the transportation plan matrix F and obtain an approximate solution transportation plan matrix F ′ .

[0110] In order to obtain the final solution, the approximate solution transportation planning matrix F ′ It is regarded as a probability matrix, in which each element represents the probability of the corresponding interlayer via being assigned to the corresponding grid. If the bounding box of a network is very small, its size is very sensitive to the location of the interlayer via; conversely, if the bounding box of a network is large, its size is relatively less sensitive to the location of the interlayer via. In the present invention, the bounding box of the network refers to the smallest rectangular area in a layer of the target chip that surrounds all the connection points of the network in that layer. The interlayer vias are sorted based on the size of the bounding box corresponding to a network. The smaller the area of ​​the bounding box of a network, the higher its priority. The interlayer vias of the network with high priority are placed first, and then the interlayer vias of the network with low priority are placed. When placing the interlayer vias, the grid with the highest probability and meeting the grid capacity requirements in the approximate solution transportation plan matrix F′ is placed first, until the final interlayer via deployment plan is obtained.

[0111] 7. Advantages and Positive Effects

[0112] The following is a detailed comparison of the present invention with other methods. Table 1 shows the comparison of the effects of the present invention and the traditional minimum cost maximum flow model in the case of two layers. It can be found that the present invention only increases the line length by less than 1%, and can achieve more than 20 times acceleration on some data sets.

[0113] Table 1: Comparison results of the effects of the present invention and the minimum cost maximum flow model in the case of two layers

[0114]

[0115] In Table 1, “GridSize” refers to the granularity of dividing the layout into grids. “Speed” indicates the multiple of time acceleration, and “Wire↑” represents the wire length increased by the OT-based algorithm compared to the optimal wire length obtained by the minimum cost maximum flow method.

[0116] In the case of multiple layers, Figure 6 The results of various methods on 4-layer layout are shown in comparison with other algorithms for solving multi-layer via placement. Figure 6 "Layer-by-layer" refers to placing vias layer by layer by applying the minimum cost maximum flow model; "Lagrange" refers to the method based on the Lagrange relaxation algorithm; "Multilevel" refers to the multi-level heuristic method of coarsening first and then refining. The y-axis represents the ratio of the line length to the lower bound (pseudo-solution based on the shortest path method). Figure 6 It can be seen that the present invention has the best line length performance in most data sets in the case of multiple layers, and the present invention has better time performance, and the detailed comparison is shown in Table 2.

[0117] As the integration level of 3D-ICs increases, the number of through-holes required increases. The present invention further experiments with scenarios with a large number of netlists (and therefore a large number of through-holes). The present invention designs two types of benchmarks, using layouts from ami33 and n300 circuits, respectively, because they represent two different types of circuits from MCNC and GSRC, respectively. Keep their layouts and randomly generate a large number of networks, as shown in Table 2. For the two-layer case, the minimum cost maximum flow model can produce the optimal solution, and the present invention only causes a very small increase in line length (less than 0.5%). For the multi-layer case, the algorithm of the present invention reduces the line length by approximately 4%-10% compared to the layer-by-layer minimum cost maximum flow method. The present invention demonstrates a significant acceleration effect. For example, in a 4-layer setting of the n300 circuit, there are 50K cross-layer networks, and the layer-by-layer algorithm takes 6.8 hours, while the OT-based method produces the result in only 36 seconds, achieving a significant acceleration ratio of 670 times.

[0118] Table 2: Comparison of the performance of the minimum cost maximum flow model and the model of the present invention under different numbers of networks.

[0119]

[0120] In Table 2, for the case of two layers, the present invention still uses the minimum cost maximum flow method as the benchmark, and the meanings of "Wire↑" and "Speed" are the same as those in Table 1. For the case of four layers, since there is no optimal solution, the present invention directly uses the layer-by-layer method in the literature as the benchmark, and the wire length obtained by the present invention is lower, so the value of "Wire↑" is negative.

[0121] It can be seen from this that the present invention can achieve a large degree of acceleration, and can fully utilize the advantages of parallel computing of GPU to significantly improve computing efficiency while maintaining good results.

[0122] The above-described embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A method for arranging through-holes between layers of a 3D chip, characterized in that: include: Step 1: Define the i-th network among all n networks that need to be connected in the target chip of layer D as nt i , the inter-layer through-hole set corresponding to the i-th network nti is Gri i , the jth grid in the cth layer chip is The goal of inter-layer via placement is to minimize the cost function Cost; Step 2: When the 3D chip is a two-layer chip, the interlayer through-holes required by each network are used as supply nodes, and the grids with blank areas are used as demand nodes. The supply quantity of each supply node, the demand quantity of each demand node, and the cost from each demand node to each supply node are defined to construct the optimal transmission model. Step 3: When the 3D chip is a chip with at least three layers, the source point of the network is used as the supply node, the sink point of the network is used as the demand node, the grid is used as the transit node, and the inter-layer through-hole is used as the commodity. The capacity and cost of the edges connecting various nodes and the capacity of each node are defined to construct an integer minimum cost multi-commodity flow model; the integer minimum cost multi-commodity flow model is solved to obtain the layout plan to be adjusted; The interlayer through holes of each layer in the layout scheme to be adjusted are taken as supply nodes, and the grids with blank areas of the layer are taken as demand nodes. The optimal transmission model of each layer is constructed to fine-tune the layout scheme to be adjusted so that each node meets the capacity constraint. Step 4: After introducing the entropy regularization term into the objective function of the optimal transmission model, the transportation plan matrix of the optimal transmission model is solved by Sinkhorn's matrix scaling algorithm as the layout plan of the interlayer vias of the target chip; In step 3, the source point of the network is used as the supply node, the sink point of the network is used as the demand node, the grid is used as the transit node, and the inter-layer through-hole is used as the commodity. The capacity and cost of the edges connecting various nodes and the capacity of each node are defined to construct an integer minimum cost multi-commodity flow model. Specifically, a directed graph of the cost multi-commodity flow model is constructed in the following way: Construct a directed graph G(V, E) where the point set V includes the source point Meeting Point and non-zero blank grid points s i Represents the i-th network nt i The source point, t i Represents the i-th network nt i The meeting point, Represents the jth grid in the cth layer of the target chip. The connection scheme between a source node and a sink node represents the inter-layer via arrangement scheme of a network; The edge set includes {S→V g }, represents the edge of the source point pointing to a non-zero blank grid point; {V g →V g }, represents the edge of a non-zero blank grid point pointing to another non-zero blank grid point; {V g →T}, represents the edge of a non-zero blank grid point pointing to the sink; The capacity of non-zero blank grid points is set to the number of inter-layer vias that its corresponding grid can actually accommodate, and the capacity of other types of points is set to infinity; For the edge from the source point to the non-zero blank grid point, and the edge from the non-zero blank grid point to the sink point, its capacity is defined as 1, and the capacity of other types of edges is set to infinity; For the edge pointing to the sink from a non-zero blank grid point, its cost is set to 0. For the edge pointing to the jth grid in the cth layer, If the i-th network nt i If an interlayer via is required on layer c, then point to The cost of the edge for: in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i The set of inter-layer vias that need to be arranged on the c-th layer is connected. Represents the i-th network nt i At the bottom layer of the span, HPWL() stands for the half-perimeter line length calculation function; The step 3 solves the integer minimum cost multi-commodity flow model to obtain the layout plan to be adjusted, which specifically includes: Use the shortest path algorithm to solve the shortest paths between all source and sink nodes in graph G in parallel; Among them, for the i-th network nt i The set of grid cells traversed on the shortest path obtained by the shortest path algorithm is the network nt i The layout plan to be adjusted The arrangement schemes to be adjusted of all networks constitute the arrangement schemes to be adjusted of the inter-layer vias.

2. The method for arranging through-holes between layers of a 3D chip according to claim 1, characterized in that: The cost function Cost in step 1 is: in, Represents the i-th network nt i In the subnet at layer c, Represents the i-th network nt i The set of inter-layer vias that need to be arranged on the c-th layer is connected. For network nt i Crossing the bottom, For network nt i At the top level, HPWL() stands for the half-perimeter line length calculation function. Represents network nt i The half perimeter line length of the 2D bounding box of the inter-layer via that needs to be arranged to connect the subnet of the cth layer to this subnet.

3. The method for arranging through-holes between layers of a 3D chip according to claim 1, characterized in that: Step 2 specifically refers to constructing the optimal transmission model in the following manner when the 3D chip is a two-layer chip: An interlayer via required by each network is taken as a supply node, and the supply quantity of each supply node is set to 1; Each grid with blank area is regarded as a demand node, and the demand of each demand node is set to the capacity of the grid represented by the demand node; Supply node p i To the demand node q j The price of A i，j Let nt be the i-th network i The required inter-layer via is arranged on the jth blank grid and the line length cost A is i，j : in, represents the jth blank grid in the first layer of the chip, Represents the i-th network nt i In the subnet at layer zero, Represents the i-th network nt i In the first layer of the subnet, HPWL() stands for the half-perimeter line length calculation function.

4. The method for arranging through-holes between layers of a 3D chip according to claim 1, characterized in that: When the 3D chip is a two-layer chip, a virtual supply node is introduced into the constructed optimal transmission model. The supply quantity of the virtual supply node is set to the difference between the demand quantity of all demand nodes and the supply quantity of all supply nodes, and the cost from the virtual supply node to each demand node is set to the same constant.

5. The method for arranging interlayer vias of a 3D chip according to claim 1, characterized in that: In step 3, the interlayer through holes of each layer in the arrangement scheme to be adjusted are used as supply nodes, and the grids with blank areas of the layer are used as demand nodes to construct the optimal transmission model, which specifically includes: Define the layout to be adjusted The final layout after fine-tuning is The optimization goal for fine-tuning the layout to be adjusted is: Among them, T c represents the set of nets that need to have vias placed on layer c, Represents T c The interlayer vias in the layout to be adjusted To the final layout plan The sum of the Manhattan distances of ; Each As an independent optimal transportation example, the problem of fine-tuning the layout scheme to be adjusted is modeled as an optimal transmission model, where for layer c, the interlayer through holes passing through the layer are the supply nodes, and the grids with blank areas in the layer are the demand nodes. The supply of each supply node is set to 1, and the demand of each demand node is set to the capacity of the grid corresponding to the demand node. The unit cost is set to 6. The method for arranging through-holes between layers of a 3D chip according to claim 1, characterized in that: In step 4, the entropy regularization term is introduced into the objective function of the optimal transmission model, specifically including: The objective function of defining the optimal transmission model is: h(F)=-∑ i，j F i，j logF i，j ; Among them, A i，j Represents the supply node p i To the demand node q j The cost of supplying node p i To the demand node q j The transport volume F i，j Represents the optimal transmission problem corresponding to the current layer, the i-th network nt i The number of through holes corresponding to the inter-layer through holes assigned to the j-th blank grid, F represents the transport volume F i，j The transportation planning matrix composed of , λ is the positive regularization parameter, and h(F) is the entropy of the transportation planning matrix F.

7. The method for arranging interlayer vias of a 3D chip according to claim 1, characterized in that: The transport planning matrix of the optimal transport model is solved by Sinkhorn's matrix scaling algorithm in step 4, which specifically includes: The supply nodes, demand nodes, cost matrix and regularization parameter λ of the optimal transport model are used as function inputs in the python library POT to solve the transport planning matrix F and obtain an approximate solution transport planning matrix F′.

8. The method for arranging through-holes between layers of a 3D chip according to claim 7, characterized in that: After obtaining the approximate solution transportation plan matrix F', optimize it in the following way: The approximate solution transportation plan matrix F′ is regarded as a probability matrix, where each element represents the probability of the corresponding inter-layer through hole being assigned to the corresponding grid; The inter-layer vias are sorted based on the size of the bounding box corresponding to a network. The smaller the area of ​​the bounding box of a network, the higher its priority; The interlayer vias of the network with high priority are placed first, and then the interlayer vias of the network with low priority. When placing the interlayer vias, the grids with the highest probability and meeting the grid capacity requirements in the approximate solution transportation plan matrix F′ are given priority until the final interlayer via deployment plan is obtained.

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