Heterojunction back-polished battery and preparation method thereof

Abstract

The present disclosure provides a method for preparing a heterojunction back-polished cell, comprising: performing an impurity gettering treatment on a silicon wafer; removing the phosphorus-silicate glass layer on the back of the silicon wafer; and performing a texturing treatment on the silicon wafer. The present disclosure also provides a heterojunction back-polished cell, comprising: a silicon wafer; the front side of the silicon wafer includes a first amorphous silicon layer and a first TCO film layer in sequence along a direction away from the back side of the silicon wafer; the back side of the silicon wafer includes a second amorphous silicon layer and a second TCO film layer in sequence along a direction away from the front side of the silicon wafer; the front side of the heterojunction back-polished cell includes a pyramid-shaped structure; the back side of the heterojunction back-polished cell includes a pit-shaped structure. The method for preparing a heterojunction back-polished cell provided in the present disclosure can increase the back optical path of the heterojunction cell by adding a step of removing the phosphorus-silicate glass layer, promote the secondary absorption of light in the cell, and enhance the photoelectric performance of the heterojunction cell.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a method for preparing a heterojunction back-polished cell, and a heterojunction back-polished cell prepared by the preparation method. Background Art

[0002] Heterojunction (HJT) is a type of N-type battery. It is a double-sided symmetrical structure, with double-sided power generation, high double-sidedness and low light attenuation. N-type monocrystalline silicon wafers are more suitable for thinning. Thinning of silicon wafers not only reduces the manufacturing cost of the main material, but also reduces internal recombination, reduces saturation current and increases opening voltage.

[0003] Compared with other existing solar cells, HJT cells have fewer manufacturing processes, higher process stability and lower manufacturing process temperature; however, they have high equipment investment, strict process requirements and high non-silicon manufacturing costs. In view of this, it is necessary to further improve the efficiency of heterojunction cells and reduce manufacturing costs. Summary of the invention

[0004] The present disclosure provides a method for preparing a heterojunction back-polished battery, and a heterojunction back-polished battery prepared by the preparation method.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for preparing a heterojunction back-polished cell, comprising: performing a doping treatment on a silicon wafer; removing a phosphosilicate glass layer on the back of the silicon wafer; and performing a texturing treatment on the silicon wafer.

[0006] In some embodiments, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer includes: spraying a water film on the front side of the silicon wafer; and removing the phosphosilicate glass layer on the back side of the silicon wafer by an etching solution.

[0007] In some embodiments, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer by etching solution includes: placing the silicon wafer in a mixed solution of HF and HCl for reaction to remove the phosphosilicate glass layer.

[0008] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 5-15 wt %, and the concentration of HCl is 1-10 wt %.

[0009] In some embodiments, the silicon wafer is placed in a mixed solution of HF and HCl for reaction for 1-5 minutes.

[0010] In some embodiments, in the step of placing the silicon wafer in a mixed solution of HF and HCl for reaction, the silicon wafer is transported by rollers at a speed of 2-5 m / min.

[0011] In some embodiments, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer further includes: during the process of placing the silicon wafer in a mixed solution of HF and HCl for reaction, supplementing the mixed solution of HF and HCl.

[0012] In some embodiments, the step of supplementing the mixed solution of HF and HCl includes: supplementing the mixed solution of HF and HCl accounting for 0.03%-0.08% of the total volume for every 4500-5500 half-sheet silicon wafers.

[0013] In some embodiments, the step of texturing the silicon wafer includes: during the pretreatment process, placing the silicon wafer in a mixed solution of HF and HCl for reaction at a temperature of 15-25° C., wherein the concentration of HF is 4-8wt% and the concentration of HCl is 1-5 wt%.

[0014] In some embodiments, the step of texturing the silicon wafer also includes: during the texturing process, placing the silicon wafer in a mixed solution of a texturing additive and KOH for reaction at a temperature of 75-90°C; wherein the concentration of the texturing additive is 0.5-1.3 wt%, and the concentration of KOH is 0.03-0.08 wt%.

[0015] In a second aspect, the present disclosure provides a heterojunction back-polished cell, which is prepared by the preparation method described in the first aspect of the present disclosure.

[0016] In a third aspect, the present disclosure provides a heterojunction back-polished cell, comprising: a silicon wafer; the front side of the silicon wafer comprises a first amorphous silicon layer and a first TCO film layer in sequence along the direction away from the back side of the silicon wafer; the back side of the silicon wafer comprises a second amorphous silicon layer and a second TCO film layer in sequence along the direction away from the front side of the silicon wafer; the front side of the heterojunction back-polished cell comprises a pyramid-shaped structure; the back side of the heterojunction back-polished cell comprises a pit-shaped structure.

[0017] In some embodiments, the depth of the pit-shaped structure on the back side of the heterojunction back-polished cell is 500-1000 nm.

[0018] In some embodiments, the reflectivity of the back side of the heterojunction back-polished cell is greater than or equal to 45%.

[0019] In the preparation method of the heterojunction back-polished cell of the embodiment of the present disclosure, a step of removing the phosphosilicate glass layer is added after the doping treatment, and the phosphosilicate glass layer on the back of the silicon wafer is selectively removed to complete the etching and polishing of the back of the silicon wafer, thereby improving the reflectivity of the back of the silicon wafer; it is also beneficial to the deposition of the amorphous silicon layer and the TCO film layer, thereby improving the passivation effect; it also reduces the overall deweighting of the silicon wafer, thereby improving the efficiency of the heterojunction back-polished cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a flow chart of a method for preparing a heterojunction back-polished battery in an embodiment of the present disclosure.

[0021] Figure 2A It is a schematic diagram of pre-cleaning a silicon wafer in an embodiment of the present disclosure.

[0022] Figure 2B Schematic diagram of the gettering process for a silicon wafer in an embodiment of the present disclosure.

[0023] Figure 2C Schematic diagram of removing the phosphosilicate glass layer on the back side of a silicon wafer in an embodiment of the present disclosure.

[0024] Figure 2D It is a schematic diagram of texturing a silicon wafer in an embodiment of the present disclosure.

[0025] Figure 2E It is a schematic diagram of performing amorphous silicon deposition processing on a silicon wafer in an embodiment of the present disclosure.

[0026] Figure 2F Schematic diagram of TCO film deposition process on silicon wafer in an embodiment of the present disclosure.

[0027] Figure 2G It is a schematic diagram of metallizing a silicon wafer in an embodiment of the present disclosure.

[0028] Figure 3 It is a schematic diagram of the structure of a heterojunction back-polished battery in an embodiment of the present disclosure.

[0029] Figure 4 It is a schematic diagram of the structure of a heterojunction battery prepared according to a comparative example.

[0030] Figure 5 This is an enlarged view of the back side of the silicon wafer prepared according to Example 1 of the present disclosure.

[0031] Figure 6 This is an enlarged view of the back side of the silicon wafer prepared according to Comparative Example 1. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the technical solution of the present disclosure is described in detail below with reference to the accompanying drawings.

[0033] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0034] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0035] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0038] In the first aspect, the present disclosure provides a method for preparing a heterojunction back-polished battery, referring to Figure 1 ,include:

[0039] S1, performing gettering treatment on the silicon wafer;

[0040] S2, removing the phosphosilicate glass (PSG) layer on the back side of the silicon wafer;

[0041] S3, performing texturing treatment on the silicon wafer.

[0042] In the process of preparing heterojunction cells, high-temperature gettering of silicon wafers will produce PSG layers on the front and back of the silicon wafers. The PSG layers can prevent the alkali from reacting with the silicon wafers. In some related technologies, the HJT cell preparation method includes pre-cleaning, gettering, texturing, amorphous silicon deposition, TCO deposition, and electrode printing.

[0043] The disclosed embodiment adds a step of removing the PSG layer on the back of the silicon wafer before texturing the silicon wafer, so that etching and polishing of the back of the silicon wafer can be completed after texturing, thereby improving the reflectivity of the back of the silicon wafer, which is beneficial to promoting secondary reflection of light and increasing long-wave absorption of the battery. After etching and polishing the back of the silicon wafer, the surface is smoother, and the surface dangling bonds are reduced, thereby reducing surface recombination, which is beneficial to the subsequent deposition of amorphous silicon layers and TCO film layers, and improving the passivation effect, thereby improving the efficiency of the HJT battery. By adding the step of removing the PSG layer on the back of the silicon wafer and performing single-sided texturing, the overall deweighting of the silicon wafer can also be reduced.

[0044] In the disclosed embodiments, the silicon wafer is subjected to a gettering treatment, mainly to reduce the contamination in the processing and technological process of the silicon wafer, and to reduce the minority carrier recombination centers in the silicon wafer, thereby improving the performance of the silicon wafer.

[0045] In some embodiments, before performing the gettering process on the silicon wafer, the silicon wafer is also pre-cleaned to remove impurities and damaged layers on the surface of the silicon wafer.

[0046] In some embodiments, after the silicon wafer is textured, it also includes: a step of depositing an amorphous silicon layer, utilizing the passivation effect of amorphous silicon to significantly increase the minority carrier lifetime; a step of depositing a TCO film layer, which can effectively increase the collection of carriers; and a metallization step, preparing the positive and negative electrodes of the battery through screen printing to form an ohmic contact.

[0047] Figures 2A to 2G Schematic diagram of the process flow for preparing heterojunction back-polished cells in the embodiments of the present disclosure.

[0048] like Figure 2A As shown, the silicon wafer 1 is pre-cleaned; as Figure 2B As shown, a high temperature gettering treatment is performed on the silicon wafer 1 to generate a PSG layer 2 on the front and back sides of the silicon wafer 1; Figure 2C As shown, the PSG layer on the back of the silicon wafer 1 is removed; Figure 2D As shown, the silicon wafer 1 is textured to form a pyramid structure on the front side of the silicon wafer 1, and the back side of the silicon wafer 1 is etched and polished; Figure 2E As shown, a first amorphous silicon layer 31 and a second amorphous silicon layer 32 are deposited on the surface of the silicon wafer 1, wherein an intrinsic amorphous silicon (ia-Si:H) layer 311 and a doped N-type amorphous silicon (na-Si:H) layer 312 are sequentially deposited on the front side of the silicon wafer 1, and an intrinsic amorphous silicon (ia-Si:H) layer 321 and a doped P-type amorphous silicon (pa-Si:H) layer 322 are sequentially deposited on the back side of the silicon wafer 1; Figure 2F As shown, a TCO film layer 4 is deposited on the surface of the silicon wafer 1; Figure 2G As shown, the metal electrode 5 is prepared by screen printing.

[0049] In the embodiment of the present disclosure, a PEVD method may be used to deposit an amorphous silicon layer on the surface of a silicon wafer.

[0050] In the embodiment of the present disclosure, a TCO film layer may be deposited on the surface of a silicon wafer using a PVD method.

[0051] The disclosed embodiment does not specifically limit how to remove the PSG layer on the back side of the silicon wafer.

[0052] In some embodiments, the chain PSG removal process is used to remove the phosphosilicate glass layer on the back side of the silicon wafer, and the steps include:

[0053] Spraying a water film on the front side of the silicon wafer;

[0054] The phosphosilicate glass layer on the back side of the silicon wafer is removed by etching solution.

[0055] In the method disclosed herein, there is no particular limitation on the etching solution used to remove the PSG layer on the back side of the silicon wafer, as long as the purpose of removing the PSG layer on the back side can be achieved.

[0056] In some embodiments, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer by etching solution comprises:

[0057] The silicon wafer is placed in a mixed solution of HF and HCl to react and remove the phosphosilicate glass layer.

[0058] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 5-15 wt %, and the concentration of HCl is 1-10 wt %.

[0059] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 7-9 wt %, and the concentration of HCl is 2-5 wt %.

[0060] In some embodiments, when removing the PSG layer on the back side of the silicon wafer, the silicon wafer is placed in a mixed solution of HF and HCl to react at room temperature.

[0061] In some embodiments, the silicon wafer is placed in a mixed solution of HF and HCl for reaction for 1-5 minutes.

[0062] In some embodiments, the time for removing the PSG layer on the back side of the silicon wafer is 3-4 minutes.

[0063] In some embodiments, in the step of placing the silicon wafer in a mixed solution of HF and HCl for reaction, the silicon wafer is transported by rollers at a speed of 2-5 m / min.

[0064] In some embodiments, when removing the PSG layer on the back side of the silicon wafer, the speed of transporting the silicon wafer by rollers is 3.9 m / min.

[0065] In some embodiments, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer further comprises:

[0066] In the process of placing the silicon wafer in the mixed solution of HF and HCl for reaction, the mixed solution of HF and HCl is supplemented.

[0067] In the embodiment of the present disclosure, the mixed solution of supplementing HF and HCl can ensure that the concentrations of HF and HCl in the mixed solution meet the requirements, thereby ensuring the effect of removing the PSG layer on the back side of the silicon wafer.

[0068] In some embodiments, the step of supplementing the mixed solution of HF and HCl includes: supplementing the mixed solution of HF and HCl by 0.03%-0.08% of the total volume for every 4500-5500 half-sheet silicon wafers.

[0069] In some embodiments, 0.05% of the total volume of a mixed solution of HF and HCl is added every 5000 tablets, and the concentration ratio of HF and HCl in the added mixed solution is consistent with the initial concentration ratio.

[0070] In some embodiments, the step of performing texturing on the silicon wafer comprises:

[0071] During the pretreatment process, the silicon wafer is placed in a mixed solution of HF and HCl for reaction at a temperature of 15-25° C. for 140-160 seconds, wherein the concentration of HF is 4-8wt% and the concentration of HCl is 1-5wt%.

[0072] In the disclosed embodiment, a step of removing the PSG layer on the back side of the silicon wafer is added before the texturing treatment. During the texturing treatment, a mixed solution of HF and HCl with a relatively low concentration may be used.

[0073] In some embodiments, during the texturing pretreatment process, the concentration of HF in the mixed solution of HF and HCl is 4-6 wt %, and the concentration of HCl is 1-4 wt %.

[0074] In some embodiments, during the texturing pretreatment process, the concentration of HF in the mixed solution of HF and HCl is 4-6 wt %, and the concentration of HCl is 1-1.8 wt %.

[0075] In some embodiments, during the texturing pretreatment process, the silicon wafer is placed in a mixed solution of HF and HCl for a reaction at a temperature of 20° C. for 150 seconds.

[0076] In some embodiments, the step of performing texturing on the silicon wafer further includes:

[0077] During the texturing process, the silicon wafer is placed in a mixed solution of a texturing additive and KOH for reaction at a temperature of 75-90° C. for 450-500 seconds, wherein the concentration of the texturing additive is 0.5-1.3 wt%, and the concentration of KOH is 0.03-0.08 wt%.

[0078] In some embodiments, the concentration of the texturing additive is 0.8-1.3 wt %, and the concentration of KOH is 0.05-0.08 wt %.

[0079] In some embodiments, the concentration of the texturing additive is 1.1-1.3 wt %, and the concentration of KOH is 0.06-0.08 wt %.

[0080] In some embodiments, the silicon wafer is placed in a mixed solution of a texturing additive and KOH for reaction at a temperature of 85° C. for 480 seconds.

[0081] In some embodiments, the silicon wafer is placed in a mixed solution of a texturing additive and KOH for reaction at a temperature of 80°C.

[0082] In the disclosed embodiment, a step of removing the PSG layer on the back of the silicon wafer is added before the texturing process, and during the texturing process, a texturing additive with a higher concentration is used to increase the protectiveness; further, the reaction temperature can be lowered, for example, the reaction temperature can be lowered to 80°C.

[0083] In a second aspect, an embodiment of the present disclosure provides a heterojunction back-polished cell, and the heterojunction back-polished cell is prepared by the preparation method described in the first aspect of the embodiment of the present disclosure.

[0084] In a third aspect, the present disclosure provides a heterojunction back-polished battery, referring to Figure 3 The heterojunction back-polished cell includes: a silicon wafer 1; the front side of the silicon wafer 1 includes a first amorphous silicon layer 31 and a first TCO film layer 41 in sequence along the direction away from the back side of the silicon wafer 1; the back side of the silicon wafer 1 includes a second amorphous silicon layer 32 and a second TCO film layer 42 in sequence along the direction away from the front side of the silicon wafer 1; the front side of the heterojunction back-polished cell includes a pyramid-shaped structure; the back side of the heterojunction back-polished cell includes a pit-shaped structure.

[0085] like Figure 3 As shown, the heterojunction back-polished cell also includes a metal electrode 5 .

[0086] In some embodiments, the depth of the pit-type structure on the back side of the heterojunction back-polished cell is 500-1000 nm.

[0087] In some embodiments, the depth of the pit-type structure on the back side of the heterojunction back-polished cell is 600-900 nm, for example, the depth of the pit-type structure is 800 nm.

[0088] In some embodiments, the reflectivity of the back side of the heterojunction back-polished cell is greater than or equal to 45%.

[0089] In order to enable those skilled in the art to more clearly understand the technical solution of the present disclosure, the technical solution of the present disclosure is described in detail below through specific embodiments:

[0090] Example 1

[0091] Pre-clean and absorb impurities on the silicon wafers, then load them into the silicon wafer baskets, 240 pieces / basket, and transport the silicon wafers from the baskets to the material position on the chain-type PSG machine; during the roller transport process, spray water film on the front of the silicon wafers and continue to transport them, with a transport speed of 3.8 m / min;

[0092] The silicon wafer sprayed with water film was placed in a mixed solution of 15 wt% HF and 10 wt% HCl, and reacted at room temperature for 2 min.

[0093] The silicon wafers are gradually transported from the acid tank to the water tank for dilution through roller transport, with a transport speed of 3.8 m / min.

[0094] After roller transport, water-removing roller treatment and air knife drying, the silicon wafers are transported to the flower basket via belts and subjected to the following texturing treatment:

[0095] The texturing adopts a full-slot processing method, 4 baskets / slot, 240pcs / basket, and the silicon wafers are loaded to the loading position through the flower basket;

[0096] The silicon wafer was placed in a PRE tank and reacted in a mixed solution of 0.1 wt% KOH and 3 wt% H2O2 at 65°C for 150 s.

[0097] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0098] The silicon wafer was placed in a TEX tank and reacted at 90°C for 450 seconds in a mixed solution of 1.3 wt% of the texturing additive and 0.08 wt% of KOH.

[0099] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0100] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of 0.4 wt% KOH and 4 wt% H2O2.

[0101] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0102] The silicon wafer was placed in a CP tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0103] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0104] The silicon wafer was placed in the FINAL tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at room temperature for 150 seconds.

[0105] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0106] Place the silicon wafer into the slow pull tank and keep it in the slow pull tank for 150 seconds at room temperature;

[0107] Place the silicon wafer in a drying tank at 95°C for 630 seconds;

[0108] The material cutting process is finished.

[0109] After the texturing treatment, the front side of the silicon wafer that has not been treated with PSG will grow a pyramid velvet surface, while the back side after PSG removal will be relatively flat.

[0110] Then, amorphous silicon deposition and TCO film deposition are carried out, followed by screen printing metallization and curing and sintering to complete the process preparation of the HJT cell.

[0111] Example 2

[0112] Pre-clean and absorb impurities on the silicon wafers, then load them into the silicon wafer baskets, 240 pieces / basket, and transport the silicon wafers from the baskets to the material position on the chain-type PSG machine; during the roller transport process, spray water film on the front of the silicon wafers and continue to transport them, with a transport speed of 3.8 m / min;

[0113] The silicon wafer sprayed with water film was placed in a mixed solution of 5 wt% HF and 1 wt% HCl, and reacted at room temperature for 5 min.

[0114] The silicon wafers are gradually transported from the acid tank to the water tank for dilution through roller transport, with a transport speed of 3.8 m / min.

[0115] After roller transport, water-removing roller treatment and air knife drying, the silicon wafers are transported to the flower basket via belts and subjected to the following texturing treatment:

[0116] The texturing adopts a full-slot processing method, 4 baskets / slot, 240pcs / basket, and the silicon wafers are loaded to the loading position through the flower basket;

[0117] The silicon wafer was placed in a PRE tank and reacted in a mixed solution of 0.1 wt% KOH and 3 wt% H2O2 at 65°C for 150 s.

[0118] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0119] The silicon wafer was placed in a TEX tank and reacted at 75°C for 500s in a mixed solution of 0.5 wt% of the texturing additive and 0.03 wt% of KOH.

[0120] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0121] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of 0.4 wt% KOH and 4 wt% H2O2.

[0122] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0123] The silicon wafer was placed in a CP tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0124] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0125] The silicon wafer was placed in the FINAL tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at room temperature for 150 seconds.

[0126] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0127] Place the silicon wafer into the slow pull tank and keep it in the slow pull tank for 150 seconds at room temperature;

[0128] Place the silicon wafer in a drying tank at 95°C for 630 seconds;

[0129] The material cutting process is finished.

[0130] After the texturing treatment, the front side of the silicon wafer that has not been treated with PSG will grow a pyramid velvet surface, while the back side after PSG removal will be relatively flat.

[0131] Then, amorphous silicon deposition and TCO film deposition are carried out, followed by screen printing metallization and curing and sintering to complete the process preparation of the HJT cell.

[0132] Example 3

[0133] Pre-clean and absorb impurities on the silicon wafers, then load them into the silicon wafer baskets, 240 pieces / basket, and transport the silicon wafers from the baskets to the material position on the chain-type PSG machine; during the roller transport process, spray water film on the front of the silicon wafers and continue to transport them, with a transport speed of 3.8 m / min;

[0134] The silicon wafer sprayed with water film was placed in a mixed solution of 10 wt% HF and 5 wt% HCl, and reacted at room temperature for 3 minutes.

[0135] The silicon wafers are gradually transported from the acid tank to the water tank for dilution through roller transport, with a transport speed of 3.8 m / min.

[0136] After roller transport, water-removing roller treatment and air knife drying, the silicon wafers are transported to the flower basket via belts and subjected to the following texturing treatment:

[0137] The texturing adopts a full-slot processing method, 4 baskets / slot, 240pcs / basket, and the silicon wafers are loaded to the loading position through the flower basket;

[0138] The silicon wafer was placed in a PRE tank and reacted in a mixed solution of 0.1 wt% KOH and 3 wt% H2O2 at 65°C for 150 s.

[0139] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0140] The silicon wafer was placed in a TEX tank and reacted at 82°C for 480 seconds in a mixed solution of 1 wt% texturing additive and 0.05 wt% KOH.

[0141] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0142] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of 0.4 wt% KOH and 4 wt% H2O2.

[0143] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0144] The silicon wafer was placed in a CP tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0145] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0146] The silicon wafer was placed in the FINAL tank and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at room temperature for 150 seconds.

[0147] Place the silicon wafer in a water tank at room temperature for 120 seconds;

[0148] Place the silicon wafer into the slow pull tank and keep it in the slow pull tank for 150 seconds at room temperature;

[0149] Place the silicon wafer in a drying tank at 95°C for 630 seconds;

[0150] The material cutting process is finished.

[0151] After the texturing treatment, the front side of the silicon wafer that has not been treated with PSG will grow a pyramid velvet surface, while the back side after PSG removal will be relatively flat.

[0152] Then, amorphous silicon deposition and TCO film deposition are carried out, followed by screen printing metallization and curing and sintering to complete the process preparation of the HJT cell.

[0153] Comparative Examples 1-3

[0154] The HJT cell was prepared according to the method of Examples 1-3, with the only difference being that the step of removing the phosphosilicate glass layer on the back side of the silicon wafer was omitted between the gettering process and the texturing process.

[0155] The silicon wafers in the above-mentioned embodiments and comparative examples were weighed before and after processing to calculate their weight loss, and after texturing, the reflectivity of the front and back sides of the silicon wafers was measured. The results are shown in Table 1.

[0156] Table 1

[0157]

[0158] like Figure 3 As shown, in the above embodiment, in the prepared HJT cell, the front side of the silicon wafer (C-Si) includes an intrinsic amorphous silicon (ia-Si:H) layer, a doped N-type amorphous silicon (na-Si:H) layer, and a TCO film layer in sequence, and the back side of the silicon wafer includes an intrinsic amorphous silicon (ia-Si:H) layer, a doped P-type amorphous silicon (pa-Si:H) layer, and a TCO film layer in sequence. The HJT cell also includes metal electrodes (Agfingers), and only the front side of the silicon wafer has a pyramid structure. Figure 4 As shown, in the above comparative example, in the prepared HJT cell, the front side of the silicon wafer (C-Si) includes an intrinsic amorphous silicon (ia-Si:H) layer, a doped N-type amorphous silicon (na-Si:H) layer, and a TCO film layer in sequence, and the back side of the silicon wafer includes an intrinsic amorphous silicon (ia-Si:H) layer, a doped P-type amorphous silicon (pa-Si:H or p-nc-a-Si:H) layer, and a TCO film layer in sequence. The HJT cell also includes metal electrodes (Ag fingers), and both the front and back sides of the silicon wafer are pyramid-shaped structures. A scanning electron microscope was used to take a picture of the back side of the silicon wafer after texturing. Figure 5 and Figure 6 They are enlarged views of the back side of the silicon wafer in Example 1 and Comparative Example 1, respectively. The back side of the silicon wafer in Example 1 is a pit-type structure without forming a pyramid velvet surface; the back side of the silicon wafer in Comparative Example 1 is a pyramid-type structure with a pyramid velvet surface.

[0159] It can be seen from the data in the table and the accompanying drawings that, compared with the comparative example, the silicon wafer obtained in the embodiment of the preparation method disclosed in the present invention has a reduction in overall weight loss, and the back side etching and polishing are completed after texturing to improve the back side reflectivity. The increase in back side reflectivity can promote secondary reflection of light and increase the absorption of the battery cell in the long-wave band. Back side etching and polishing make the surface of the silicon wafer smoother, reduce surface dangling bonds and reduce surface recombination, which is more conducive to the subsequent deposition of amorphous silicon and TCO, improve the passivation effect, and improve the efficiency of the HJT battery.

[0160] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for preparing a heterojunction back-polished battery, comprising: Gettering of silicon wafers; removing the phosphosilicate glass layer on the back side of the silicon wafer; Performing a texturing process on the silicon wafer; Wherein, the step of removing the phosphosilicate glass layer on the back side of the silicon wafer comprises: Spraying a water film on the front side of the silicon wafer; placing the silicon wafer in a mixed solution of HF and HCl to react and remove the phosphosilicate glass layer; In the mixed solution of HF and HCl, the concentration of HF is 5-15 wt %, and the concentration of HCl is 1-10 wt %; The silicon wafer is placed in a mixed solution of HF and HCl for a reaction time of 1-5 min; Wherein, in the step of placing the silicon wafer in a mixed solution of HF and HCl for reaction, the silicon wafer is transported by rollers at a speed of 2-5 m / min; The step of removing the phosphosilicate glass layer on the back side of the silicon wafer further comprises: In the process of placing the silicon wafer in the mixed solution of HF and HCl for reaction, the mixed solution of HF and HCl is supplemented; the mixed solution of HF and HCl accounting for 0.03%-0.08% of the total volume is supplemented for every 4500-5500 half silicon wafers.

2. The preparation method according to claim 1, wherein The step of performing texturing treatment on the silicon wafer comprises: During the pretreatment process, the silicon wafer is placed in a mixed solution of HF and HCl for reaction at a temperature of 15-25° C., wherein the concentration of HF is 4-8 wt % and the concentration of HCl is 1-5 wt %.

3. The preparation method according to claim 2, wherein The step of performing texturing treatment on the silicon wafer further includes: During the texturing process, the silicon wafer is placed in a mixed solution of a texturing additive and KOH for reaction at a temperature of 75-90° C., wherein the concentration of the texturing additive is 0.5-1.3 wt %, and the concentration of KOH is 0.03-0.08 wt %.

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