A high-precision and low-power power-off detection circuit

Abstract

The present invention provides a high-precision, low-power power-off detection circuit, comprising: a current generating module, used for generating a reference current, a power-off current and a recovery current when a power supply voltage is detected to be lower than a pre-power-off threshold voltage during a power-off process; a current comparison module, connected to the current generating module, used for comparing a reference current and a power-off current to generate a first output signal when a power supply voltage is detected to be lower than a pre-power-off threshold voltage during a power-off process; comparing a reference current and a recovery current to generate a second output signal; a control and output module, connected to the current generating module and the current comparison module; inputting the first output signal and the second output signal; generating a switch control signal, a pre-power-off signal and a recovery signal, and outputting a power-off signal; and the switch control signal and the pre-power-off signal are input to the current generating module.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-precision and low-power power-off detection circuit. Background Art

[0002] With the development of mixed-signal integrated circuits that integrate power management and emerging non-volatile memory technologies, brown-out-detection (BOD) circuits play a vital role in monitoring power supply voltages. The BOD module responds to power-down events caused by interference to ensure that the system operates normally at a sufficient power supply voltage level. When the power supply voltage drops below the minimum required voltage level, a reset signal is generated to ensure system safety.

[0003] In the traditional power-off detection circuit, there are mainly Figure 1 As shown in FIG. 1 , a power-off detection scheme is implemented based on a bandgap reference and a comparator. Figure 2 As shown, power-off detection is implemented based on a delay unit and a diode. Figure 1 In the scheme shown, when the power supply voltage starts to drop from the normal supply voltage, the power supply voltage is divided by two resistors to obtain a reference voltage related to the power supply voltage; at the same time, the bandgap reference generates a reference voltage that is not affected by the power supply voltage and temperature. The two voltages are compared by a voltage comparator, and when the power supply voltage drops to a certain threshold, the voltage comparator outputs a low level. This power-off detection structure can achieve power-off detection more accurately, but the bandgap reference, resistor divider, and voltage comparator consume a lot of static power consumption and circuit area. Figure 2 In the scheme shown, the capacitor formed by the NMOS tube N3 is fully charged by the current mirror circuit composed of the NMOS tube N1, the NMOS tube N2, the PMOS tube P1 and the PMOS tube P2 during the power-on stage. During the power-off stage, when the power supply voltage is lower than the threshold voltage of the first diode D1 and the second diode D2, the PMOS tube P4 is turned off, and the gate of the PMOS tube P3 is pulled to a low potential, thereby turning on the PMOS tube P3, releasing the charge at the gate end of the NMOS tube N3, and causing the output to flip through the inverter. The diode of this circuit can be replaced by a MOS tube with the gate and drain interconnected. Although this circuit has a simple structure and relatively low circuit power consumption, its accuracy is limited by the threshold voltage of the diode and is sensitive to the process angle, temperature, and power-off time.

[0004] In view of this, it is necessary to provide a new type of high-precision and low-power power-off detection circuit to solve the above problems in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a high-precision and low-power power-off detection circuit, which can at least solve the problems of large area, high power consumption and low reliability of the existing power-off detection circuit.

[0006] In order to achieve the above object, the present invention provides a high-precision and low-power power-off detection circuit, comprising:

[0007] The current generating module is used to generate a reference current, a power-off current and a recovery current when the power supply voltage is detected to be lower than the pre-power-off threshold voltage during the power-off process; the reference current is independent of the absolute temperature and the power supply voltage; the power-off current and the recovery current are independent of the absolute temperature and are related to the power supply voltage; wherein the output ports corresponding to the reference current, the power-off current and the recovery current are respectively denoted as V IR Terminal, V IB Terminal and V IRE end;

[0008] A current comparison module is connected to the current generation module and is used to compare the reference current with the power-off current to generate a first output signal when the power supply voltage is detected to be lower than the pre-power-off threshold voltage during the power-off process. This port is recorded as OUT B compares the reference current and the recovery current to generate a second output signal, which is recorded as OUT R end;

[0009] A control and output module, connected to the current generating module and the current comparing module; inputting the first output signal and the second output signal; generating a switch control signal, a pre-power-off signal and a recovery signal, and outputting a power-off signal; and the switch control signal and the pre-power-off signal are inputted into the current generating module; the output ports corresponding to the switch control signal, the pre-power-off signal and the recovery signal are respectively recorded as the B terminal, the Pre terminal and the Rec terminal;

[0010] During the power-off process of the power supply voltage, when the power supply voltage is lower than the pre-power-off threshold voltage, the control and output module generates the pre-power-off signal, the switch control signal jumps, and the current generating module and the current comparing module are turned on; when the power supply voltage is lower than the power-off threshold voltage, the power-off current is lower than the reference current, the first output signal output jumps, and the control and output module outputs the power-off signal to implement the power-off detection operation;

[0011] During the power-off process of the power supply voltage, if the power supply voltage returns to a normal state after being lower than the pre-power-off threshold voltage and is higher than the recovery threshold voltage, the recovery current exceeds the reference current, the second output signal output jumps, the control and output module generates the recovery signal, and the switch control signal flips, thereby turning off the current generation module and the current comparison module, and the circuit enters a voltage stable state;

[0012] Wherein, the pre-power-down threshold voltage, the power-down threshold voltage and the recovery threshold voltage satisfy the relationship V BOD <V Pre-BOD <V REC ; where V BOD Indicates the power-down threshold voltage, V Pre-BOD Indicates the pre-power-down threshold voltage, V REC Represents the recovery threshold voltage.

[0013] In an optional solution, the current generating module includes: a reference current generating circuit, which is used to generate the reference current during the power-down process of the power supply voltage;

[0014] The power-off and recovery current generating circuit is used to generate the power-off current and the recovery current during the power-off process of the power supply voltage.

[0015] In an optional solution, the reference current generating circuit includes: a first PNP transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor and a thirteenth PMOS transistor;

[0016] Wherein, the gate of the first PMOS tube P1 is connected to the Pre terminal, the drain is connected to the control and output module, and the source is connected to the gate and drain of the second PMOS tube, the gate of the third PMOS tube and the source of the fourth PMOS tube, the gate of the sixth PMOS tube, and the gate of the eleventh PMOS tube; the source terminal of the second PMOS tube is connected to the power supply voltage VDD; the source of the third PMOS tube is connected to the power supply voltage VDD, and the drain is connected to the source of the fifth PMOS tube; the gate of the fourth PMOS tube is connected to the B terminal, and the drain is connected to the drain of the first NMOS tube; the gate of the fifth PMOS tube is connected to the B terminal, and the drain is connected to the gate of the first NMOS tube and the gate and drain of the second NMOS tube; the source of the first NMOS tube is connected to one end of the first resistor; the other end of the first resistor is grounded; the source of the second NMOS tube is grounded; the source terminal of the sixth PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the seventh PMOS tube; the gate of the seventh PMOS tube is connected to the B terminal, and the drain is connected to the one end of the second resistor; the other end of the second resistor is connected to the emitter of the first PNP transistor and the gate of the third NMOS tube; the base and collector of the first PNP transistor are grounded; the source of the third NMOS tube is grounded, and the drain is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the B terminal, and the source is connected to the gate and drain of the eighth PMOS tube and the gate of the tenth PMOS tube; the source of the eighth PMOS tube is connected to the power supply voltage; the source of the tenth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the eleventh PMOS tube and the source of the twelfth PMOS tube; the source of the eleventh PMOS tube is connected to the power supply voltage; the gate of the twelfth PMOS tube is connected to the B terminal, and the drain is connected to the drain and gate of the fourth NMOS tube and the gate of the fifth NMOS tube; the source of the fourth NMOS tube is grounded; the source of the fifth NMOS tube is grounded, and the drain is connected to the gate and drain of the thirteenth PMOS tube, which end point is the VIR terminal; the source of the thirteenth PMOS tube is connected to the power supply voltage.

[0017] In an optional solution, the power-off and recovery current generating circuit includes: a second PNP transistor, a third resistor, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube and a twenty-third PMOS tube;

[0018] The source of the fourteenth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the fifteenth PMOS tube and the gate of the nineteenth PMOS tube; the gate of the fifteenth PMOS tube is connected to the B terminal, and the drain is connected to one end of the third resistor; the other end of the third resistor is connected to the emitter of the second PNP transistor and the gate of the sixth NMOS tube; the base and collector of the second PNP transistor are grounded; the source of the sixth NMOS tube is grounded, and the drain is connected to the drain of the seventeenth PMOS tube; the gate of the seventeen ... the drain of the seventeenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the B terminal, and the drain is connected to the drain of the seventeenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to The source of the 16th PMOS tube is connected to the B terminal, the source of the 16th PMOS tube is connected to the gate and drain of the 21st PMOS tube, and the gate of the 22nd PMOS tube; the source of the 16th PMOS tube is connected to the power supply voltage; the source of the 18th PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the 19th PMOS tube and the source of the 20th PMOS tube; the source of the 19th PMOS tube is connected to the power supply voltage; the gate of the 20th PMOS tube is connected to the B terminal, and the drain is connected to the gate and drain of the seventh NMOS tube, and this endpoint is the V IB The source of the seventh NMOS tube is grounded; the source of the twenty-first PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the twenty-second PMOS tube and the source of the twenty-third PMOS tube; the source of the twenty-second PMOS tube is connected to the power supply voltage; the gate of the twenty-third PMOS tube is connected to the B terminal, and the drain is connected to the gate and drain of the eighth NMOS tube, which is the endpoint of the V IRE The source of the eighth NMOS tube is grounded.

[0019] In the optional solution, the control and output module includes: a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first buffer, a second buffer, and a first NAND gate;

[0020] Among them, the drain and source of the twenty-seventh PMOS tube are connected to the power supply voltage, and the gate is connected to the drain and gate of the twelfth NMOS tube; the source of the twelfth NMOS tube is connected to the drain and gate of the thirteenth NMOS tube, and the end point is connected to the current generating module; the source of the thirteenth NMOS tube is connected to the drain and gate of the fourteenth NMOS tube; the source of the fourteenth NMOS tube is grounded; the source of the twenty-eighth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the twenty-ninth PMOS tube; the drain and gate of the twenty-ninth PMOS tube are connected to the power supply voltage, and the gate and drain are connected to the source of the twenty-ninth PMOS tube; The gate terminal of the fifteenth NMOS tube is connected to the drain of the thirty-second PMOS tube and the source of the thirty-fourth PMOS tube; the source and drain of the fifteenth NMOS tube are grounded; the source of the thirtieth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the thirty-first PMOS tube; the drain and gate of the thirty-first PMOS tube are connected to the gate of the sixteenth NMOS tube, the drain of the thirty-third PMOS tube and the source of the thirty-fifth PMOS tube; the source and drain of the sixteenth NMOS tube are grounded; the gate of the thirty-second PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the thirty-first PMOS tube; the drain and gate of the thirty-first PMOS tube are connected to the gate of the sixteenth NMOS tube, the drain of the thirty-third PMOS tube and the source of the thirty-fifth PMOS tube; the source and drain of the sixteenth NMOS tube are grounded; The gate of the thirty-fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the seventeenth NMOS tube, the drain of the eighteenth NMOS tube, the drain of the thirty-sixth PMOS tube and the input end of the fourth inverter; the gate of the thirty-fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the nineteenth NMOS tube, the drain of the twentieth NMOS tube, the drain of the thirty-seventh PMOS tube The drain of the 36th PMOS tube is connected to the power supply voltage, and the gate is connected to the B terminal; the gate of the 17th NMOS tube is connected to the external input On signal, and the source is grounded; the gate of the 18th NMOS tube is connected to the Rec terminal, and the source is grounded; the source of the 37th PMOS tube is connected to the power supply voltage, and the gate is connected to the B terminal; the gate of the 19th NMOS tube is connected to the external input On signal, and the source is grounded; the gate of the 20th NMOS tube is connected to the Rec terminal, and the source is grounded; the input of the first inverter is connected to the OUT BThe output of the first buffer is connected to the input of the first buffer; the output of the first buffer outputs the power-off signal; the output of the second inverter is connected to the input of the third inverter; the output of the third inverter is connected to an input of the first NAND gate; the other input of the first NAND gate is connected to the B terminal, and the output is the Pre terminal; the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter, which is recorded as the B_ terminal; the output of the sixth inverter is the B terminal; the input of the seventh inverter is connected to the OUTR terminal, and the output is connected to the input of the second buffer; the second buffer The output end of the inverter is connected to the gate of the thirty-eighth PMOS tube, the gate of the twenty-second NMOS tube and the gate of the twenty-third NMOS tube; the source of the thirty-eighth PMOS tube is connected to the power supply voltage, and the drain is connected to the gate and drain of the twenty-first NMOS tube and the gate of the twenty-fourth NMOS tube and the input end of the eighth inverter; the source of the twenty-first NMOS tube is connected to the drain of the twenty-second NMOS tube; the source of the twenty-second NMOS tube is connected to the drain of the twenty-third NMOS tube; the source of the twenty-third NMOS tube is grounded; the source and drain of the twenty-fourth NMOS tube are grounded; the output end of the eighth inverter is the Rec end.

[0021] In an optional solution, the current comparison module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube and a twenty-sixth PMOS tube;

[0022] The gate of the twenty-fourth PMOS tube is connected to the V IR The source is connected to the power supply voltage, the drain is connected to the drain of the ninth NMOS tube and the drain of the tenth NMOS tube, and the endpoint is the OUT B The gate of the ninth NMOS tube is connected to the V IB The gate of the tenth NMOS tube is connected to the B terminal, and the source is grounded; the gate of the twenty-fifth PMOS tube is connected to the B_ terminal, the source is connected to the power supply voltage, and the drain is connected to the drain of the twenty-sixth PMOS tube and the drain of the eleventh NMOS tube. This endpoint is the OUT R The gate of the twenty-sixth PMOS tube is connected to the V IR The gate of the eleventh NMOS tube is connected to the V IRE terminal, the source is grounded.

[0023] In an optional solution, the first inverter, the second inverter, the fourth inverter, the seventh inverter and the eighth inverter are Schmitt inverters.

[0024] The beneficial effects of the present invention are:

[0025] The present invention realizes that when the power supply voltage drops from the normal operating voltage to below the minimum required voltage (power-off threshold voltage), the power-off detection circuit generates a reliable power-off signal. The main function of the power-off signal is to reset the circuit to avoid malfunction of the integrated circuit system due to insufficient voltage.

[0026] Furthermore, when the power supply voltage works normally, the power-off detection circuit of the present invention can achieve extremely low static power consumption because the current generating module and the current comparing module are turned off.

[0027] Furthermore, the power-off detection circuit of the present invention compares a reference current and a power-off current having similar temperature characteristics but greatly different power supply voltage sensitivities. The power-off threshold voltage is insensitive to process angle and temperature (improving the accuracy of the power-off threshold voltage), and is insensitive to power supply voltage and power-off speed / power-off time.

[0028] Furthermore, the power-off and recovery current generating circuit of the power-off detection circuit of the present invention and its logic control signal can prevent the circuit from causing large static power consumption under special circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0030] Figure 1 The invention is a high-precision power-off detection circuit in the prior art.

[0031] Figure 2 The invention is a low-power-down detection circuit in the prior art.

[0032] Figure 3 4 is a circuit diagram of a high-precision, low-power power-off detection circuit in one embodiment of the present invention.

[0033] Figure 4 It is a schematic diagram of transient simulation results of normal power-off of the power-off detection circuit in one embodiment of the present invention.

[0034] Figure 5 FIG. 1 is a schematic diagram of transient simulation results of a special power-off of a power-off detection circuit in an embodiment of the present invention.

[0035] Figure 6FIG. 1 is a schematic diagram of process corner and temperature simulation results of a slow power-off detection circuit in an embodiment of the present invention.

[0036] Figure 7 Schematic diagram of process corner and temperature simulation results of rapid power-off of a power-off detection circuit in an embodiment of the present invention.

[0037] Figure 8a FIG. 4 is a schematic diagram of a Monte Carlo simulation result (power-off threshold voltage) of a power-off detection circuit under slow conditions in an embodiment of the present invention.

[0038] Figure 8b FIG. 1 is a schematic diagram of Monte Carlo simulation results (power-off threshold voltage) of a power-off detection circuit under fast conditions in an embodiment of the present invention.

[0039] Figure 9a FIG. 1 is a schematic diagram showing a change in a power-off threshold voltage of a power-off detection circuit along with a power supply voltage in an embodiment of the present invention.

[0040] Figure 9b Schematic diagram of the change of the power-off threshold voltage of the power-off detection circuit with the power-off time in one embodiment of the present invention.

[0041] Description of reference numerals:

[0042] 10-power-off detection circuit; 100-current generating module; 101-reference current generating circuit; 102-power-off and recovery current generating circuit; 200-current comparison module; 300-control and output module. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0045] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Example 1

[0048] Reference Figure 3 As shown in FIG. 9 , this embodiment provides a high-precision and low-power power-off detection circuit 10, including:

[0049] The current generating module 100 is used to generate a reference current IR, a power-off current IB and a recovery current IRE when the power supply voltage VDD is detected to be lower than the pre-power-off threshold voltage during the power-off process; the reference current IR is independent of the absolute temperature and the power supply voltage; the power-off current IB and the recovery current IRE are independent of the absolute temperature and are related to the power supply voltage; wherein the output ports corresponding to the reference current IR, the power-off current IB and the recovery current IRE are respectively denoted as V IR Terminal, V IB Terminal and V IRE end;

[0050] The current comparison module 200 is connected to the current generation module 100 and is used to compare the reference current IR with the power-down current IB to generate a first output signal OUT during the power-down process when the power supply voltage VDD is detected to be lower than the pre-power-down threshold voltage. B , this port is recorded as OUT B terminal, compares the reference current IR with the recovery current IRE, and generates a second output signal OUT R , this port is recorded as OUT R end;

[0051] The control and output module 300 is connected to the current generating module 100 and the current comparing module 200; it inputs the first output signal OUT B and the second output signal OUT R ; Generate a switch control signal B, a pre-power-down signal Pre and a recovery signal Rec, and output a power-down signal BOD; and the switch control signal B and the pre-power-down signal Pre are input to the current generating module 100, and the output ports corresponding to the switch control signal B, the pre-power-down signal Pre and the recovery signal Rec are respectively recorded as the B terminal, the Pre terminal and the Rec terminal;

[0052] During the power-off process of the power supply voltage, when the power supply voltage VDD is lower than the pre-power-off threshold voltage, the control and output module 300 generates the pre-power-off signal Pre, the switch control signal B jumps, and the current generating module 100 and the current comparing module 200 are turned on; when the power supply voltage VDD is lower than the power-off threshold voltage, the power-off current IB is lower than the reference current IR, and the first output signal OUT B Output jump, the control and output module 300 outputs a power-off signal BOD to implement a power-off detection operation;

[0053] During the power-off process, if the power voltage VDD returns to a normal state after being lower than the pre-power-off threshold voltage and is higher than the recovery threshold voltage, the recovery current IRE exceeds the reference current IR, and the second output signal OUTR The output jumps, the control and output module 300 generates a recovery signal Rec, and the switch control signal B flips, thereby turning off the current generating module 100 and the current comparing module 200, and the circuit enters a voltage stable state;

[0054] Wherein, the pre-power-down threshold voltage, the power-down threshold voltage and the recovery threshold voltage satisfy the relationship V BOD <V Pre-BOD <V REC ; where V BOD Indicates the power-down threshold voltage, V Pre-BOD Indicates the pre-power-down threshold voltage, V REC Represents the recovery threshold voltage.

[0055] Specifically, in this embodiment, the current generating module 100 includes: a reference current generating circuit 101, which is used to generate the reference current IR during the power-off process of the power supply voltage VDD; a power-off and recovery current generating circuit 102, which is used to generate the power-off current IB and the recovery current IRE during the power-off process of the power supply voltage VDD.

[0056] In this embodiment, the reference current generating circuit includes: a first PNP transistor Q1, a first resistor R1, a second resistor R2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, and a tenth PMOS transistor P10. 10 , Eleventh PMOS tube P 11 , the twelfth PMOS tube P 12 And the thirteenth PMOS tube P 13 ; Wherein, the gate of the first PMOS tube P1 is connected to the Pre terminal, and the drain is connected to the V of the control and output module C The source is connected to the gate and drain of the second PMOS tube P2, the gate of the third PMOS tube P3 and the source of the fourth PMOS tube P4, the gate of the sixth PMOS tube P6, the gate of the eleventh PMOS tube P 11The gate of the second PMOS tube P2 is connected to the power supply voltage VDD; the source of the third PMOS tube P3 is connected to the power supply voltage VDD, and the drain is connected to the source of the fifth PMOS tube P5; the gate of the fourth PMOS tube P4 is connected to the B terminal, and the drain is connected to the drain of the first NMOS tube N1; the gate of the fifth PMOS tube P5 is connected to the B terminal, and the drain is connected to the gate of the first NMOS tube N1 and the gate and drain of the second NMOS tube N2; the source of the first NMOS tube N1 is connected to one end of the first resistor R1; the other end of the first resistor R1 is grounded; the source of the second NMOS tube N2 is grounded; The source terminal of the sixth PMOS tube P6 is connected to the power supply voltage, and the drain is connected to the source of the seventh PMOS tube P7; the gate terminal of the seventh PMOS tube P7 is connected to the B terminal, and the drain is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the emitter of the first PNP transistor Q1 and the gate of the third NMOS tube N3; the base and collector of the first PNP transistor Q1 are grounded; the source of the third NMOS tube N3 is grounded, and the drain is connected to the drain of the ninth PMOS tube P9; the gate of the ninth PMOS tube P9 is connected to the B terminal, and the source is connected to the gate and drain of the eighth PMOS tube P8 and the tenth PMOS tube P 10 The gate of the eighth PMOS tube P8 is connected to the power supply voltage; the source of the tenth PMOS tube P 10 The source is connected to the power supply voltage, and the drain is connected to the eleventh PMOS tube P 11 The drain of the twelfth PMOS tube P 12 The source of the eleventh PMOS tube P 11 The source of the twelfth PMOS tube P 12 The gate of the fourth NMOS tube N4 is connected to the B terminal, and the drain is connected to the drain and gate of the fourth NMOS tube N4 and the gate of the fifth NMOS tube N5; the source of the fourth NMOS tube N4 is grounded; the source of the fifth NMOS tube N5 is grounded, and the drain is connected to the thirteenth PMOS tube P 13 The gate and drain terminals are the V IR The thirteenth PMOS tube P 13 The source is connected to the supply voltage.

[0057] In this embodiment, the power-off and recovery current generating circuit 102 includes: a second PNP transistor Q2, a third resistor R3, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a fourteenth PMOS transistor P 14 15th PMOS tube P 1516th PMOS tube P 16 17th PMOS tube P 17 18th PMOS tube P 18 19th PMOS tube P 19 、20th PMOS tube P 20 、21st PMOS tube P 21 22nd PMOS tube P 22 And the twenty-third PMOS tube P 23 ; wherein the fourteenth PMOS tube P 14 The source is connected to the power supply voltage, and the gate and drain are connected to the fifteenth PMOS tube P 15 The source of the nineteenth PMOS tube P 19 The gate of the fifteenth PMOS tube P 15 The gate of the transistor is connected to the B terminal, and the drain is connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to the emitter of the second PNP transistor Q2 and the gate of the sixth NMOS transistor N6; the base and collector of the second PNP transistor Q2 are grounded; the source of the sixth NMOS transistor N6 is grounded, and the drain is connected to the seventeenth PMOS transistor P 17 The drain of the seventeenth PMOS tube P 17 The gate is connected to the B terminal, and the source is connected to the sixteenth PMOS tube P 16 The gate and drain of the twenty-first PMOS tube P 21 The gate and the twenty-second PMOS tube P 22 The gate of the sixteenth PMOS tube P 16 The source of the eighteenth PMOS tube P 18 The source is connected to the power supply voltage, and the drain is connected to the nineteenth PMOS tube P 19 The drain of the 20th PMOS tube P 20 The source of the nineteenth PMOS tube P 19 The source of the 20th PMOS tube P 20 The gate of the transistor is connected to the B terminal, and the drain is connected to the gate and drain of the seventh NMOS transistor N7. The endpoint is the V IB The source of the seventh NMOS tube N7 is grounded; the twenty-first PMOS tube P 21 The source is connected to the power supply voltage, and the drain is connected to the twenty-second PMOS tube P 22 The drain of the twenty-third PMOS tube P 23 The source of the twenty-second PMOS tube P 22The source of the twenty-third PMOS tube P 23 The gate of the transistor is connected to the B terminal, and the drain is connected to the gate and drain of the eighth NMOS transistor N8. The endpoint is the V IRE The source of the eighth NMOS tube N8 is grounded.

[0058] The reference current IR provided by the reference current generating circuit 101 is equal to m1I PTAT +m2I CTAT ; where I PTAT and I CTAT Respectively represent the current with a positive temperature coefficient and the current with a negative temperature coefficient, and m1 and m2 respectively represent the coefficients of the two currents scaled by the current mirror. By setting a suitable current mirror scaling ratio, a reference current IR with a temperature coefficient close to zero can be generated. The working principle of the power-off and recovery current generating circuit 102 is similar, and both the power-off current IB and the recovery current IRE are achieved by a positive temperature coefficient and a negative temperature coefficient to have a temperature coefficient close to zero. The positive temperature coefficient current and the negative temperature coefficient current that constitute the reference current IR are little affected by the power supply voltage within the range where the power supply is greater than the power-off threshold voltage, so the reference current is little affected by the power supply voltage. On the contrary, the two positive temperature coefficient currents and negative temperature coefficient currents that constitute the power-off current and the recovery current come from the bias, and their current magnitudes are very sensitive to the power supply voltage magnitude. Since the above-mentioned currents exhibit similar temperature characteristics and completely different power supply characteristics, an accurate power-off threshold voltage can be obtained through the current comparison module 200.

[0059] The current comparison module 200 includes a ninth NMOS transistor N9, a tenth NMOS transistor N 10 、11th NMOS tube N 11 、24th PMOS tube P 24 25. PMOS tube P 25 And the twenty-sixth PMOS tube P 26 ; wherein the twenty-fourth PMOS tube P 24 The gate is connected to the V IR The source is connected to the power supply voltage, and the drain is connected to the drain of the ninth NMOS tube N9 and the drain of the tenth NMOS tube N 10 The drain of the B The gate of the ninth NMOS tube N9 is connected to the V IB The tenth NMOS tube N 10 The gate of the twenty-fifth PMOS tube P is connected to the B terminal, and the source is grounded; 25 The gate is connected to the B_ terminal, the source is connected to the power supply voltage, and the drain is connected to the twenty-sixth PMOS tube P 26The drain of the eleventh NMOS tube N 11 The drain of the R The twenty-sixth PMOS tube P 26 The gate is connected to the V IR The source of the eleventh NMOS tube N 11 The gate is connected to the V IRE terminal, the source is grounded.

[0060] The tenth NMOS transistor N in the current comparison module 200 10 And the twenty-fifth PMOS tube P 25 It is used to prevent the current comparison module from generating erroneous output due to signal interference before the pre-power-down signal arrives.

[0061] The control and output module includes: a twenty-seventh PMOS tube P 27 、28th PMOS tube P 28 、29th PMOS tube P 29 、30th PMOS tube P 30 、31st PMOS tube P 31 、32nd PMOS tube P 32 、33rd PMOS tube P 33 、34th PMOS tube P 34 、35th PMOS tube P 35 、36th PMOS tube P 36 、37 PMOS tube P 37 、38 PMOS tube P 38 , the twelfth NMOS tube N 12 、Thirteenth NMOS tube N 13 , the fourteenth NMOS tube N 14 , the fifteenth NMOS tube N 15 , the sixteenth NMOS tube N 16 , Seventeenth NMOS tube N 17 , the eighteenth NMOS tube N 18 , the nineteenth NMOS tube N 19 、The 20th NMOS tube N 20 、The twenty-first NMOS tube N 21 、22nd NMOS tube N 22 、23rd NMOS tube N 23 、24th NMOS tube N 24, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first buffer Buffer1, a second buffer Buffer1, and a first NAND gate NAND1; wherein the twenty-seventh PMOS tube P 27 The drain and source are connected to the power supply voltage, and the gate is connected to the twelfth NMOS tube N 12 The drain and gate of the twelfth NMOS tube N 12 The source of the thirteenth NMOS tube N 13 The drain and gate of the C terminal (connected to the drain of the first PMOS tube P1); the thirteenth NMOS tube N 13 The source of the fourteenth NMOS tube N 14 The drain and gate of the fourteenth NMOS tube N 14 The source of the twenty-eighth PMOS tube P 28 The source is connected to the power supply voltage, and the gate and drain are connected to the twenty-ninth PMOS tube P 29 The source of the twenty-ninth PMOS tube P 29 The drain and gate of the fifteenth NMOS tube N 15 The gate terminal and the thirty-second PMOS tube P 32 The drain and the thirty-fourth PMOS tube P 34 The source of the fifteenth NMOS tube N 15 The source and drain of the 30th PMOS tube P 30 The source is connected to the power supply voltage, and the gate and drain are connected to the thirty-first PMOS tube P 31 The source of the thirty-first PMOS tube P 31 The drain and gate of the sixteenth NMOS tube N 16 The gate of the thirty-third PMOS tube P 33 The drain and the thirty-fifth PMOS tube P 35 The source of the sixteenth NMOS tube N 16 The source and drain of the thirty-second PMOS tube P 32 The gate terminal is connected to the external input On signal, and the source is connected to the power supply voltage; the thirty-third PMOS tube P 33 The gate is connected to the external input On_ signal, and the source is connected to the power supply voltage; the thirty-fourth PMOS tube P 34 The gate is connected to the power supply voltage, and the drain is connected to the seventeenth NMOS tube N17 The drain of the eighteenth NMOS tube N 18 The drain of the thirty-sixth PMOS tube P 36 and the input terminal of the fourth inverter INV4; the thirty-fifth PMOS tube P 35 The gate is connected to the power supply voltage, and the drain is connected to the nineteenth NMOS tube N 19 The drain of the 20th NMOS tube N 20 The drain of the thirty-seventh PMOS tube P 37 and the drain of the second inverter INV2; the thirty-sixth PMOS tube P 36 The source of the seventeenth NMOS tube N is connected to the power supply voltage, and the gate is connected to the B terminal; 17 The gate of the eighteenth NMOS tube N is connected to the external input On signal, and the source is grounded; 18 The gate of the thirty-seventh PMOS tube P is connected to the Rec terminal, and the source is grounded; 37 The source of the nineteenth NMOS tube N is connected to the power supply voltage, and the gate is connected to the B terminal; 19 The gate of the 20th NMOS tube N is connected to the external input On signal, and the source is grounded; 20 The gate of the first inverter INV1 is connected to the OUT terminal, and the source is grounded; the input of the first inverter INV1 is connected to the OUT terminal. B The output of the first buffer Buffer1 is connected to the input of the first buffer Buffer1; the output of the first buffer Buffer1 outputs the power-off signal; the output of the second inverter INV2 is connected to the input of the third inverter INV3; the output of the third inverter INV3 is connected to an input of the first NAND gate NAND1; the other input of the first NAND gate NAND1 is connected to the B terminal, and the output is the Pre terminal; the output of the fourth inverter INV4 is connected to the input of the fifth inverter INV5, and the output of the fifth inverter INV5 is connected to the input of the sixth inverter INV6, which is recorded as the B_ terminal; the output of the sixth inverter INV6 is the B terminal; the input of the seventh inverter INV7 is connected to the OUT R The output end of the second buffer Buffer2 is connected to the input end of the third PMOS tube P 38 The gate of the twenty-second NMOS tube N 22 The gate and the twenty-third NMOS tube N 23 The gate of the thirty-eighth PMOS tube P 38The source is connected to the power supply voltage, and the drain is connected to the twenty-first NMOS tube N 21 The gate and drain of the twenty-fourth NMOS tube N 24 The gate of the eighth inverter INV8 and the input end of the eighth inverter INV8; the twenty-first NMOS tube N 21 The source of the 22nd NMOS tube N 22 The drain of the twenty-second NMOS tube N 22 The source of the twenty-third NMOS tube N 23 The drain of the twenty-third NMOS tube N 23 The source of the twenty-fourth NMOS tube N 24 The source and drain of the eighth inverter INV8 are grounded; the output end of the eighth inverter INV8 is the Rec end.

[0062] In this embodiment, the first inverter, the second inverter, the fourth inverter, the seventh inverter and the eighth inverter are Schmitt inverters.

[0063] Among them, the switch control signal B and the pre-power-off signal Pre generated by the control and output module 300 are affected by the threshold voltage of the transistor. Specifically, the pre-power-off signal Pre is a pulse signal used to activate the reference current generating circuit. Specifically, the positive temperature coefficient current generator of the reference current is first activated (the current generator includes the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the first NMOS tube N1, the second NMOS tube N2 and the first resistor R1), and then a negative temperature coefficient reference current is generated through a current mirror to obtain the final reference current. The switch control signal B is a switch control signal used to activate the current generating module 100 after detecting a power-off event. The fifteenth NMOS tube N 15 and the sixteenth NMOS tube N 16 Acting as two identical capacitors, the twenty-eighth PMOS tube P 28 29th PMOS tube P 29 The 30th PMOS tube P 30 The thirty-first PMOS tube P 31 The capacitor is connected as a diode to prevent charge leakage. During the period when the power supply voltage drops, the capacitor voltage remains unchanged. When the voltage difference between the power supply voltage and the capacitor voltage causes the thirty-fourth PMOS tube P acting as a switch to 34 When turned on, the switch control signal B switches to logic "0". This threshold voltage is called the pre-power-down threshold voltage V Pre-BOD The thirty-second PMOS tube P 32 、33rd PMOS tube P 33、36th PMOS tube P 36 And the thirty-seventh PMOS tube P 37 The purpose of this is to prevent charge leakage during a slow power-down event. 34 And the thirty-fifth PMOS tube P 35 Depending on the size of the switch, different switch threshold voltages can be obtained, thereby generating a pre-power-down signal Pre through a logic element.

[0064] The control and output module 300 receives the second output signal OUT from the current comparison module 200. R Connected to the seventh inverter INV7. Through the thirty-eighth PMOS tube P 38 21st NMOS tube N 21 22nd NMOS tube N 22 23rd NMOS tube N 23 24th NMOS tube N 24 A small delay module composed of a power-on reset circuit generates a pre-power-off signal Rec to reset the switch control signal B. The On signal is provided by an external power-on reset circuit. The On_ signal is the direction signal of the On signal. When the system is powered on or recovers from an unstable state, the switch control signal B is refreshed and the current generation module is turned off, thereby achieving extremely low static power consumption.

[0065] In this embodiment, during the power-off process of the power supply voltage, the power-off detection is divided into two stages; the first stage is the pre-power-off detection process, in which the control and output module 300 generates a pre-power-off detection of the power supply voltage. When the power supply voltage is lower than the pre-power-off threshold voltage, a pre-power-off signal is generated and the current generating module 100 and the current comparing module 200 are turned on. The second stage is the precise power-off detection process, by comparing the reference current and the power-off current, which have similar temperature characteristics but very different power sensitivity characteristics. When the power supply voltage is lower than the power-off threshold voltage, the output of the current comparison module used for power-off detection jumps (the power-off current is lower than the reference current, and the first output signal OUT of the current comparison module is higher than the reference current). B The control and output module 300 generates a precise power-off signal BOD for output to implement the power-off detection operation. If the power supply voltage returns to normal after being lower than the pre-power-off threshold voltage and is higher than the recovery threshold voltage, the recovery current exceeds the reference current, and the second output signal OUT R When the power supply voltage of the power-off detection circuit is working normally, the current generating module and the current comparing module are turned off.

[0066] The function of the recovery current is to protect the circuit in a special scenario and turn off the current generating module to achieve low static power consumption; when the power supply voltage is lower than the pre-power-off threshold voltage, the current generating module is activated. During the normal power-off process, when the power-off voltage is lower than the power-off threshold voltage, the circuit will no longer consume power as the power supply voltage drops to zero. If the power supply is lower than the power-off threshold voltage and then returns to the normal voltage, the circuit can enter a low power consumption state through an external power-on signal. However, in a special case, the power supply voltage drops below the pre-power-off threshold voltage and then returns to the normal working voltage. If there is no recovery signal control circuit, the current generating module will be turned on all the time, resulting in large static power consumption. In this embodiment, in the current generating module, a recovery current for comparison with the reference current is generated. When the power supply voltage recovers to exceed the recovery threshold voltage, the recovery current exceeds the reference current, causing the output of the current comparator used for the recovery signal to flip, and the control and output module generates a recovery signal to control the shutdown of the current generating module and the current comparison module, thereby achieving extremely low static power consumption.

[0067] Refer to the following Figure 3 9 , a method for realizing power-off detection by the power-off detection circuit 10 is described in detail.

[0068] The power supply voltage is in normal working state, the switch control signal B of the power-off detection circuit is high level, the current generating module in the circuit is in off state, and the output first output signal OUT of the current comparison module is B and the second output signal OUT R They are low level and high level respectively. As the power supply voltage starts to drop, when the power supply voltage drops below the pre-power-off threshold voltage, the switch control signal B (B terminal) jumps to a low level, and the pre-power-off signal Pre is generated, activating the reference current generating circuit. The two currents of the power-off current meter are a reference current that is almost independent of absolute temperature and power supply voltage, and a power-off current that is almost independent of absolute temperature and related to power supply voltage; under normal power-off conditions, the power-off current continues to decrease as the power supply voltage drops until the power supply voltage is lower than the power-off threshold voltage, the power-off current is lower than the reference current, and the first output signal OUT of the current comparison module is B Flip to high level, and get the final power-off signal BOD through Schmitt trigger and buffer. In special power-off situation, the power supply voltage returns to normal state after falling below the pre-power-off threshold voltage. The two currents of the recovery current comparison are the reference current which has almost nothing to do with absolute temperature and power supply voltage, and the recovery current which has almost nothing to do with absolute temperature and is related to power supply voltage. When the power supply voltage is higher than the recovery threshold voltage, the recovery current exceeds the reference current, and the second output signal OUT RAfter passing through the Schmitt inverter, buffer and small delay module, a recovery signal Rec is generated, and the switch control signal B is flipped to a high level, thereby turning off the current generation module, and the circuit enters a voltage stable state with extremely low static power consumption.

[0069] like Figure 4 As shown, when the power supply voltage is at a normal working voltage, the circuit static power consumption is extremely low. When the power supply is powered off normally, the power-off detection circuit generates a reliable power-on and power-off signal.

[0070] like Figure 5 As shown, when the power supply voltage is at the normal working voltage, the circuit static power consumption is extremely low. When the power supply is specially powered off, when the power supply voltage is lower than the pre-power-off threshold voltage, the current generating circuit is turned on, and when the power supply rises to the recovery threshold voltage, the switch control signal B jumps to a high level, and the circuit enters a voltage stable state, and the static power consumption is extremely low.

[0071] like Figure 6 As shown, under different temperatures and process angles, the power-off detection circuit works normally in a slow power-off condition with high accuracy.

[0072] like Figure 7 As shown, under different temperatures and process angles, the power-off detection circuit works normally in a fast power-off situation with high accuracy.

[0073] like Figure 8a and Figure 8b As shown, in 1000 Monte Carlo simulations, the power-off threshold voltage deviation of the power-off signal generated by the power-off detection circuit in both slow (power-off time of 10ms) and fast (power-off time of 100μs) power-off conditions is small, and it has reliability and high precision.

[0074] like Figure 9a and Figure 9b As shown, under different power supply voltages and power-off time conditions, the power-off threshold voltage deviation of the power-off signal generated by the power-off detection circuit is small, and has reliability and high precision.

[0075] It can be seen that the high-precision, low-power power-off detection circuit of this embodiment has the following beneficial effects: 1) The power-off detection circuit can achieve extremely low static power consumption when the power supply voltage is working normally; 2) The power-off detection circuit can achieve a precise power-off threshold voltage and is insensitive to process angle and temperature. 3) The power-off and recovery current generation circuit of the power-off detection circuit and its logic control signal can prevent the circuit from causing large static power consumption under special circumstances. 4) The power-off detection circuit is not sensitive to the power supply voltage and power-off time.

[0076] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-precision, low-power power-off detection circuit, characterized in that: include: A current generating module, used for generating a reference current, a power-off current and a recovery current when the power supply voltage is detected to be lower than a pre-power-off threshold voltage during the power-off process; the reference current is independent of absolute temperature and power supply voltage; The power-off current and the recovery current are independent of absolute temperature and are related to the power supply voltage; wherein the output ports corresponding to the reference current, the power-off current and the recovery current are respectively denoted as V IR Terminal, V IB Terminal and V IRE end; A current comparison module is connected to the current generation module and is used to compare the reference current with the power-off current to generate a first output signal when the power supply voltage is detected to be lower than the pre-power-off threshold voltage during the power-off process. This port is recorded as OUT B compares the reference current and the recovery current to generate a second output signal, which is recorded as OUT R end; A control and output module, connected to the current generating module and the current comparing module; inputting the first output signal and the second output signal; generating a switch control signal, a pre-power-off signal and a recovery signal, and outputting a power-off signal; and the switch control signal and the pre-power-off signal are inputted into the current generating module; the output ports corresponding to the switch control signal, the pre-power-off signal and the recovery signal are respectively recorded as the B terminal, the Pre terminal and the Rec terminal; During the power-off process of the power supply voltage, when the power supply voltage is lower than the pre-power-off threshold voltage, the control and output module generates the pre-power-off signal, the switch control signal jumps, and the current generating module and the current comparing module are turned on; when the power supply voltage is lower than the power-off threshold voltage, the power-off current is lower than the reference current, the first output signal output jumps, and the control and output module outputs the power-off signal to implement the power-off detection operation; During the power-off process of the power supply voltage, if the power supply voltage returns to a normal state after being lower than the pre-power-off threshold voltage and is higher than the recovery threshold voltage, the recovery current exceeds the reference current, the second output signal output jumps, the control and output module generates the recovery signal, and the switch control signal flips, thereby turning off the current generation module and the current comparison module, and the circuit enters a voltage stable state; Wherein, the pre-power-down threshold voltage, the power-down threshold voltage and the recovery threshold voltage satisfy the relationship V BOD <V Pre-BOD <V REC ; where V BOD Indicates the power-down threshold voltage, V Pre-BOD Indicates the pre-power-down threshold voltage, V REC Represents the recovery threshold voltage.

2. The high-precision, low-power power-off detection circuit according to claim 1, characterized in that: The current generating module comprises: A reference current generating circuit, used for generating the reference current when the power supply voltage is powered down; The power-off and recovery current generating circuit is used to generate the power-off current and the recovery current during the power-off process of the power supply voltage.

3. The high-precision, low-power power-off detection circuit according to claim 2, characterized in that: The reference current generating circuit includes: a first PNP transistor, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube; Among them, the gate of the first PMOS tube P1 is connected to the Pre terminal, the drain is connected to the control and output module, and the source is connected to the gate and drain of the second PMOS tube, the gate of the third PMOS tube and the source of the fourth PMOS tube, the gate of the sixth PMOS tube, and the gate of the eleventh PMOS tube; the source terminal of the second PMOS tube is connected to the power supply voltage VDD; the source of the third PMOS tube is connected to the power supply voltage VDD, and the drain is connected to the source of the fifth PMOS tube; the gate of the fourth PMOS tube is connected to the B terminal, and the drain is connected to the drain of the first NMOS tube; the gate of the fifth PMOS tube is connected to the B terminal, The drain of the first NMOS tube is connected to the gate of the first NMOS tube and the gate and drain of the second NMOS tube; the source of the first NMOS tube is connected to one end of the first resistor; the other end of the first resistor is grounded; the source of the second NMOS tube is grounded; the source end of the sixth PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the seventh PMOS tube; the gate end of the seventh PMOS tube is connected to the B end, and the drain is connected to one end of the second resistor; the other end of the second resistor is connected to the emitter of the first PNP transistor and the gate of the third NMOS tube; the base and collector of the first PNP transistor are grounded; the source of the third NMOS tube is grounded, and the drain is connected to the drain of the ninth PMOS tube; the ninth The gate of the PMOS tube is connected to the B terminal, and the source is connected to the gate and drain of the eighth PMOS tube and the gate of the tenth PMOS tube; the source of the eighth PMOS tube is connected to the power supply voltage; the source of the tenth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the eleventh PMOS tube and the source of the twelfth PMOS tube; the source of the eleventh PMOS tube is connected to the power supply voltage; the gate of the twelfth PMOS tube is connected to the B terminal, and the drain is connected to the drain and gate of the fourth NMOS tube and the gate of the fifth NMOS tube; the source of the fourth NMOS tube is grounded; the source of the fifth NMOS tube is grounded, and the drain is connected to the gate and drain of the thirteenth PMOS tube, and the endpoints are the V IR The source of the thirteenth PMOS tube is connected to the power supply voltage.

4. The high-precision, low-power power-off detection circuit according to claim 2, characterized in that: The power-off and recovery current generating circuit comprises: a second PNP transistor, a third resistor, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube and a twenty-third PMOS tube; The source of the fourteenth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the fifteenth PMOS tube and the gate of the nineteenth PMOS tube; the gate of the fifteenth PMOS tube is connected to the B terminal, and the drain is connected to one end of the third resistor; the other end of the third resistor is connected to the emitter of the second PNP transistor and the gate of the sixth NMOS tube; the base and collector of the second PNP transistor are grounded; the source of the sixth NMOS tube is grounded, and the drain is connected to the drain of the seventeenth PMOS tube; the gate of the seventeen ... the drain of the seventeenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the B terminal, and the drain is connected to the drain of the seventeenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to the B terminal, and the drain of the seventeenth PMOS tube is connected to The source of the 16th PMOS tube is connected to the B terminal, the source is connected to the gate and drain of the 16th PMOS tube, the gate of the 21st PMOS tube, and the gate of the 22nd PMOS tube; the source of the 16th PMOS tube is connected to the power supply voltage; the source of the 18th PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the 19th PMOS tube and the source of the 20th PMOS tube; the source of the 19th PMOS tube is connected to the power supply voltage; the gate of the 20th PMOS tube is connected to the B terminal, and the drain is connected to the gate and drain of the 7th NMOS tube, and the endpoints are the V IB The source of the seventh NMOS tube is grounded; the source of the twenty-first PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the twenty-second PMOS tube and the source of the twenty-third PMOS tube; the source of the twenty-second PMOS tube is connected to the power supply voltage; the gate of the twenty-third PMOS tube is connected to the B terminal, and the drain is connected to the gate and drain of the eighth NMOS tube, and the endpoint is the V IRE The source of the eighth NMOS tube is grounded.

5. The high-precision, low-power power-off detection circuit according to claim 1, characterized in that: The control and output module includes: a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first buffer, a second buffer, and a first NAND gate; The drain and source of the twenty-seventh PMOS tube are connected to the power supply voltage, and the gate is connected to the drain and gate of the twelfth NMOS tube; the source of the twelfth NMOS tube is connected to the drain and gate of the thirteenth NMOS tube, and the endpoints are connected to the current generating module; the source of the thirteenth NMOS tube is connected to the drain and gate of the fourteenth NMOS tube; the source of the fourteenth NMOS tube is grounded; the source of the twenty-eighth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the twenty-ninth PMOS tube; the drain and gate of the twenty-ninth PMOS tube are connected to the The gate terminal of the fifteenth NMOS tube is connected to the drain of the thirty-second PMOS tube and the source of the thirty-fourth PMOS tube; the source and drain of the fifteenth NMOS tube are grounded; the source of the thirtieth PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the thirty-first PMOS tube; the drain and gate of the thirty-first PMOS tube are connected to the gate of the sixteenth NMOS tube, the drain of the thirty-third PMOS tube and the source of the thirty-fifth PMOS tube; the source and drain of the sixteenth NMOS tube are grounded; the gate terminal of the thirty-second PMOS tube is connected to the power supply voltage, and the gate and drain are connected to the source of the thirty-first PMOS tube; the drain and gate of the thirty-first PMOS tube are connected to the gate of the sixteenth NMOS tube, the drain of the thirty-third PMOS tube and the source of the thirty-fifth PMOS tube; the source and drain of the sixteenth NMOS tube are grounded; The gate of the thirty-fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the seventeenth NMOS tube, the drain of the eighteenth NMOS tube, the drain of the thirty-sixth PMOS tube and the input end of the fourth inverter; the gate of the thirty-fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the nineteenth NMOS tube, the drain of the twentieth NMOS tube, the drain of the thirty-seventh PMOS tube, and the input end of the fourth inverter. The drain of the 36th PMOS tube is connected to the power supply voltage, and the gate is connected to the B terminal; the gate of the 17th NMOS tube is connected to the external input On signal, and the source is grounded; the gate of the 18th NMOS tube is connected to the Rec terminal, and the source is grounded; the source of the 37th PMOS tube is connected to the power supply voltage, and the gate is connected to the B terminal; the gate of the 19th NMOS tube is connected to the external input On signal, and the source is grounded; the gate of the 20th NMOS tube is connected to the Rec terminal, and the source is grounded; the input of the first inverter is connected to the OUT B The output of the first buffer is connected to the input of the first buffer; the output of the first buffer outputs the power-off signal; the output of the second inverter is connected to the input of the third inverter; the output of the third inverter is connected to an input of the first NAND gate; the other input of the first NAND gate is connected to the B terminal, and the output is the Pre terminal; the output of the fourth inverter is connected to the input of the fifth inverter, the output of the fifth inverter is connected to the input of the sixth inverter, and the endpoint is recorded as the B_ terminal; the output of the sixth inverter is the B terminal; the input of the seventh inverter is connected to the OUT R The output end is connected to the input end of the second buffer; the output end of the second buffer is connected to the gate of the thirty-eighth PMOS tube, the gate of the twenty-second NMOS tube and the gate of the twenty-third NMOS tube; the source of the thirty-eighth PMOS tube is connected to the power supply voltage, and the drain is connected to the gate and drain of the twenty-first NMOS tube and the gate of the twenty-fourth NMOS tube and the input end of the eighth inverter; the source of the twenty-first NMOS tube is connected to the drain of the twenty-second NMOS tube; the source of the twenty-second NMOS tube is connected to the drain of the twenty-third NMOS tube; the source of the twenty-third NMOS tube is grounded; the source and drain of the twenty-fourth NMOS tube are grounded; the output end of the eighth inverter is the Rec end.

6. The high-precision, low-power power-off detection circuit according to claim 5, characterized in that: The current comparison module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube and a twenty-sixth PMOS tube; The gate of the twenty-fourth PMOS tube is connected to the V IR The source is connected to the power supply voltage, the drain is connected to the drain of the ninth NMOS tube and the drain of the tenth NMOS tube, and the endpoint is the OUT B The gate of the ninth NMOS tube is connected to the V IB The gate of the tenth NMOS tube is connected to the B terminal, and the source is grounded; the gate of the twenty-fifth PMOS tube is connected to the B_ terminal, the source is connected to the power supply voltage, the drain is connected to the drain of the twenty-sixth PMOS tube and the drain of the eleventh NMOS tube, and the endpoint is the OUT R The gate of the twenty-sixth PMOS tube is connected to the V IR The gate of the eleventh NMOS tube is connected to the V IRE terminal, the source is grounded.

7. The high-precision, low-power power-off detection circuit according to claim 5, characterized in that: The first inverter, the second inverter, the fourth inverter, the seventh inverter and the eighth inverter are Schmitt inverters.

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