A process method for reducing ohmic contact resistance and laser chip

Abstract

The present application proposes a process method and a laser chip for reducing ohmic contact resistance, the method comprising: growing a diffusion barrier layer on the surface of a wafer and performing an annealing treatment to form Ga vacancies in the wafer; performing photolithography on the diffusion barrier layer to form a diffusion window, and performing conductive medium diffusion to fill the Ga vacancies with the conductive medium. The process method proposed in the present application can reduce ohmic contact resistance, thereby improving product reliability and product yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a process method for reducing ohmic contact resistance and a laser chip. Background Art

[0002] In the field of optical communications, resistance is an important indicator for evaluating product performance.

[0003] Many products in the prior art have excessively high resistance, which can affect product reliability and further affect product yield.

[0004] The prior art lacks a process method capable of reducing ohmic contact resistance. Summary of the invention

[0005] To solve the above problems, the embodiments of the present application provide a process method for reducing ohmic contact resistance and a laser chip, which can reduce the potential barrier on the surface of the semiconductor, thereby reducing the ohmic contact resistance.

[0006] The present application embodiment adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a process for reducing ohmic contact resistance, the method comprising the following steps:

[0008] Growing a diffusion barrier layer on the surface of the wafer and performing annealing to form Ga vacancies in the wafer;

[0009] The diffusion barrier layer is photolithographically processed to form a diffusion window, and then the conductive medium is diffused to fill the Ga vacancies.

[0010] In some embodiments, the wafer is made of InGaAs material.

[0011] In some embodiments, the diffusion barrier layer is a SiO2 film.

[0012] In some embodiments, the diffusion barrier layer has a thickness of 200-700 nm.

[0013] In some embodiments, the diffusion barrier layer is deposited on the wafer surface by a PECVD process.

[0014] In some embodiments, the annealing process is performed at a temperature of 800-1000°C.

[0015] In some embodiments, the annealing time is 1-3 minutes.

[0016] In some embodiments, the conductive medium is Zn.

[0017] In some embodiments, the temperature of the diffusion is 470-550°C.

[0018] In a second aspect, an embodiment of the present application further provides a laser chip obtained by any of the above-mentioned process methods for reducing ohmic contact resistance.

[0019] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0020] The process method for reducing ohmic contact resistance provided by the present application is to deposit a SiO2 film on the surface of the wafer by PECVD before opening the window, and then perform rapid annealing to form more Ga vacancies; after impurity diffusion, Zn fills the Ga vacancies to increase the concentration of carriers, thereby reducing the potential barrier on the semiconductor surface and reducing the ohmic contact resistance. The method provided by the present application can improve the reliability of the product and the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A flow chart showing a process method for reducing ohmic contact resistance according to an embodiment of the present application;

[0023] Figure 2 A schematic diagram showing a growth diffusion barrier layer according to an embodiment of the present application;

[0024] Figure 3 A schematic diagram showing a diffusion window after being formed according to an embodiment of the present application;

[0025] Figure 4 A schematic diagram is shown after a diffusion region is formed according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The exemplary embodiments of the present application will be described in more detail below. However, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0027] The disclosure of the present invention provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described in the present invention. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0028] Generally, the terms may be understood at least in part based on the usage of the above invention. For example, the term "one or more" used in the present invention depends at least in part on the above invention, and may be used to describe any component, structure or feature in a singular form, or may be used to describe a combination of components, structures or features in a plural form. Similarly, terms such as "one", "an" or "the" may also be understood at least in part based on the above invention as conveying singular usage or conveying plural usage. In addition, the term "based on..." may be understood as not necessarily intended to convey a set of exclusive factors, but may alternatively, at least in part depending on the context, allow for the presence of additional factors that do not necessarily have to be explicitly described.

[0029] It should be noted that, in the description of the present application, the meanings of the terms "on", "over", "above", "over", etc. should be interpreted in the broadest way, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be intermediate components or layers between the components."

[0030] For ease of description, the present application may also use spatially relative terms such as "under", "beneath", "below", "under", "upper", "lower", etc. to describe the relationship of one component to another component shown in the drawings. In addition to the orientations described in the drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways, and the spatially relative descriptions used in the present application can be interpreted accordingly.

[0031] The method proposed in the present application is applicable to the field of laser chip manufacturing on InGaAs substrates in the optical communication industry, and is a method for reducing the ohmic contact resistance of laser chips.

[0032] Figure 1 The schematic diagram of the process of reducing ohmic contact resistance proposed in one embodiment of the present application is shown. Figure 1As shown, the process method for reducing ohmic contact resistance provided in the embodiment of the present application includes the following steps:

[0033] S1, growing a diffusion barrier layer on the surface of the wafer and performing annealing to form Ga vacancies in the wafer;

[0034] S2. Photolithography is performed on the diffusion barrier layer to form a diffusion window, and conductive medium diffusion is performed to fill the Ga vacancy with the conductive medium.

[0035] In the prior art, materials such as SiO2 and SiNx are often used as diffusion barriers. The diffusion barrier is deposited on the surface of the wafer, and a window is opened in the diffusion barrier, and then the conductive medium is diffused in the diffusion window. However, the existing process often makes the resistance of the product too high, which affects the yield of the product.

[0036] Based on this, the process method proposed in the embodiment of the present application performs annealing after growing a diffusion barrier layer on the surface of the wafer, thereby forming more Ga vacancies in the wafer; after window diffusion, the conductive medium can fill more Ga vacancies, so that the ohmic contact resistance can be reduced.

[0037] Figures 2 to 4 The following is a schematic diagram showing the corresponding steps in the process for reducing ohmic contact resistance proposed in one embodiment of the present application. Figures 2 to 4 In the figure, 1 represents the wafer, 2 represents the diffusion barrier layer, and 3 represents the diffusion region. Figures 2 to 4 , the process method provided in the embodiments of the present application is introduced.

[0038] Figure 2 FIG. 1 is a schematic diagram showing a growth diffusion barrier layer according to an embodiment of the present application. Figure 2 As shown, first, a diffusion barrier layer is grown on the wafer surface.

[0039] In some embodiments, the wafer is made of InGaAs material.

[0040] In some embodiments, the diffusion barrier layer is a SiO2 film.

[0041] In an embodiment of the present application, a layer of SiO2 film can be deposited on the surface of the InGaAs wafer before opening a window. SiO2 is a loose dielectric film. The solid solubility of Ga in the SiO2 dielectric film is relatively high, and the diffusion speed in the SiO2 dielectric film is relatively fast. Therefore, through rapid high-temperature annealing, vacancy induction can be formed, allowing the Ga ions in the InGaAs to diffuse outward, leaving more Ga vacancies, thereby providing more holes. After opening a window for conductive medium diffusion, the conductive medium fills the Ga vacancies, thereby increasing the concentration of carriers, reducing the potential barrier on the semiconductor surface, and then reducing the ohmic contact resistance.

[0042] In some embodiments, the diffusion barrier layer has a thickness of 200-700 nm.

[0043] In some embodiments, the diffusion barrier layer is deposited on the wafer surface by a PECVD (plasma enhanced chemical vapor deposition) process.

[0044] Before the diffusion barrier layer is deposited on the wafer surface, the I NP material can be etched for a few seconds using pure hydrochloric acid etching solution to expose the I nGaAs material. After the wafer is flushed with water and blown dry with a nitrogen gun, it is ready to be sent to the PECVD chamber for the diffusion barrier layer deposition.

[0045] Taking the deposition of SiO2 dielectric film as an example, N2, SiH4, and N20 are filled, the chamber pressure and RF power are controlled, and the deposition time is controlled according to the required thickness of the SiO2 dielectric film.

[0046] Then, the wafer with the diffusion barrier layer deposited thereon is annealed.

[0047] In some embodiments, the annealing process is performed at a temperature of 800-1000°C.

[0048] In some embodiments, the annealing time is 1-3 minutes.

[0049] In order to form more Ga vacancies in the wafer, the wafer with the diffusion barrier layer deposited needs to be annealed. The annealing condition is rapid high-temperature annealing to allow Ga ions in InGaAs to diffuse outward based on vacancy induction, providing more Ga vacancies in the wafer.

[0050] Figure 3 FIG. 1 is a schematic diagram showing a diffusion window after forming an embodiment of the present application. Figure 3 As shown, then, the diffusion barrier layer is photolithographically processed to form a diffusion window.

[0051] The diffusion barrier layer may be spin-coated with photoresist on its surface, and then subjected to pre-baking, exposure, development, hardening, and RIE dry etching steps in sequence to remove the diffusion barrier layer in the area where diffusion is required.

[0052] The diffusion barrier layer and the wafer after photolithography are immersed in an acetone solution to remove the photoresist.

[0053] Figure 4 FIG. 1 is a schematic diagram showing a diffusion region after forming an embodiment of the present application. Figure 4 As shown, finally, conductive medium diffusion is carried out in the diffusion window.

[0054] During diffusion, closed tube diffusion, switch diffusion and other methods can be used to make the conductive medium diffuse from a high concentration diffusion source to a low concentration wafer.

[0055] Since the diffusion window has no diffusion barrier layer, conductive medium doping is formed on the wafer surface in the diffusion window portion.

[0056] In some embodiments, the conductive medium is Zn.

[0057] In some embodiments, the temperature of the diffusion is 470-550°C.

[0058] The diffusion source may be a zinc source, and in particular, a gaseous zinc source may be used for diffusion. A high temperature diffusion furnace may be used for zinc diffusion, thereby forming a Zn diffusion zone.

[0059] During diffusion, since Ga vacancies provide more holes, Zn fills Ga vacancies and increases the carrier concentration, thereby reducing the ohmic contact resistance.

[0060] A specific embodiment of the process for reducing ohmic contact resistance is given below.

[0061] Example 1

[0062] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0063] S11, depositing a SiO2 dielectric film on the surface of the InGaAs wafer by a PECVD process, wherein the thickness of the SiO2 dielectric film is 200 nm;

[0064] S12, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 800° C. and the annealing time being 3 min.

[0065] S13, performing photolithography on the SiO2 dielectric film to remove the SiO2 dielectric film in the area where diffusion is required to form a diffusion window;

[0066] S14. A gaseous zinc source is diffused in a high temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 470°C.

[0067] Example 2

[0068] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0069] S21, depositing a SiO2 dielectric film on the surface of the InGaAs wafer by a PECVD process, wherein the thickness of the SiO2 dielectric film is 700 nm;

[0070] S22, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 1000° C. and the annealing time being 1 min.

[0071] S23, performing photolithography on the SiO2 dielectric film to remove the SiO2 dielectric film in the area where diffusion is required to form a diffusion window;

[0072] S24. A gaseous zinc source is diffused in a high temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 550°C.

[0073] Example 3

[0074] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0075] S31, depositing a SiO2 dielectric film on the surface of the InGaAs wafer by a PECVD process, wherein the thickness of the SiO2 dielectric film is 200 nm;

[0076] S32, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 800° C. and the annealing time being 1 minute.

[0077] S33, performing photolithography on the SiO2 dielectric film to remove the SiO2 dielectric film in the area where diffusion is required, thereby forming a diffusion window;

[0078] S34. Use a gaseous zinc source to diffuse in a high-temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 550°C.

[0079] Example 4

[0080] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0081] S41, depositing a SiO2 dielectric film on the surface of the InGaAs wafer by a PECVD process, wherein the thickness of the SiO2 dielectric film is 700 nm;

[0082] S42, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 1000° C. and the annealing time being 3 minutes.

[0083] S43, performing photolithography on the SiO2 dielectric film to remove the SiO2 dielectric film in the area where diffusion is required, thereby forming a diffusion window;

[0084] S44. A gaseous zinc source is diffused in a high temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 470°C.

[0085] Example 5

[0086] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0087] S51, using pure hydrochloric acid etching solution to etch the I NP material for several seconds to expose the I nGaAs material, and then flushing the wafer with water and drying it with a nitrogen gun;

[0088] S52, filling N2, SiH4, and N20 into the PECVD chamber, controlling the chamber pressure and the radio frequency power, controlling the deposition time according to the required thickness of the SiO2 dielectric film, and depositing the SiO2 dielectric film on the surface of the InGaAs wafer, the thickness of the SiO2 dielectric film being 200 nm;

[0089] S53, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 1000° C. and the annealing time being 1 minute.

[0090] S54, spin-coating a photoresist on the surface of the SiO2 dielectric film, sequentially performing pre-baking, exposure, development, hardening, and RIE dry etching processes to remove the SiO2 dielectric film in the area where diffusion is required, and immersing the SiO2 dielectric film and the InGaAs wafer after photolithography in an acetone solution to remove the photoresist;

[0091] S55. Use a gaseous zinc source to perform open tube doping diffusion in a high temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 470°C.

[0092] Example 6

[0093] The process method for reducing ohmic contact resistance provided in this embodiment includes the following steps:

[0094] S61, using pure hydrochloric acid etching solution to etch the I NP material for several seconds to expose the I nGaAs material, and then flushing the wafer with water and drying it with a nitrogen gun;

[0095] S62, filling N2, SiH4, and N20 into the PECVD chamber, controlling the chamber pressure and the RF power, controlling the deposition time according to the required thickness of the SiO2 dielectric film, and depositing the SiO2 dielectric film on the surface of the InGaAs wafer, the thickness of the SiO2 dielectric film being 700 nm;

[0096] S63, annealing the InGaAs wafer with the SiO2 dielectric film deposited thereon, with the annealing temperature being 800° C. and the annealing time being 3 minutes.

[0097] S64, spin-coating a photoresist on the surface of the SiO2 dielectric film, sequentially performing pre-baking, exposure, development, hardening, and RIE dry etching processes to remove the SiO2 dielectric film in the area where diffusion is required, and immersing the SiO2 dielectric film and the InGaAs wafer after photolithography in an acetone solution to remove the photoresist;

[0098] S65. Use gaseous zinc source to perform open tube doping diffusion in a high temperature diffusion furnace to form a Zn diffusion zone. The diffusion temperature is 550°C.

[0099] In addition, an embodiment of the present application further provides a laser chip, which can be obtained by using the above-mentioned process method for reducing ohmic contact resistance.

[0100] The above is only a specific implementation of the present application. Under the above teachings of the present application, those skilled in the art can make other improvements or modifications based on the above embodiments. Those skilled in the art should understand that the above specific description is only to better explain the purpose of the present application, and the protection scope of the present application shall be based on the protection scope of the claims.

[0101] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

Claims

1. A process for reducing ohmic contact resistance, characterized in that: The following steps are involved: Growing a diffusion barrier layer on the surface of the wafer and performing annealing treatment to form Ga vacancies in the wafer; the diffusion barrier layer is a SiO2 film, and the annealing temperature is 800-1000°C; The diffusion barrier layer is subjected to photolithography to form a diffusion window, and a conductive medium is diffused so that the conductive medium fills the Ga vacancy.

2. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The wafer is made of InGaAs material.

3. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The thickness of the diffusion barrier layer is 200-700 nm.

4. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The diffusion barrier layer is deposited on the surface of the wafer by a PECVD process.

5. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The annealing treatment time is 1-3 minutes.

6. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The conductive medium is Zn.

7. The process for reducing ohmic contact resistance according to claim 1, characterized in that: The diffusion temperature is 470-550°C.

8. A laser chip obtained according to the process for reducing ohmic contact resistance according to any one of claims 1 to 7.

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