Processor lockstep system, method, device and storage medium

Abstract

The present application discloses a processor lockstep system, method, device and storage medium, and relates to the technical field of integrated circuit design. The system includes: a main core, a check core, a lockstep monitor and a lockstep coupling decoupling controller; a lockstep coupling decoupling controller is used to obtain the operation mode for the processor, and the processor includes at least two cores; when the operation mode is lockstep operation, the input of the main core is controlled to be the system bus, and the main core is controlled to output to the system bus and the lockstep monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lockstep monitor; when the operation mode is decoupled operation, the input of the main core is controlled to be the system bus and output to the system bus, and the input of the check core is controlled to be the system bus and output to the system bus, so that the main core and the check core can operate independently; the lockstep monitor is used to compare the outputs of the main core and the check core. It can support two modes of lockstep operation and decoupled independent operation at low cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a processor lockstep system, method, device and storage medium. Background Art

[0002] At present, due to functional safety requirements, the automotive electronics field will lock the central processing unit (CPU), that is, at least two cores will execute the same task and then analyze the output of the two cores to make abnormal judgments, and meet the requirements through dual-mode redundancy. However, for some customers who do not have lock-step requirements in actual use but need more computing power, the lock-step solution in the existing technology will sacrifice half of the CPU computing power and reduce data processing efficiency. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a processor lockstep system, method, device and storage medium, which can support two modes of lockstep operation and decoupled independent operation. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a processor lockstep system, including: a main core, a check core, a lockstep monitor, and a lockstep coupling and decoupling controller;

[0005] The lock-step coupling and decoupling controller is used to obtain an operation mode for a processor, wherein the processor includes at least two cores; when the operation mode is lock-step operation, the input of the main core is controlled to be a system bus, and the main core is controlled to output to the system bus and a lock-step monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lock-step monitor; when the operation mode is decoupled operation, the input of the main core is controlled to be a system bus and output to the system bus, and the input of the check core is controlled to be a system bus and output to the system bus, so that the main core and the check core operate independently;

[0006] The lockstep monitor is used to compare the outputs of the main core and the verification core.

[0007] Optionally, the lock-step coupling and decoupling controller comprises: a first multiplexer, a second multiplexer, a lock-step enable register, a power switch, a clock gating, and a virtual output unit;

[0008] The first multiplexer is used to control the input of the verification core;

[0009] The second multiplexer is used to control the output of the check core.

[0010] Optionally, the lockstep enable register is connected to the power switch and the clock gating respectively, the power switch is connected to the power supply and the lockstep monitor respectively, and the clock gating is connected to the clock and the lockstep monitor respectively;

[0011] The lockstep enable register is used to obtain the operation mode, output an enable signal when the operation mode is lockstep operation, and output a disable signal when the operation mode is decoupled operation;

[0012] The power switch is used to output power to the lock-step monitor according to the enable signal;

[0013] The clock gating is used to output a clock signal to the lockstep monitor according to the enable signal.

[0014] Optionally, the lockstep enable register is connected to the first multiplexer, a first input port of the first multiplexer is connected to an input of the main core, and an output of the first multiplexer is an input of the check core;

[0015] The lockstep enable register is used to control the first multiplexer to select its own first input port as input by outputting an enable signal when the operation mode is lockstep operation.

[0016] Optionally, the lockstep enable register is connected to the first multiplexer, the second input port of the first multiplexer is connected to the system bus, and the output of the first multiplexer is the input of the check core; the lockstep enable register is connected to the second multiplexer, the second input port of the second multiplexer is connected to the output of the check core, and the output of the second multiplexer is connected to the system bus;

[0017] The lockstep enable register is used to control the first multiplexer to select its own second input port as input through an output disable signal when the operation mode is decoupled operation, and to control the second multiplexer to select its own second input port as input through an output disable signal.

[0018] Optionally, the lock-step coupling and decoupling controller further includes a shielding unit; a first input port of the shielding unit is connected to the lock-step monitor, and a second input port of the shielding unit is connected to the lock-step enable register via a NOT gate;

[0019] The shielding unit is used for shielding the output of the lock-step monitor when the operation mode is decoupling operation.

[0020] Optionally, the lock-step monitor includes a first signal delay unit, a second signal delay unit, a first information compression unit, a second information compression unit and a lock-step comparison unit;

[0021] The first signal delay unit is used to delay the output of the main core and then input it to the first information compression unit;

[0022] The first information compression unit is used to compress the input information and output the compressed information to the lock-step comparison unit;

[0023] The second signal delay unit is used to delay the input of the main core and then input it to the verification core;

[0024] The first information compression unit is used to receive and compress the output of the verification core, and output the compressed information to the lock-step comparison unit;

[0025] The lockstep comparison unit is used to compare the outputs of the main core and the verification core.

[0026] In a second aspect, the present application discloses a processor lockstep method, comprising:

[0027] Obtaining an operating mode for a processor; the processor comprising at least two cores;

[0028] When the operation mode is lock-step operation, the input of the main core is controlled to be the system bus, and the main core is controlled to output to the system bus and the lock-step monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lock-step monitor, so as to compare the outputs of the main core and the check core by using the lock-step monitor;

[0029] When the operation mode is decoupled operation, the main core is controlled to input and output the system bus, and the check core is controlled to input and output the system bus, so that the main core and the check core operate independently.

[0030] In a third aspect, the present application discloses an electronic device, including:

[0031] Memory, used to store computer programs;

[0032] The aforementioned processor lockstep system is used to execute the aforementioned computer program to implement the aforementioned processor lockstep method.

[0033] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program implements the aforementioned processor lockstep method when executed by a processor.

[0034] In the present application, a processor lockstep system includes: a main core, a check core, a lockstep monitor and a lockstep coupling and decoupling controller; the lockstep coupling and decoupling controller is used to obtain an operating mode for a processor, and the processor includes at least two cores; when the operating mode is lockstep operation, the input of the main core is controlled to be a system bus, and the main core is controlled to output to the system bus and the lockstep monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lockstep monitor; when the operating mode is decoupled operation, the input of the main core is controlled to be a system bus and output to the system bus, and the input of the check core is controlled to be a system bus and output to the system bus, so that the main core and the check core operate independently; the lockstep monitor is used to compare the outputs of the main core and the check core.

[0035] It can be seen that by using the system bus as the input of the main core and the output of the main core to the system bus and the lockstep monitor in the lockstep operation state, and using the input of the main core as the input of the verification core and outputting the verification core to the lockstep monitor, support for lockstep operation is achieved; by using the system bus as the input of the verification core and the verification core output to the system bus when the operation mode is set to decoupled operation, support for the decoupling of the core and the verification core to run independently is achieved. A lockstep solution that supports both lockstep operation and decoupled independent operation is achieved, that is, when lockstep is not required, the verification core can be decoupled and used as an independent core to provide additional computing power; and, when lockstep is not required, only a small amount of hardware overhead is added, and additional computing power can be provided to the chip at a low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A schematic diagram of the processor lockstep system structure provided for this application;

[0038] Figure 2 A schematic diagram of a specific processor lockstep system structure provided in this application;

[0039] Figure 3 A flowchart of a processor lockstep method provided in this application;

[0040] Figure 4 A structural diagram of an electronic device provided for this application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the prior art, the central processing unit is locked in step, that is, at least two cores execute the same task and then analyze the output of the two cores to make an abnormal judgment, and the demand is met through dual-mode redundancy. However, for some customers who do not have a lock-step requirement in actual use but need more computing power, the lock-step solution in the prior art will sacrifice half of the CPU computing power and reduce data processing efficiency. In order to overcome the above technical problems, the present application proposes a processor lock-step system that can support both lock-step operation and decoupled independent operation at a low cost.

[0043] The present application embodiment discloses a processor lockstep system, see Figure 1 As shown, the system includes: a main core 11, a check core 12, a lock-step monitor 13 and a lock-step coupling and decoupling controller 14;

[0044] The lock-step coupling and decoupling controller 14 is used to obtain an operation mode for a processor, wherein the processor includes at least two cores; when the operation mode is lock-step operation, the input of the main core 11 is controlled to be the system bus, and the main core 11 is controlled to output to the system bus and the lock-step monitor 13, and the input of the check core 12 is controlled to be the input of the main core 11, and the check core 12 is controlled to output to the lock-step monitor 13; when the operation mode is decoupled operation, the input of the main core 11 is controlled to be the system bus and output to the system bus, and the input of the check core 12 is controlled to be the system bus and output to the system bus, so that the main core 11 and the check core 12 operate independently;

[0045] The lockstep monitor 13 is used to compare the outputs of the main core 11 and the check core 12 .

[0046] The main core is the computing core, with input from the system bus and output back to the system bus. In the lock-step operation mode, the output of the main core will also enter the lock-step monitor and be compared with the output of the verification core.

[0047] The lock-step coupling and decoupling controller 14 may specifically include: a first multiplexer, a second multiplexer, a lock-step enable register, a power switch, a clock gating, and a virtual output unit; wherein the first multiplexer is used to control the input of the check core; and the second multiplexer is used to control the output of the check core. The lock-step enable register is used to select whether to output an enable signal according to the operation mode selected by the user. The power switch is used to supply power to the lock-step monitor 13 when an enable signal is present, and the clock gating is used to send a clock signal to the lock-step monitor 13 when an enable signal is present. The virtual output unit is used to output a virtual value.

[0048] Among them, the lock-step enable register is respectively connected to the power switch and the clock gating, the power switch is respectively connected to the power supply and the lock-step monitor, and the clock gating is respectively connected to the clock and the lock-step monitor; the lock-step enable register is used to obtain the operation mode, and outputs an enable signal when the operation mode is lock-step operation, and outputs a disable signal when the operation mode is decoupled operation; the power switch is used to output power to the lock-step monitor according to the enable signal; the clock gating is used to output a clock signal to the lock-step monitor according to the enable signal. In other words, the power switch connects the power supply and the output of the lock-step enable register, and can realize the AND gate logic, that is, when the lock-step operation is in progress, the power supply is at a high level, and the enable signal is at a high level. At this time, the power switch is turned on, and the power supply can supply power to the lock-step monitor, otherwise it is not turned on. Similarly, the clock gating is turned on when the lock-step operation is in progress, and the clock provides a clock signal to the lock-step monitor. When the decoupled operation is in progress, the lock-step monitor cannot receive the clock signal.

[0049] The lock-step enable register is connected to the first multiplexer, the first input port of the first multiplexer is connected to the input of the main core, and the output of the first multiplexer is the input of the check core; the lock-step enable register is used to control the first multiplexer to select its first input port as input by outputting an enable signal when the operation mode is lock-step operation. The input interface of the first multiplexer controlled by the lock-step enable register is effective, and the input of the first multiplexer under lock-step operation is the input of the main core, that is, the input of the check core is the same as the input of the main core.

[0050] Among them, the lockstep enable register is connected to the second multiplexer, the first input port of the second multiplexer is connected to the virtual output unit, and the output of the second multiplexer is connected to the system bus; the lockstep enable register is used to control the second multiplexer to select its own first input port as input through an output enable signal when the operation mode is lockstep operation. It can be understood that in order to avoid interference with the system bus and not affect bus arbitration, the output of the check core to the system bus needs to be shielded. This embodiment is implemented through the second multiplexer and the virtual output unit, that is, when the lockstep operation is in progress, the second multiplexer will output the virtual output unit The dummy value (dummy) is given to the system bus instead of the actual output result of the check core.

[0051] Among them, the lockstep enable register is connected to the first multiplexer, the second input port of the first multiplexer is connected to the system bus, and the output of the first multiplexer is the input of the check core; the lockstep enable register is connected to the second multiplexer, the second input port of the second multiplexer is connected to the output of the check core, and the output of the second multiplexer is connected to the system bus; the lockstep enable register is used to control the first multiplexer to select its own second input port as input through the output disable signal when the operation mode is decoupled operation, and control the second multiplexer to select its own second input port as input through the output disable signal. That is, under decoupled operation, the processing result of the check core is fed back to the system bus through the second multiplexer.

[0052] Among them, the lock-step monitor is also used to output a warning signal when the output of the main core is inconsistent with the output of the verification core under lock-step operation. When in a decoupled state, even if the lock-step coupling decoupling controller does not power the lock-step monitor, an abnormal situation may still occur, causing the lock-step monitor to output a high level. Therefore, in this embodiment, the lock-step coupling decoupling controller also includes a shielding unit; the first input port of the shielding unit is connected to the lock-step monitor, and the second input port of the shielding unit is connected to the lock-step enable register through a NOT gate; the shielding unit is used to shield the output of the lock-step monitor when the above-mentioned operating mode is decoupled operation. That is, at this time, the signal output by the lock-step monitor will be shielded by the shielding unit to avoid the influence of unknown warnings on the functional safety monitoring of the chip.

[0053] Among them, the lock-step monitor includes a first signal delay unit, a second signal delay unit, a first information compression unit, a second information compression unit and a lock-step comparison unit; the first signal delay unit is used to delay the output of the main core and input it to the first information compression unit; the first information compression unit is used to compress the input information and output it to the lock-step comparison unit after compression; the second signal delay unit is used to delay the input of the main core and input it to the verification core; the first information compression unit is used to receive the output of the verification core and compress it, and output it to the lock-step comparison unit after compression; the lock-step comparison unit is used to compare the outputs of the main core and the verification core. It can be understood that, through the first signal delay unit and the second signal delay unit, the running time of the main core and the verification core under lock-step operation is staggered to avoid the influence of common mode failure; common mode failure refers to failure caused by the same reason. The core output is compressed through information compression units, such as ECC (Error Checking and Correcting) error correction codes, to minimize the impact of single point failures. Single point of failure (SPoF) refers to a situation in which a component or service in the system fails, causing the entire system or service to become unavailable.

[0054] As can be seen from the above, the processor lockstep system in this embodiment includes: a main core, a check core, a lockstep monitor and a lockstep coupling and decoupling controller; the lockstep coupling and decoupling controller is used to obtain an operation mode for a processor, and the processor includes at least two cores; when the operation mode is lockstep operation, the input of the main core is controlled to be a system bus, and the main core is controlled to output to the system bus and the lockstep monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lockstep monitor; when the operation mode is decoupled operation, the input of the main core is controlled to be a system bus and output to the system bus, and the input of the check core is controlled to be a system bus and output to the system bus, so that the main core and the check core operate independently; the lockstep monitor is used to compare the outputs of the main core and the check core. It can be seen that by using the system bus as the input of the main core and the output of the main core to the system bus and the lockstep monitor in the lockstep operation state, and using the input of the main core as the input of the verification core and outputting the verification core to the lockstep monitor, support for lockstep operation is achieved; by using the system bus as the input of the verification core and the verification core output to the system bus when the operation mode is set to decoupled operation, support for the decoupling of the core and the verification core to run independently is achieved. A lockstep solution that supports both lockstep operation and decoupled independent operation is achieved, that is, when lockstep is not required, the verification core can be decoupled and used as an independent core to provide additional computing power; and, when lockstep is not required, only a small amount of hardware overhead is added, and additional computing power can be provided to the chip at a low cost.

[0055] Based on the above embodiments, the present application also discloses a specific dual-core lock-step architecture that supports lock-step operation or decoupled independent operation, see Figure 2 shown.

[0056] The lockstep operation or decoupled independent operation is controlled by the lockstep couple-decouple controller. The lockstep operation or decoupled operation mode selection is loaded from the non-volatile memory (VNM) to the lockstep enable register (Lockstep Enable Register) at power-on, and remains unchanged before power-off, thereby controlling the data, clock and power supply of the checker core (Checker CPU) and the lockstep monitor (Lockstep Monitor) in the system in different modes.

[0057] When lockstep operation is selected, the main core (Main CPU), Checker CPU and Lockstep Monitor form a DCLS (dual core lock step) system. The Main CPU serves as the computing core. The power supply and clock of the Lockstep monitor are turned on by the power switch (Power Switch) and the clock gate (Clock Gate). The Checker CPU and Lockstep monitor jointly complete the lockstep monitoring of the Main CPU.

[0058] The Main CPU is a computing core, with input from the system bus and output back to the system bus. In the lockstep operation mode, the output of the Main CPU will also enter the Lockstep Monitor and be compared with the output of the Checker CPU.

[0059] The input of the Checker CPU is selected by Mux0 (the first multiplexer) and becomes the input of the MainCPU after the delay. The output enters the Lockstep monitor and is compared with the output of the Main CPU after the delay. To avoid interference with the system bus, the output of the Checker CPU to the system bus is shielded by Mux1 (the second multiplexer) and the dummy output unit (dummy CPU output), and replaced by a dummy value that does not affect bus arbitration.

[0060] The Lockstep monitor consists of three parts: a signal delay unit (Delay Buffer), an information compression unit (InformationCompressor), and a lockstep comparison unit (Mismatch detector). The Delay Buffer is a signal delay unit used to stagger the running time of the Main CPU and the Checker CPU to avoid common mode failure; the InformationCompressor is an information compression algorithm unit used to compress the CPU output to avoid the impact of single point failure as much as possible and reduce the channel width required by the Mismatch Detector to save chip area overhead; the MismatchDetector is a lockstep comparison unit that outputs an alarm signal (alarm) to the functional safety monitoring module of the chip when the output of the Main CPU and the Checker CPU loses lock.

[0061] When decoupled operation is selected, the Main CPU is a computing core, with input from the system bus and output returned to the system bus. The Checker CPU is another computing core, with input from the system bus through the selection of Mux0, and output returned to the system bus through the selection of Mux1. The Main CPU and Checker CPU are two independent computing cores, each running independently. The power supply and clock of the Lockstep monitor are turned off by the Power Switch and Clock Gate, and the output alarm signal is isolated to zero by the shielding unit (Isolation "0" cell), reducing the system power consumption and avoiding the impact of unknown alarm status on the functional safety monitoring module of the chip.

[0062] The present application embodiment discloses a processor lockstep method, see Figure 3 As shown, the method may include the following steps:

[0063] Step S11: Obtain an operating mode for a processor, wherein the processor includes at least two cores.

[0064] The above-mentioned acquisition of the operating mode for the processor includes: acquiring the operating mode for the processor through a lock-step coupling and decoupling controller; the lock-step coupling and decoupling controller includes: a first multiplexer, a second multiplexer, a lock-step enable register, a power switch, a clock gating, and a virtual output unit; the first multiplexer is used to control the input of the check core, and the second multiplexer is used to control the output of the check core.

[0065] The lockstep enable register is respectively connected to the power switch and the clock gating, the power switch is respectively connected to the power supply and the lockstep monitor, and the clock gating is respectively connected to the clock and the lockstep monitor; obtaining the operation mode for the processor, including: obtaining the operation mode through the lockstep enable register, when the operation mode is lockstep operation, the lockstep enable register outputs an enable signal, and when the operation mode is decoupled operation, the lockstep enable register outputs a disable signal; when the operation mode is lockstep operation, the power switch is used to output power to the lockstep monitor, and the clock gating is used to output a clock signal to the lockstep monitor.

[0066] Step S12: When the operation mode is lock-step operation, the input of the main core is controlled to be the system bus, and the main core is controlled to output to the system bus and the lock-step monitor, and the input of the verification core is controlled to be the input of the main core, and the verification core is controlled to output to the lock-step monitor, so as to use the lock-step monitor to compare the outputs of the main core and the verification core.

[0067] The lock-step monitor includes a first signal delay unit, a second signal delay unit, a first information compression unit, a second information compression unit and a lock-step comparison unit, including: the first signal delay unit is used to delay the output of the main core and input it to the first information compression unit; the first information compression unit is used to compress the input information and output it to the lock-step comparison unit after compression; the second signal delay unit is used to delay the input of the main core and input it to the verification core; the first information compression unit is used to receive the output of the verification core and compress it, and output it to the lock-step comparison unit after compression; using the lock-step monitor to compare the outputs of the main core and the verification core, including: using the lock-step comparison unit in the lock-step monitor to compare the outputs of the main core and the verification core.

[0068] The lockstep enable register is connected to the first multiplexer, the first input port of the first multiplexer is connected to the input of the main core, and the output of the first multiplexer is the input of the check core; when the operation mode is lockstep operation, the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lockstep monitor, including: when the operation mode is lockstep operation, the lockstep enable register controls the first multiplexer to select its own first input port as input through an output enable signal; the lockstep enable register is connected to the second multiplexer, the first input port of the second multiplexer is connected to the virtual output unit, and the output of the second multiplexer is connected to the system bus; the method also includes: when the operation mode is lockstep operation, the lockstep enable register controls the second multiplexer to select its own first input port as input through an output enable signal.

[0069] Step S13: When the operation mode is decoupled operation, the main core is controlled to input and output the system bus, and the verification core is controlled to input and output the system bus, so that the main core and the verification core operate independently.

[0070] The lockstep enable register is connected to the first multiplexer, the second input port of the first multiplexer is connected to the system bus, and the output of the first multiplexer is the input of the check core; the lockstep enable register is connected to the second multiplexer, the second input port of the second multiplexer is connected to the output of the check core, and the output of the second multiplexer is connected to the system bus;

[0071] When the operation mode is decoupled operation, the input of the control check core is the system bus and the output is to the system bus, including: when the operation mode is decoupled operation, the lockstep enable register controls the first multiplexer to select its own second input port as input through an output disable signal, and controls the second multiplexer to select its own second input port as input through an output disable signal.

[0072] The lock-step coupling and decoupling controller also includes a shielding unit; a first input port of the shielding unit is connected to the lock-step monitor, and a second input port of the shielding unit is connected to the lock-step enable register through a NOT gate; the shielding unit is used to shield the output of the lock-step monitor when the operating mode is decoupling operation.

[0073] As can be seen from the above, the processor lockstep system in this embodiment includes: a main core, a check core, a lockstep monitor and a lockstep coupling and decoupling controller; the lockstep coupling and decoupling controller is used to obtain an operation mode for a processor, and the processor includes at least two cores; when the operation mode is lockstep operation, the input of the main core is controlled to be a system bus, and the main core is controlled to output to the system bus and the lockstep monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lockstep monitor; when the operation mode is decoupled operation, the input of the main core is controlled to be a system bus and output to the system bus, and the input of the check core is controlled to be a system bus and output to the system bus, so that the main core and the check core operate independently; the lockstep monitor is used to compare the outputs of the main core and the check core. It can be seen that by using the system bus as the input of the main core and the output of the main core to the system bus and the lockstep monitor in the lockstep operation state, and using the input of the main core as the input of the verification core and outputting the verification core to the lockstep monitor, support for lockstep operation is achieved; by using the system bus as the input of the verification core and the verification core output to the system bus when the operation mode is set to decoupled operation, support for the decoupling of the core and the verification core to run independently is achieved. A lockstep solution that supports both lockstep operation and decoupled independent operation is achieved, that is, when lockstep is not required, the verification core can be decoupled and used as an independent core to provide additional computing power; and, when lockstep is not required, only a small amount of hardware overhead is added, and additional computing power can be provided to the chip at a low cost.

[0074] Furthermore, the present application also discloses an electronic device, see Figure 4 As shown, the contents in the drawings should not be considered as any limitation on the scope of use of the present application.

[0075] Figure 4The present invention is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor lockstep system 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor lockstep system 21 to implement the relevant steps in the processor lockstep method disclosed in any of the aforementioned embodiments.

[0076] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0077] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223 including an operating mode, etc. The storage method can be temporary storage or permanent storage.

[0078] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the processor lock-step method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0079] Furthermore, an embodiment of the present application also discloses a computer storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the processor lock-step method steps disclosed in any of the aforementioned embodiments are implemented.

[0080] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the system part description.

[0081] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0082] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0083] The processor lockstep system, method, device and storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A processor lockstep system, characterized in that: include: Main core, check core, lockstep monitor and lockstep coupling and decoupling controller; The lock-step coupling and decoupling controller is used to obtain an operation mode for a processor, wherein the processor includes at least two cores; when the operation mode is lock-step operation, the input of the main core is controlled to be the system bus, and the main core is controlled to output to the system bus and the lock-step monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lock-step monitor; When the operation mode is decoupled operation, controlling the input of the main core to be the system bus and output to the system bus, and controlling the input of the check core to be the system bus and output to the system bus, so that the main core and the check core operate independently; The lockstep monitor is used to compare the outputs of the main core and the verification core; Wherein, the lock-step coupling and decoupling controller comprises: a first multiplexer, a second multiplexer, a lock-step enable register, a power switch, a clock gating, and a virtual output unit; The first multiplexer is used to control the input of the verification core; The second multiplexer is used to control the output of the verification core; The lockstep enable register is connected to the second multiplexer, the first input port of the second multiplexer is connected to the virtual output unit, and the output of the second multiplexer is connected to the system bus; the lockstep enable register is used to control the second multiplexer to select its first input port as input through an output enable signal when the operation mode is lockstep operation; Wherein, the lockstep enable register is connected to the power switch and the clock gating respectively, the power switch is connected to the power supply and the lockstep monitor respectively, and the clock gating is connected to the clock and the lockstep monitor respectively; The lockstep enable register is used to obtain the operation mode, output an enable signal when the operation mode is lockstep operation, and output a disable signal when the operation mode is decoupled operation; The power switch is used to output power to the lock-step monitor according to the enable signal; The clock gating is used to output a clock signal to the lockstep monitor according to the enable signal.

2. The processor lockstep system according to claim 1, characterized in that: The lockstep enable register is connected to the first multiplexer, a first input port of the first multiplexer is connected to an input of the main core, and an output of the first multiplexer is an input of the check core; The lockstep enable register is used to control the first multiplexer to select its own first input port as input by outputting an enable signal when the operation mode is lockstep operation.

3. The processor lockstep system according to claim 1, characterized in that: The lockstep enable register is connected to the first multiplexer, the second input port of the first multiplexer is connected to the system bus, and the output of the first multiplexer is the input of the check core; the lockstep enable register is connected to the second multiplexer, the second input port of the second multiplexer is connected to the output of the check core, and the output of the second multiplexer is connected to the system bus; The lockstep enable register is used to control the first multiplexer to select its own second input port as input through an output disable signal when the operation mode is decoupled operation, and to control the second multiplexer to select its own second input port as input through an output disable signal.

4. The processor lockstep system according to claim 1, wherein: The lock-step coupling and decoupling controller further comprises a shielding unit; a first input port of the shielding unit is connected to the lock-step monitor, and a second input port of the shielding unit is connected to the lock-step enable register via a NOT gate; The shielding unit is used for shielding the output of the lock-step monitor when the operation mode is decoupling operation.

5. The processor lockstep system according to any one of claims 1 to 4, characterized in that: The lockstep monitor comprises a first signal delay unit, a second signal delay unit, a first information compression unit, a second information compression unit and a lockstep comparison unit; The first signal delay unit is used to delay the output of the main core and then input it to the first information compression unit; The first information compression unit is used to compress the input information and output the compressed information to the lock-step comparison unit; The second signal delay unit is used to delay the input of the main core and then input it to the verification core; The first information compression unit is used to receive and compress the output of the verification core, and output the compressed information to the lock-step comparison unit; The lockstep comparison unit is used to compare the outputs of the main core and the verification core.

6. A processor lockstep method, characterized in that: include: Obtaining an operating mode for a processor; the processor comprising at least two cores; When the operation mode is lock-step operation, the input of the main core is controlled to be the system bus, and the main core is controlled to output to the system bus and the lock-step monitor, and the input of the check core is controlled to be the input of the main core, and the check core is controlled to output to the lock-step monitor, so as to compare the outputs of the main core and the check core by using the lock-step monitor; When the operation mode is decoupled operation, the input of the main core is controlled to be the system bus and the output is controlled to be the system bus, and the input of the verification core is controlled to be the system bus and the output is controlled to be the system bus, so that the main core and the verification core operate independently; Wherein, the input of the check core is controlled by a first multiplexer, and the output of the check core is controlled by a second multiplexer; When the operation mode is lock-step operation, the lock-step enable register outputs an enable signal to control the second multiplexer to select its own first input port as input; the lock-step enable register is connected to the second multiplexer, the first input port of the second multiplexer is connected to the virtual output unit, and the output of the second multiplexer is connected to the system bus; When the operation mode is lock-step operation, the lock-step enable register outputs an enable signal, and when the operation mode is decoupled operation, the lock-step enable register outputs a disable signal; wherein the lock-step enable register is respectively connected to a power switch and a clock gating, the power switch is respectively connected to a power supply and the lock-step monitor, and the clock gating is respectively connected to a clock and the lock-step monitor; the power switch is used to output power to the lock-step monitor according to the enable signal; and the clock gating is used to output a clock signal to the lock-step monitor according to the enable signal.

7. An electronic device, characterized in that: include: Memory, used to store computer programs; The processor lockstep system according to any one of claims 1 to 5, configured to execute the computer program to implement the processor lockstep method according to claim 6.

8. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein when the computer program is executed by a processor, the processor lockstep method as claimed in claim 6 is implemented.

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