A failure analysis method for static random access memory
The method addresses SRAM failure analysis by identifying high-resistance failures through selective read-write tests and physical analysis, optimizing production and reducing costs by targeting analysis efforts.
Patent Information
- Application Number
- CN202411178748.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-08-27
AI Technical Summary
Existing failure analysis methods for static random access memory (SRAM) struggle to distinguish between Single Bit Soft Fail (SBSF) and high-resistance failures, hindering efficient yield improvement and requiring excessive resources.
A method involving wafer testing, selective read-write tests at varying voltages, and subsequent physical analysis to identify and locate high-resistance failures in SRAM, optimizing the production process and reducing analysis time and cost.
The method effectively screens and identifies high-resistance failures in SRAM, distinguishing between read and write failures, and accurately locates their positions, thereby enhancing yield improvement without excessive resource use.
Smart Images
Figure CN118692546B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a failure analysis method for a static random access memory. Background Art
[0002] Single Bit Soft Fail (SBSF) is one of the main failure modes of Static Random-Access Memory (SRAM), and is also the main factor affecting the yield of SRAM at low working voltage (Vmin). Through failure analysis (FA), it is found that the main causes of SBSF are as follows: high resistance failure, threshold voltage mismatch (Vt mismatch) and leakage failure, among which Vt mismatch needs to be improved through the device itself, and it is difficult to improve the yield in a short time. Other failure modes such as high resistance failure can be quickly improved through process design of experiment (DOE), so as to achieve the purpose of improving product yield in a short time.
[0003] At present, chip probing (CP) can only distinguish failure modes such as SBSF or single bit hard fail (SBHF), but cannot further distinguish the specific cause of SBSF. Therefore, when selecting SBSF for analysis, it seriously affects the progress of analyzing and improving high-resistance failures, thereby affecting the rapid improvement of yield. Summary of the invention
[0004] The purpose of the present invention is to provide a failure analysis method for a static random access memory. By providing the failure analysis method for a static random access memory, the present invention can selectively select high-resistance failed devices for failure analysis, optimize the enterprise production process, avoid repetitive work, shorten the analysis time, and reduce the enterprise production cost.
[0005] In order to solve the above technical problems, the present invention provides a failure analysis method for a static random access memory, which at least comprises:
[0006] Providing a plurality of static random access memories;
[0007] Performing wafer testing to screen out the static random access memory with unit soft failure;
[0008] Setting the starting voltage as the test voltage to perform a read-write 0 test and / or a read-write 1 test on the static random access memory with a single-bit soft failure;
[0009] Performing a read-write 0 test and / or a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a preset gradient, stopping the test when the test voltage reaches a termination voltage, and outputting the test result;
[0010] Determine whether it is a high resistance failure according to the test result; and
[0011] Failure analysis is performed on the static random access memory with high resistance failure.
[0012] In one embodiment of the present invention, the analysis method further comprises:
[0013] Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure;
[0014] Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result;
[0015] If all the first test results are passed, setting the second starting voltage as the test voltage to perform a read-write 1 test on the static random access memory with a single-bit soft failure;
[0016] Performing a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a second preset gradient, stopping the test when the test voltage reaches a second termination voltage, and outputting a second test result; and
[0017] According to the second test result, determine whether it is a high resistance failure.
[0018] In one embodiment of the present invention, the analysis method further comprises:
[0019] Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure;
[0020] Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result; and
[0021] If the first test results do not all pass, determine whether it is a high-resistance failure based on the first test results.
[0022] In one embodiment of the present invention, the analysis method further comprises:
[0023] Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure;
[0024] Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result;
[0025] Setting the second starting voltage as a test voltage to perform a read-write 1 test on the static random access memory with a unit soft failure;
[0026] Performing a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a second preset gradient, stopping the test when the test voltage reaches a second termination voltage, and outputting a second test result; and
[0027] Whether it is a high-resistance failure is determined according to the first test result and the second test result.
[0028] In one embodiment of the present invention, the first starting voltage is equal to the second starting voltage, and / or the first preset gradient is equal to the second preset gradient, and / or the first termination voltage is equal to the second termination voltage.
[0029] In one embodiment of the present invention, the first starting voltage and the second starting voltage are respectively 50% to 70% of the operating voltage of the static random access memory.
[0030] In an embodiment of the present invention, the first preset gradient and the second preset gradient are respectively 5% to 15% of the operating voltage of the static random access memory.
[0031] In one embodiment of the present invention, the first termination voltage and the second termination voltage are respectively 140% to 160% of the operating voltage of the static random access memory.
[0032] In an embodiment of the present invention, in the test result, the SRAM with a unit soft failure that fails the test at a voltage greater than the operating voltage is a high-resistance failure.
[0033] In one embodiment of the present invention, physical failure analysis, nanoprobe measurement and transmission electron microscopy test are performed on the high-resistance failed static random access memory.
[0034] In summary, the present invention provides a failure analysis method for static random access memory. The unexpected technical effect of the present application is that it can screen out static random access memory with high resistance failure in unit soft failure after wafer testing, can distinguish high resistance failure as write failure or read failure, can accurately locate the position of high resistance failure in the static random access memory with unit soft failure, and conduct failure analysis in a targeted manner. Devices with high resistance failure can be selected for failure analysis in a targeted manner, and can be analyzed in a targeted manner to quickly improve product yield. It does not require a large amount of manpower and material resources to test and screen and analyze devices with high resistance failure, which can optimize the production process of the enterprise, avoid repetitive work, shorten analysis time, and reduce the production cost of the enterprise.
[0035] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0037] Figure 1 The figure is a flow chart of a failure analysis method of a static random access memory according to an embodiment of the present invention.
[0038] Figure 2 FIG. 4 is a schematic diagram of a power management structure of a static random access memory according to an embodiment of the present invention.
[0039] Figure 3 The figure is a flow chart of a failure analysis method of a static random access memory according to another embodiment of the present invention.
[0040] Figure 4 FIG. 2 is a second test result of a static random access memory with a single-bit soft fail according to an embodiment of the present invention.
[0041] Figure 5 It is a first test result of a static random access memory with a single-bit soft fail in another embodiment of the present invention.
[0042] Figure 6 FIG. 4 is a second test result of a static random access memory with a single-bit soft fail according to another embodiment of the present invention.
[0043] Figure 7 This is a flow chart of failure analysis of an example and a comparative example in one embodiment of the present invention.
[0044] Figure 8This is a time distribution diagram of high resistance failure analysis performed on an example and a comparative example in one embodiment of the present invention. DETAILED DESCRIPTION
[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. In addition, the terms "first" and "second" are only used for description and distinction purposes and cannot be understood as indicating or implying relative importance.
[0047] The present invention provides a failure analysis method for static random access memory. After the static random access memory with unit soft failure is screened out by wafer testing, the static random access memory with high resistance failure in the unit soft failure can be screened out, and the failure analysis can be performed more targetedly, the product yield can be quickly improved, and the product development cycle can be shortened. In addition, the analysis method provided by the present application is simple, easy to operate, and will not increase the production cost of the enterprise.
[0048] See also Figure 1 As shown, in one embodiment of the present invention, a failure analysis method for a static random access memory provided by the present invention includes steps S11-S18.
[0049] Step S11, providing a plurality of static random access memories.
[0050] Step S12: perform wafer testing to screen out SRAMs with unit soft failures.
[0051] Step S13, setting the first starting voltage as the test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure.
[0052] Step S14, performing a read-write 0 test on the static random access memory with a single-bit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result.
[0053] Step S151, determine whether all first test results are passed.
[0054] Step S152: If all the first test results are passed, set the second starting voltage as the test voltage to perform a read-write 1 test on the SRAM with a single-bit soft failure.
[0055] Step S16, performing a read-write 1 test on the static random access memory with a single-bit soft failure by increasing the test voltage with a second preset gradient, stopping the test when the test voltage reaches a second termination voltage, and outputting a second test result.
[0056] Step S17: Determine whether it is a high resistance failure according to the first test result or the second test result.
[0057] Step S18: performing failure analysis on the high-resistance failed static random access memory.
[0058] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in steps S11-S12, after the front-end process is completed, multiple static random access memories are distributed on the wafer. Wafer testing is performed to screen out the static random access memories with unit soft failures on the wafer, and locate the positions of the static random access memories with unit soft failures.
[0059] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a power management structure of SRAM is provided, including peripheral circuit power supply VDDP1, word line power supply VDDP2, logic circuit power supply VDDP3, interface power supply VDDP4 and array power supply VDDC, etc. When performing wafer testing, the above power supplies are set to high level.
[0060] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after step S12, the static random access memory with unit soft failure is screened out, and then steps S13 and S14 are performed, and the static random access memory with unit soft failure is subjected to a read-write 0 (Scan0) test with the set first starting voltage as the test voltage. The first starting voltage is, for example, 50% to 70% of the working voltage of the static random access memory, and is also, for example, 60%. When performing the read-write 0 test, the peripheral circuit power supply VDDP1, the word line power supply VDDP2, the logic circuit power supply VDDP3, the interface power supply VDDP4, and the array power supply VDDC are set to a high level. After the first Scan0 test is performed, the test voltage is increased with a first preset gradient and the read-write 0 test is performed again on the static random access memory with unit soft failure, until the test voltage reaches the first termination voltage, the test is stopped, and the first test result is output. The first preset gradient is, for example, 5% to 15% of the working voltage of the static random access memory, the first termination voltage is, for example, 140% to 160% of the working voltage of the static random access memory, and the first test result of the read-write 0 test of the static random access memory with unit soft failure under different working voltages is output. In the test result, when both the read and write of the static random access memory pass the test, it is recorded as Pass, and when at least one of the read and write of the static random access memory fails the test, it is recorded as Fail.
[0061] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after performing a read-write 0 test on a static random access memory with a single soft failure at different test voltages, step S151 is performed to determine whether all the first test results are passed. If all the first test results are passed, steps S152 and S16 are performed to perform a read-write 1 (Scan1) test on the static random access memory with a single soft failure with a set second starting voltage as the test voltage. The second starting voltage is, for example, 50% to 70% of the working voltage of the static random access memory, and another example is 60%. When performing the read-write 1 test, the peripheral circuit power supply VDDP1, the word line power supply VDDP2, the logic circuit power supply VDDP3, the interface power supply VDDP4, and the array power supply VDDC are set to a high level. After performing the first Scan1 test, the test voltage is increased by a second preset gradient to perform a read-write 1 test on the static random access memory with a single soft failure again, until the test voltage reaches the second termination voltage, the test is stopped, and the second test result is output. Among them, the second preset gradient is, for example, 5%~15% of the working voltage of the static random access memory, the second termination voltage is, for example, 140%~160% of the working voltage of the static random access memory, and the second test result of the read-write 1 test of the static random access memory with unit soft failure under different working voltages is output.
[0062] See also Figure 1 As shown, in one embodiment of the present invention, if the first test result is not all passed, step S17 can be directly performed, and the first test result is analyzed to determine whether the static random access memory with a unit soft failure is a high-resistance failure. If the first test result is all passed, after the second test result is obtained in steps S152-S16, step S17 is performed, and the second test result is analyzed to determine whether the static random access memory with a unit soft failure is a high-resistance failure. Among them, the specific failure cause of the static random access memory with a unit soft failure is determined by analyzing the test results of the static random access memory with a unit soft failure at different voltages. Since some locations where high-resistance failures occur will only fail under the read-write 0 test or the read-write 1 test, the read-write 0 test and the read-write 1 test are performed to locate the location of the high-resistance failure, but different types of high-resistance failures will fail under the read-write 0 test or the read-write 1 test. For example, when the driving transistor has high resistance, it can only be reflected under the read-write 0 test. Therefore, the static random access memory with a unit soft failure is sequentially subjected to the read-write 0 test or the read-write 0 test and the read-write 1 test. In other embodiments, a read-write 1 test may be performed on the SRAM with a single-bit soft failure first, and then a determination may be made whether to perform a read-write 0 test based on the result of the read-write 1 test.
[0063] See also Figure 3 As shown, in another embodiment of the present invention, steps S11-S14 are the same as the steps of the previous embodiment. After obtaining the first test result, steps S15-S16 are directly performed, and the second starting voltage is directly set as the test voltage to perform a read-write 1 test on the semiconductor device with a single soft failure. After obtaining the second test result, it is determined whether it is a high-resistance failure based on the first test result and the second test result. In this embodiment, after obtaining the first test result, the first test result is not judged, and a read-write 1 test is directly performed, that is, in this embodiment, a static random access memory with a single soft failure performs a read-write 0 test and a read-write 1 test, and the two test results are combined to determine whether it is a high-resistance failure, and a high-resistance failure is confirmed twice, thereby improving the accuracy of judging a high-resistance failure.
[0064] See also Figure 1 and Figure 3 As shown, in one embodiment of the present invention, when performing a read-write 0 test and a read-write 1 test on a static random access memory with a single-bit soft failure, the first starting voltage is, for example, equal to the second starting voltage, the first preset gradient is, for example, equal to the second preset gradient, and the first termination voltage is, for example, equal to the second termination voltage. In other embodiments, the starting voltage, preset gradient or termination voltage in the read-write 0 test and the read-write 1 test are, for example, not equal.
[0065] See also Figure 1 and Figures 4 to 6As shown, in one embodiment of the present invention, the operating voltage of the static random access memory with a single soft failure is, for example, 1.1V, the first starting voltage for the read-write 0 test and the read-write 1 test is, for example, equal to the second starting voltage, for example, 60% of the operating voltage, the first preset gradient is, for example, equal to the second preset gradient, for example, 10% of the operating voltage, and the first termination voltage is, for example, equal to the second termination voltage, for example, 140% of the operating voltage. That is, the static random access memory with a single soft failure is tested under the same test conditions to perform the read-write 0 test and the read-write 1 test to improve the comparability of the test results.
[0066] See also Figure 1 and Figure 4 As shown, in one embodiment of the present invention, Figure 4 The second test result of the read-write 1 test for a static random access memory with a unit soft failure, at this time, the read-write 0 test of the static random access memory passed the test at different test voltages, and the first test result is not listed here. When the static random access memory with a unit soft failure passes the read-write 0 test, but in the read-write 1 test result, when the test voltage is less than or equal to the operating voltage, the static random access memory fails the test, and when the test voltage is greater than the operating voltage, the static random access memory passes the test. Combined with the first test result and the second test result, it is consistent with the read-write result that the device fails the test at low voltage due to the threshold voltage mismatch, so it can be judged that the failure type of the static random access memory with a unit soft failure is the threshold voltage mismatch, and the failure type of the static random access memory is write failure. When performing high-resistance failure analysis, the static random access memory is not selected for analysis.
[0067] See also Figure 1 and Figure 5 As shown, in one embodiment of the present invention, Figure 5 The first test result of the read-write 0 test for a static random access memory with a unit soft failure. In the present embodiment, in the first test result, in the read-write 0 test result, when the test voltage is less than or equal to the operating voltage, the static random access memory passes the test, and when the test voltage is greater than the operating voltage, the static random access memory fails the test. The read-write result that meets the high-resistance failure causes the device to fail the read-write test at a high voltage, so it can be determined that the failure type of the static random access memory with a unit soft failure is a high-resistance failure, and the static random access memory with a high-resistance failure is a write failure. In the present embodiment, when the first test result of the read-write 0 test can analyze the failure type of the static random access memory, the read-write 1 test can be omitted, which can simplify the test process and speed up the test.
[0068] See also Figure 1 and Figure 6As shown, in one embodiment of the present invention, Figure 6 The second test result of the read-write 1 test for a static random access memory with a unit soft failure, at this time, the read-write 0 test of the static random access memory passed the test at different test voltages, and the first test result is not listed here. When the static random access memory with a unit soft failure passes the read-write 1 test, but in the read-write 1 test result, when the test voltage is less than or equal to 110% of the operating voltage, the static random access memory passes the test, and when the test voltage is greater than 110% of the operating voltage, the static random access memory fails the test, that is, the read-write 1 test result fails at a high voltage. Combined with the first test result and the second test result, it is consistent with the read-write result of the device failing to pass the read and write test at a high voltage due to a high-resistance failure, so it can be determined that the failure type of the static random access memory with a unit soft failure is a high-resistance failure, and the static random access memory with a high-resistance failure is a read failure. That is, through the analysis method of the present application, on the one hand, it is possible to screen out the SRAM with a unit soft failure as a device with a high resistance failure, and on the other hand, it is possible to distinguish whether the high resistance failure is a write failure or a read failure, and the position of the high resistance failure in the SRAM with the unit soft failure can be accurately located, so that the FA analysis can be performed more targeted. In one embodiment of the present invention, for example, when the high resistance failure is a read failure, the focus of the FA analysis is on the driving transistor and the transmission transistor, which can provide a direction for the subsequent FA analysis.
[0069] See also Figures 1 to 7 As shown, in one embodiment of the present invention, after the high-resistance failed static random access memory is screened out, step S18 is performed to perform failure analysis on the high-resistance failed static random access memory. In the present application, for example, physical failure analysis (PFA), nano probe measurement (Nano Probe) and transmission electron microscope test (TEM) are performed on the high-resistance failed static random access memory in sequence to determine the cause of the high-resistance failure, which is used to improve the manufacturing process of the static random access memory and can quickly improve the product yield in a short time.
[0070] See also Figure 7As shown, in one embodiment of the present invention, an embodiment is provided. After forming a wafer test, the method provided by the present application is used to screen out high-resistance failure devices. When selecting failed samples, the static random access memory with high-resistance failure is directly selected for failure analysis to determine the cause of the high-resistance failure. The analysis method provided by the present application is compatible with the CP test process. It only needs to add some test content for the device with unit soft failure, and the coordinates of the high-resistance failure can be directly located. That is, after the wafer test, the static random access memory with unit soft failure is read and written. The coordinates of the device with high-resistance failure can be accurately screened and located. When selecting failed samples, the device with high-resistance failure can be selected in a targeted manner, and then FA analysis can be performed. The analysis can be performed in a targeted manner to avoid repetitive work, save time and cost, and quickly improve product yield.
[0071] See also Figure 7 As shown, in one embodiment of the present invention, a pair of ratios is provided. After wafer testing, a static random access memory with a unit soft failure is directly selected for failure analysis. The device needs to be subjected to physical failure analysis, nanoprobe measurement, and transmission electron microscopy test in sequence to determine whether it is a high-resistance failure. If the failed device is a high-resistance failure, the case is closed. If the failed device is not a high-resistance failure, it is necessary to re-select the failed sample, re-perform physical failure analysis, nanoprobe measurement, and transmission electron microscopy test, etc., to re-determine whether it is a high-resistance failure. In one embodiment of the present invention, in the static random access memory with a unit soft failure, high-resistance failure accounts for about 40%, threshold voltage mismatch accounts for about 40%, and leakage failure accounts for about 20%. Therefore, directly selecting a static random access memory with a unit soft failure for failure analysis has a lower probability of selecting a device with a high-resistance failure, and the failure analysis takes a longer time.
[0072] See also Figures 7 and 8 As shown, in an embodiment, when the analysis method provided by the present application is used to perform failure analysis on a static random access memory with a high resistance failure and a unit soft failure, the time required for FA analysis is, for example, about 14 days. In the comparative example, after the wafer test, the static random access memory with a unit soft failure is directly selected for failure analysis, and the time required to complete the FA analysis of the static random access memory with a high resistance failure is, for example, about 32 days. That is, the analysis method provided by the present application can shorten the time required for FA analysis by more than half, and does not require a large amount of manpower and material resources to test and screen and analyze devices with high resistance failures, which can optimize the production process of the enterprise and reduce the production cost of the enterprise.
[0073] In summary, the present invention provides a failure analysis method for static random access memory, by performing high resistance failure judgment after wafer testing, the unexpected technical effect of the present application is that it can screen out static random access memory with high resistance failure in unit soft failure after wafer testing, can distinguish high resistance failure as write failure or read failure, can accurately locate the position of high resistance failure in the static random access memory with unit soft failure, and perform failure analysis in a targeted manner. Devices with high resistance failure can be selected for failure analysis in a targeted manner, and can be analyzed in a targeted manner to quickly improve product yield. It does not require a large amount of manpower and material resources to test and screen and analyze devices with high resistance failure, which can optimize the production process of the enterprise, avoid repetitive work, shorten analysis time, and reduce the production cost of the enterprise.
[0074] References throughout the specification to "one embodiment," "an embodiment," or "a specific embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, and not necessarily in all embodiments. Thus, various appearances of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout the specification do not necessarily refer to the same embodiment. In addition, the particular features, structures, or characteristics of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein may be possible in light of the teachings herein and are to be considered part of the spirit and scope of the invention.
[0075] It should also be understood that the embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A failure analysis method for static random access memory, characterized in that: At least: Providing a plurality of static random access memories; Performing wafer testing to screen out the static random access memory with unit soft failure; Setting a starting voltage as a test voltage to perform a read-write 0 test and / or a read-write 1 test on the static random access memory with a unit soft failure; the starting voltage is less than an operating voltage of the static random access memory; Performing a read-write 0 test and / or a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a preset gradient, stopping the test when the test voltage reaches a termination voltage, and outputting the test result; The termination voltage is greater than the operating voltage of the static random access memory; According to the test result, determining whether it is a high-resistance failure, wherein in the test result, when the test voltage is greater than the working voltage, the static random access memory that fails the test and has a unit soft failure is a high-resistance failure; as well as Failure analysis is performed on the static random access memory with high resistance failure.
2. The failure analysis method of static random access memory according to claim 1, characterized in that: The analysis method further comprises: Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure; Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result; If all the first test results are passed, setting the second starting voltage as the test voltage to perform a read-write 1 test on the static random access memory with a single-bit soft failure; Performing a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a second preset gradient, stopping the test when the test voltage reaches a second termination voltage, and outputting a second test result; and According to the second test result, determine whether it is a high resistance failure.
3. The failure analysis method of static random access memory according to claim 1, characterized in that: The analysis method further comprises: Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure; Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result; and If the first test results do not all pass, determine whether it is a high-resistance failure based on the first test results.
4. The failure analysis method of static random access memory according to claim 1, characterized in that: The analysis method further comprises: Setting a first starting voltage as a test voltage to perform a read-write 0 test on the static random access memory with a single-bit soft failure; Performing a read-write 0 test on the static random access memory with a unit soft failure by increasing the test voltage with a first preset gradient, stopping the test when the test voltage reaches a first termination voltage, and outputting a first test result; Setting the second starting voltage as a test voltage to perform a read-write 1 test on the static random access memory with a unit soft failure; Performing a read-write 1 test on the static random access memory with a unit soft failure by increasing the test voltage with a second preset gradient, stopping the test when the test voltage reaches a second termination voltage, and outputting a second test result; and Whether it is a high-resistance failure is determined according to the first test result and the second test result.
5. The failure analysis method of static random access memory according to claim 2 or 4, characterized in that: The first starting voltage is equal to the second starting voltage, and / or the first preset gradient is equal to the second preset gradient, and / or the first ending voltage is equal to the second ending voltage.
6. The failure analysis method of static random access memory according to claim 2 or 4, characterized in that: The first starting voltage and the second starting voltage are respectively 50% to 70% of the operating voltage of the static random access memory.
7. The failure analysis method of static random access memory according to claim 2 or 4, characterized in that: The first preset gradient and the second preset gradient are respectively 5% to 15% of the operating voltage of the static random access memory.
8. The failure analysis method of static random access memory according to claim 2 or 4, characterized in that: The first termination voltage and the second termination voltage are respectively 140% to 160% of the operating voltage of the static random access memory.
9. The failure analysis method of static random access memory according to claim 1, characterized in that: Physical failure analysis, nanoprobe measurement and transmission electron microscope test are performed on the static random access memory with high resistance failure.