Data processing method and device, equipment and storage medium

Abstract

The invention discloses a data processing method and device, equipment and a storage medium. When the method provided by the embodiment of the invention is executed, firstly, each time domain signal to be stored is acquired one by one according to a signal input sequence, a time domain sequence number is set for each signal, then a plurality of splitting sequence numbers are set for each signal, a storage position is determined according to a calculation formula, and the signals and the corresponding time domain sequence numbers are stored in a multi-path parallel SRAM in an associated manner. And finally, performing in-situ storage on a butterfly operation result to an SRAM (Static Random Access Memory) according to the serial number of the associative storage. According to the method, the storage position is accurately calculated, and the result is stored in situ, so that an additional cache SRAM (Static Random Access Memory) is prevented from being used, and the occupation of hardware resources is reduced. And meanwhile, an in-situ storage strategy is adopted, so that the carrying of data from one SRAM to another SRAM is reduced, the requirements of data movement and copying are further reduced, the storage efficiency is improved, and the extra data transmission overhead is avoided.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data processing method, device, equipment and storage medium. Background Art

[0002] In actual parallel static random access memory (SRAM) applications, when the common radix-4-based Fast Fourier Transform (FFT) algorithm is used to save the data address and a simple serial-to-parallel conversion is used to achieve 8-way parallelism, a conflict may occur when the butterfly operation reads the SRAM. In this case, the same SRAM is read twice or even multiple times in one clock cycle, resulting in a conflict in reading the SRAM (that is, there is no conflict in the address of the FFT calculation), which leads to errors in the FFT calculation results.

[0003] In order to solve the problem of parallel reading of SRAM address conflicts, the related technology introduces an additional cache SRAM based on the original SRAM. The cache SRAM is used to store the results of each level of butterfly operation, thereby avoiding SRAM reading conflicts. Specifically, the first-level butterfly operation reads data from the original SRAM and then stores the results in the cache SRAM; then, the second-level butterfly operation reads data from the cache SRAM and stores the results in the original SRAM. It is worth noting that the read and write addresses are different, and the write address of each level satisfies the next level of read operation without conflict. In this way, the problem of SRAM reading conflicts is successfully avoided. However, this method adopts the logic of non-in-situ storage. By alternating the use of two sets of SRAM, the address conflict-free processing of FFT calculation is achieved, but it also increases the resource occupation.

[0004] Therefore, how to complete the correct FFT calculation process without increasing resource usage and using in-situ storage is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on the above problems, the present application provides a data processing method, device, equipment and storage medium, which can complete the correct FFT calculation process without increasing resource usage and using in-situ storage.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] A method for processing data, the method comprising:

[0008] Collect each time domain signal to be stored one by one according to the signal input sequence, and set a time domain sequence number for each time domain signal to be stored according to the signal input sequence;

[0009] Setting multiple split sequence numbers for the time domain signal to be stored;

[0010] Based on the plurality of split sequence numbers and storage position calculation formulas, calculating the storage position of the time domain signal to be stored in the multi-channel parallel static random access memory SRAM;

[0011] The time domain signal to be stored and the time domain serial number corresponding to the signal are stored in a corresponding storage position in the multi-channel parallel SRAM;

[0012] A butterfly operation is performed on the time domain signal to be stored in the multi-channel parallel SRAM, and the butterfly operation result is stored in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

[0013] In a possible implementation, setting a plurality of split sequence numbers for each time domain signal to be stored includes:

[0014] Setting a data index of the time domain signal to be stored;

[0015] Splitting the data index to obtain multiple split indexes;

[0016] The splitting sequence number of each splitting index is calculated based on the frequency domain sequence number corresponding to the time domain signal to be stored.

[0017] In a possible implementation manner, splitting the data index to obtain a plurality of split indexes includes:

[0018] Determine the decomposition factors in the Fast Fourier Transform;

[0019] Determine the number of segments into which the data index is to be split based on the decomposition factor in the fast Fourier transform;

[0020] The data index is evenly split based on the number of split segments to obtain a plurality of split indexes of equal length.

[0021] In a possible implementation manner, the calculating the splitting sequence number of each splitting index based on the frequency domain sequence number corresponding to the time domain signal to be stored includes:

[0022] Calculating the frequency domain sequence number corresponding to the time domain signal to be stored;

[0023] Determine, based on the valid bits specified in the split index, a split sequence number binary representation of each split index in the frequency domain sequence number;

[0024] Convert the split sequence number binary representation to decimal.

[0025] In a possible implementation, the storage location calculation formula includes: a storage number calculation formula and a write address calculation formula;

[0026] The memory number calculation formula is used to determine the target memory of the time domain signal to be stored in the multi-channel parallel SRAM; the write address calculation formula is used to determine the specific address of the time domain signal to be stored in the target memory;

[0027] The memory number calculation formula is:

[0028] sram_num=mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4;

[0029] The calculation formula for the write address is:

[0030] wr_addr=floor((64*n4+16*n3+4*n2+n1) / 2);

[0031] Among them, n1, n2, n3, n4 and n5 are the split sequence numbers.

[0032] In a possible implementation, the performing a butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM, and storing the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored, includes:

[0033] Determine a decomposition factor in a fast Fourier transform, and determine a butterfly operation series based on the decomposition factor in the fast Fourier transform;

[0034] Determine the signal reading position based on the butterfly operation position determination formula and the split sequence number;

[0035] Based on the signal reading position, reading the time domain signal to be stored stored in the multi-channel parallel SRAM;

[0036] Based on the number of read bits, a plurality of butterfly computing units are used to simultaneously perform butterfly operations on the read time domain signal to be stored to obtain an operation signal; the operation signal has a one-to-one correspondence with a time domain sequence number corresponding to the time domain signal to be stored used when calculating the operation signal;

[0037] The operation signal and its corresponding time domain serial number are stored in the multi-channel parallel SRAM in situ;

[0038] For the multi-channel parallel SRAM storing the new operation signal, the steps of determining the signal reading position, signal reading, butterfly operation and in-situ storage are repeatedly performed until the number of repetitions reaches the number of butterfly operation stages.

[0039] A data processing device, comprising: a data multiplexer MUX, a butterfly operation unit and a multi-channel parallel SRAM;

[0040] The MUX is connected to the multi-channel parallel SRAM; the MUX is also connected to the butterfly operation unit;

[0041] The MUX is used to collect each time domain signal to be stored one by one according to the signal input sequence, and set a time domain sequence number for each time domain signal to be stored according to the signal input sequence;

[0042] The MUX is further used to set a plurality of split sequence numbers for the time domain signal to be stored;

[0043] The MUX is further used to calculate the storage position of the time domain signal to be stored in the multi-channel parallel SRAM based on the multiple split sequence numbers and storage position calculation formulas;

[0044] The MUX is further used to associate and store the time domain signal to be stored and the time domain sequence number corresponding to the signal in a corresponding storage position in the multi-channel parallel SRAM;

[0045] The butterfly operation unit is used to perform butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM;

[0046] The MUX is further configured to store the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

[0047] In a possible implementation, the MUX is specifically used for:

[0048] Setting the data index of the time domain signal to be stored;

[0049] Splitting the data index to obtain multiple split indexes;

[0050] The splitting sequence number of each splitting index is calculated based on the frequency domain sequence number corresponding to the time domain signal to be stored.

[0051] A data processing device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the data processing method as described above is implemented.

[0052] A computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device executes the data processing method as described above.

[0053] Compared with the prior art, this application has the following beneficial effects:

[0054] The present application provides a data processing method, device, equipment and storage medium. Specifically, when executing the data processing method provided in the embodiment of the present application, each time domain signal to be stored can be collected one by one according to the signal input order, and a time domain sequence number can be set for each time domain signal to be stored according to the signal input order. Then, multiple split sequence numbers are set for the time domain signal to be stored, and based on the multiple split sequence numbers and the storage position calculation formula, the storage position of the time domain signal to be stored in the multi-channel parallel SRAM is calculated. Then the time domain signal to be stored and the time domain sequence number corresponding to the signal are associated and stored in the corresponding storage position in the multi-channel parallel SRAM. Then the time domain signal to be stored stored in the multi-channel parallel SRAM is subjected to a butterfly operation, and the butterfly operation result is stored in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

[0055] The present application collects the time domain signals to be stored in the order of signal input, and sets the time domain sequence number for each time domain signal in the order of signal input, and then sets the split sequence number for the time domain signal, so as to calculate the storage position based on these sequence numbers, and can effectively store the data in a multi-channel parallel SRAM. The present application makes reasonable use of storage resources and does not require additional SRAM, thereby reducing the occupation of hardware resources. At the same time, the present application can avoid the address conflict problem generated when reading SRAM in parallel by setting the time domain sequence number, the split sequence number and calculating the correct storage position. It ensures that each time domain signal can be correctly read and written to the corresponding position during the butterfly operation process, eliminating the erroneous calculation results that may be caused by the read conflict. In addition, after performing the butterfly operation on the time domain signal to be processed stored in the multi-channel parallel SRAM, the butterfly operation result is directly stored in situ back to the multi-channel parallel SRAM according to the time domain sequence number associated with the signal. This method reduces the need for data movement and copying, improves storage efficiency, and avoids additional data transmission overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 A method flow chart of a data processing method provided in an embodiment of the present application;

[0058] Figure 2 A method flow chart of a method for setting a split sequence number provided in an embodiment of the present application;

[0059] Figure 3 A method flow chart of another data processing method provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will be described below.

[0062] The radix-4-FFT algorithm is a specific algorithm for performing FFT on a sequence of length 4. In this case, the number of data points is 4, so the radix-4-FFT algorithm can be used to efficiently calculate the Fourier transform of a sequence of this length.

[0063] In actual parallel SRAM applications, when reading SRAM through butterfly operation using the Radix 4-FFT algorithm, read conflicts occur, which means that data needs to be read from the same SRAM at the same time. In this case, since most SRAMs only allow one read operation (or one read and one write operation) at the same time, multiple requests cannot be satisfied at the same time, thus causing conflicts.

[0064] For example, suppose there are 8 parallel SRAMs, the storage logic of the first 64 data in these 8 rows of SRAMs is shown in Table 1, and each SRAM needs to read 4 data points in one clock cycle. If these data points are stored in the same SRAM, there will be multiple read requests in one clock cycle, resulting in conflicts. For example, in the first butterfly operation unit of the second level, the sequence numbers of the four required data are 0, 4, 8, and 12 respectively. According to the address mapping table you provided, the data with sequence number 0 is stored in SRAM0; the data with sequence number 4 is stored in SRAM1; the data with sequence number 8 is stored in SRAM0; and the data with sequence number 12 is stored in SRAM1. In this case, in one clock cycle, the data with sequence numbers 0 and 8 need to be read from SRAM0 at the same time, and the data with sequence numbers 4 and 12 need to be read from SRAM1 at the same time. However, usually, each SRAM can only process one valid read operation in one clock cycle, so this will cause a read conflict.

[0065] Table 1 Storage logic table of the first 64 data in SRAM

[0066] address 0 1 2 3 4 5 6 7 SRAM0 0 8 16 24 32 40 48 56 SRAM1 1 9 17 25 33 41 49 57 SRAM2 2 10 18 26 34 42 50 58 SRAM3 3 11 19 27 35 43 51 59 SRAM4 4 12 20 28 36 44 52 60 SRAM5 5 13 21 29 37 45 53 61 SRAM6 6 14 22 30 38 46 54 62 SRAM7 7 15 23 31 39 47 55 63

[0067] In order to solve the problem of parallel reading of SRAM address conflicts, the related technology introduces an additional cache SRAM. The cache SRAM is used to store the results of each level of butterfly operation to avoid conflicts in reading SRAM. The specific operation is that the first level butterfly operation reads data from the original SRAM and stores the results in the cache SRAM; then the second level butterfly operation reads data from the cache SRAM and stores the results back to the original SRAM. By ensuring that the write address of each level is different from the read address of the next level, the problem of SRAM read conflicts is successfully avoided.

[0068] Although this method solves the address conflict problem, it uses non-in-situ storage logic. By using two sets of SRAM alternately, the address conflict-free processing of FFT calculation is achieved, but it also increases the resource usage.

[0069] In order to solve this problem, a data processing method, device, equipment and storage medium are provided in the embodiment of the present application. First, each time domain signal to be stored is collected one by one according to the signal input order, and a time domain sequence number is set for each signal to be stored, so as to ensure the orderly processing of the data. Then, multiple split sequence numbers are set for each time domain signal, and the storage position of each signal in the multi-channel parallel SRAM is calculated using these sequence numbers and storage position calculation formulas. Subsequently, each time domain signal to be stored is associated with its corresponding time domain sequence number and saved in the corresponding storage position in the multi-channel parallel SRAM. On this basis, a butterfly operation is performed on the time domain signal stored in the multi-channel parallel SRAM, and then the butterfly operation result is directly stored back in the multi-channel parallel SRAM according to the time domain sequence number related to the original signal, realizing an end-to-end data processing flow from storage to calculation and then to storage. The present application avoids the use of additional cache SRAM by accurately calculating the storage position and storing the result in situ, thereby reducing the occupation of hardware resources. At the same time, the in-situ storage strategy is adopted to reduce the movement of data from one SRAM to another, thereby reducing the need for data movement and copying, improving storage efficiency, and avoiding additional data transmission overhead.

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] See also Figure 1 , which is a flow chart of a method for processing data provided by an embodiment of the present application, such as Figure 1 As shown, the data processing method may include steps S101-S105:

[0072] S101: collecting each time domain signal to be stored one by one according to the signal input sequence, and setting a time domain sequence number for each time domain signal to be stored according to the signal input sequence.

[0073] In order to effectively store each time domain signal to be stored in a multi-channel parallel SRAM, it is first necessary to traverse the time domain signals to be stored one by one in the order of signal input, and assign a unique time domain serial number to each signal to ensure that the data can be correctly recorded and identified.

[0074] For example, assume that three time domain signals are sequentially input into the system for processing: signal A, signal B, and signal C. The system first receives signal A in the order in which they are input, then signal B, and finally signal C. During this process, the system sets time domain serial numbers for signals A, B, and C in turn, such as assigning time domain serial number 1 to signal A, time domain serial number 2 to signal B, and time domain serial number 3 to signal C. In this way, each signal is uniquely identified, thereby ensuring that the corresponding data can be accurately located and accessed in the subsequent processing process. In this way, data of different signals can be effectively managed and processed to ensure the orderliness and consistency of the data.

[0075] S102: Setting a plurality of split sequence numbers for the time domain signal to be stored.

[0076] Setting multiple split sequence numbers for the time domain signals to be stored can more accurately determine the position of each signal in the memory. By setting multiple split sequence numbers, the signals to be stored can be divided and classified according to different characteristics or attributes, thereby managing data storage more meticulously.

[0077] For example, for audio signals, different split sequence numbers can be set according to frequency, amplitude or other characteristics to better organize and index these signals in the memory. In this way, the storage location of each signal can be calculated more accurately, and data storage and subsequent processing operations can be effectively managed. Setting multiple split sequence numbers can improve the efficiency of data storage and retrieval, so that the system can better cope with complex data processing requirements.

[0078] See also Figure 2 , Figure 2 A method flow chart of a method for setting a split sequence number provided in an embodiment of the present application. Accordingly, step S102 can be implemented by steps A1-A3 to set multiple split sequence numbers for each time domain signal to be stored:

[0079] A1: Set the data index of the time domain signal to be stored.

[0080] In order to set multiple split sequence numbers for each time domain signal to be stored, it is first necessary to set a data index for the time domain signal to be stored. The data index can help accurately locate and identify each time domain signal so that the corresponding data can be accurately accessed and operated in subsequent processing.

[0081] In one possible implementation, the data index can be set to data_num[9:0]. Setting the data index to data_num[9:0] can limit the range of the number of bits of the data index while ensuring sufficient precision and storage space. In this setting, data_num[9:0] represents a 10-bit data index, which can represent a number range from 0 to 1023 in binary. By limiting it to 10 bits, the size of the data index can be effectively managed, and indexing and access operations for a large amount of data can be implemented within a smaller memory capacity. Such a setting can not only meet the demand for a larger amount of data, but also save storage resources and improve the efficiency and performance of the system. Therefore, selecting data_num[9:0] as the range of the number of bits of the data index can balance the relationship between the data representation range and storage efficiency.

[0082] A2: Split the data index to obtain multiple split indexes.

[0083] Splitting the data index into multiple split indexes allows for more detailed classification and management of the data. This step can organize the data more efficiently so that the data can be more accurately located and manipulated in subsequent processing.

[0084] For example, if the data index is data_num[9:0], it can be split into different parts, such as a high-order index and a low-order index, or the index can be divided into several parts according to certain rules. In this way, each split index represents a different part or attribute of the data index, which can better identify and utilize these features, thereby improving the organization and operability of the data. Split indexes help to describe and classify data in more detail to provide a more flexible and efficient way of data management.

[0085] In a possible implementation manner, splitting the data index to obtain a plurality of split indexes includes:

[0086] Determine a decomposition factor in a fast Fourier transform, and then determine the number of segments of the data index based on the decomposition factor in the fast Fourier transform. Then, evenly split the data index based on the number of segments to obtain a plurality of split indexes of equal length.

[0087] For the base 4-FFT, the decomposition factor is 4, so it can be determined that the decomposition factor in the current fast Fourier transform is 4. When the signal is converted to a base 4 representation, each data point can be represented by 5 bits (because a 4-ary number requires at least 5 different digits to express). Therefore, based on the decomposition factor 4 in the fast Fourier transform, it can be determined that the number of segments of the data index is 5. Dividing the time domain signal into 5 segments means dividing the signal into five subsequences with the same number of data points for processing in the base 4-FFT. Such segmentation helps the fast Fourier transform algorithm to process data more efficiently and provide more effective spectrum analysis results.

[0088] For example, the data index data_num[9:0] may be split into the following five split indexes:

[0089] n1 = data_num[1:0];

[0090] n2 = data_num[3:2];

[0091] n3 = data_num[5:4];

[0092] n4 = data_num[7:6];

[0093] n5=data_num[9:8].

[0094] A3: Calculate the splitting sequence number of each splitting index based on the frequency domain sequence number corresponding to the time domain signal to be stored.

[0095] After obtaining the split index, it is necessary to calculate the specific value of each split index, i.e., the split index, according to the frequency domain serial number corresponding to the time domain signal to be stored. This calculation process is based on the relationship between the specific value of the frequency domain serial number and the split index to determine the corresponding value of each split index.

[0096] For example, assuming that the frequency domain serial number of a time domain signal is 127, corresponding calculation rules or algorithms can be designed for different split indexes to calculate the specific value of each split index. These values ​​will help determine the location and characteristics of the data in the memory, allowing the system to manage and process data more accurately. Through this calculation based on the frequency domain serial number, the system can achieve precise control and allocation of split index values ​​to improve the efficiency of data storage and access, while ensuring the accuracy and reliability of data processing.

[0097] In a possible implementation manner, the calculating the splitting sequence number of each splitting index based on the frequency domain sequence number corresponding to the time domain signal to be stored includes:

[0098] The frequency domain serial number corresponding to the time domain signal to be stored is calculated. Then, based on the valid bits specified in the split index, the split serial number binary representation of each split index is determined in the frequency domain serial number. Then, the split serial number binary representation is converted into a decimal system.

[0099] It should be noted that determining the frequency domain serial number corresponding to the time domain signal involves converting the time domain signal to the frequency domain through FFT, and calculating the frequency domain index according to the sampling frequency and signal length. This process is described in detail below through a specific example.

[0100] For example, assuming the following parameters: time domain signal length N = 256, sampling frequency fs = 4096 Hz (Hertz), it is necessary to find the frequency domain serial number corresponding to the time domain signal with a frequency of 2032 Hz. The frequency domain serial number k can be calculated by the following formula: k = (fk·N) / fs, where fk is the target frequency; N is the length of the time domain signal; and fs is the sampling frequency. Substitute the formula to calculate the frequency domain serial number k = (fk·N) / fs = (2032·256) / 4096 = 127. In this way, it is determined that the frequency domain serial number corresponding to the time domain signal with a frequency of 2032 Hz is 127.

[0101] In addition, the valid bits specified in the split index refer to the number of bits used to represent different split numbers in the index. These valid bits are used to distinguish different split numbers so that the exact position of each time domain signal in the memory can be calculated. The number of valid bits depends on the system design and data processing requirements, and is usually determined on a case-by-case basis to ensure correct data splitting and storage. For the split index data_num[1:0], data_num[1:0] represents a 2-bit binary number used to represent the split index. Specifically: data_num[1:0] is from the most significant bit data_num[1] to the least significant bit data_num[0]. This 2-bit binary number can represent a range from 00 (decimal 0) to 11 (decimal 3), that is, 0, 1, 2, 3.

[0102] Exemplarily, assuming that the calculated frequency domain serial number corresponding to the time domain signal to be stored is 10 (binary representation is 0000001010), then for the split index: n1 = data_num[1:0], n2 = data_num[3:2], n3 = data_num[5:4], n4 = data_num[7:6], n5 = data_num[9:8], the split number of each split index is determined in the frequency domain serial number. The binary representation is: n1 = data_num[1:0], n2 = data_num[3:2], n3 = data_num[5:4], n4 = data_num[7:6], n5 = data_num[9:8] num[1:0]=10 (2 in decimal), n2=data_num[3:2]=10 (2 in decimal), n3=data_num[5:4]=00 (0 in decimal), n4=data_num[7:6]=00 (0 in decimal), n5=data_num[9:8]=00 (0 in decimal) Therefore, when the frequency domain number is 10, according to the above splitting method, it is obtained that n1=n2=2, n3=n4=n5=0.

[0103] It should be noted that for each time domain signal to be stored, the splitting sequence number needs to be set through steps A1-A3.

[0104] S103: Calculate the storage position of the time domain signal to be stored in the multi-channel parallel static random access memory SRAM based on the multiple split sequence numbers and storage position calculation formulas.

[0105] Based on multiple split sequence numbers and storage location calculation formulas, the specific storage location of the time domain signal to be stored in the multi-channel parallel static random access memory SRAM can be accurately determined. By combining each split sequence number with the corresponding storage location calculation formula, the system can effectively locate the location of the data in the memory and achieve efficient data management and retrieval.

[0106] In a possible implementation, the storage location calculation formula includes: a storage number calculation formula and a write address calculation formula;

[0107] The memory number calculation formula is:

[0108] sram_num=mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4;

[0109] The calculation formula for the write address is:

[0110] wr_addr=floor((64*n4+16*n3+4*n2+n1) / 2);

[0111] Among them, n1, n2, n3, n4 and n5 are the split sequence numbers.

[0112] It should be noted that the storage location calculation formula provided here is applicable to radix-4-FFT calculation.

[0113] Exemplarily, for split sequence number n1=1, n2=2, n3=n4=n5=0, according to the provided formula wr_addr=floor((64*n4+16*n3+4*n2+n1) / 2;

[0114] And sram_num = mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4 to calculate as follows:

[0115] Calculate wr_addr: multiply each item by its corresponding weight and sum it up:

[0116] wr_addr=floor((64*0+16*0+4*2+1) / 2);

[0117] wr_addr=floor((0+0+8+1) / 2);

[0118] wr_addr = floor(9 / 2);

[0119] wr_addr = floor(4.5);

[0120] Take the integer part of the result (round down): wr_addr=4.

[0121] Therefore, when n1=1, n2=2, n3=n4=n5=0, according to the given formula, wr_addr=4 is calculated.

[0122] Calculate sram_num: add n1, n2, n3, n4, n5: n1+n2+n3+n4+n5=1+2+0+0+0=3;

[0123] Modulo 4 for the above sum: mod(3,4)=3;

[0124] Calculate mod(n1,2): mod(1,2)=1;

[0125] Add the result of the first step to the result of the second step, and multiply by 4: (3+1)*4=16;

[0126] Finally, add the results of the second and third steps: sram_num=3+16=19.

[0127] Therefore, when n1=1, n2=2, n3=n4=n5=0, according to the provided formula, sram_num=19 is calculated.

[0128] This calculation method not only clarifies the physical location of data storage, but also provides guidance for subsequent reading and processing. Such accuracy and predictability greatly simplify the data operation process and ensure the security and consistency of data. In the multi-channel parallel static random access memory SRAM, based on the split sequence number and the corresponding calculation formula, each time domain signal can be quickly and accurately located and managed, thereby achieving efficient and stable data storage and retrieval operations.

[0129] S104: The time domain signal to be stored and the time domain serial number corresponding to the signal are stored in a corresponding storage position in the multi-channel parallel SRAM in association with each other.

[0130] When the time domain signal to be stored and its corresponding time domain serial number are stored in a specific position of the multi-channel parallel SRAM, accurate storage and reliable retrieval of data are achieved. This process not only ensures data integrity, but also effectively utilizes the parallel structure of SRAM to improve data access efficiency.

[0131] By locating the time domain signal and the time domain sequence number to the correct storage location, a robust data mapping mechanism is established, which provides a solid foundation for subsequent data retrieval and processing. This associative storage method ensures the orderliness of data and the efficient operation of the system. In multi-channel parallel SRAM, the process of associating the time domain signal with the time domain sequence number is designed to optimize data management and improve system performance while ensuring data consistency and traceability.

[0132] For example, taking the first 64 data of 1024-point radix 4-FFT as an example, the non-conflicting address storage method is shown in Table 2:

[0133] Table 2 Storage logic table of the first 64 data in SRAM

[0134] wr_addr = 0 wr_addr = 1 wr_addr=2 wr_addr=3 wr_addr=4 wr_addr=5 wr_addr=6 wr_addr=7 sram_num=0 0 10 19 25 34 40 49 59 sram_num=1 1 11 16 26 35 41 50 56 sram_num=2 2 8 17 27 32 42 51 57 sram_num=3 3 9 18 24 33 43 48 58 sram_num=4 7 13 22 28 37 47 52 62 sram_num=5 4 14 23 29 38 44 53 63 sram_num=6 5 15 20 30 39 45 54 60 sram_num=7 6 12 21 31 36 46 55 61

[0135] S105: performing a butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM, and storing the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

[0136] The butterfly operation is performed in the multi-channel parallel SRAM to process the time domain signal to be stored, and then the butterfly operation result is stored back to the SRAM in situ according to the information associated with the time domain sequence number. This process fully demonstrates efficient and powerful data processing and management.

[0137] Through butterfly operation, complex processing and transformation of time domain signals can be performed to generate new data results, which can effectively extract signal features and achieve data processing goals. Storing the butterfly operation results directly back to the original location not only reduces the overhead of data transmission and storage, but also retains the connection and association between data to the greatest extent.

[0138] Based on the association of time domain serial numbers, the butterfly operation results are stored in-situ in multi-channel parallel SRAM, further optimizing the data processing process. This intelligent data management method not only improves the performance and efficiency of the system, but also ensures the integrity and accuracy of the data. Through this process, efficient processing and storage of time domain signals are achieved, providing strong support for data processing and application, and reflecting the huge potential of advanced technology in the field of data processing.

[0139] See also Figure 3 , Figure 3 A method flow chart of another data processing method provided in an embodiment of the present application. Specifically, step S105 can be implemented through steps B1-B6:

[0140] B1: Determine decomposition factors in a fast Fourier transform, and determine the butterfly operation series based on the decomposition factors in the fast Fourier transform.

[0141] The process of “determining the decomposition factors in the fast Fourier transform” is consistent with the process of “determining the decomposition factors in the fast Fourier transform” mentioned in step A2, and will not be repeated here.

[0142] In the Fast Fourier Transform (FFT), the determination of the number of butterfly operations depends on the decomposition factor. For the radix-4-FFT, the decomposition factor is 4, and each butterfly node needs to process 4 data points simultaneously. According to the characteristics of the decomposition factor of 4, in the radix-4-FFT, each level of butterfly operation involves the number of data points processed simultaneously. Therefore, when the decomposition factor is 4, 5 levels of butterfly operations are required to complete the entire FFT calculation process. The butterfly operations are performed step by step to ensure that each data point is processed and exchanged correctly, and finally an accurate FFT result is obtained.

[0143] B2: Determine the signal reading position based on the butterfly operation position determination formula and the split sequence number.

[0144] Determining the signal reading position based on the butterfly operation position determination formula and the splitting sequence number refers to determining the signal reading position based on the splitting sequence numbers n1, n2, n3, n4 and n5. There are different butterfly operation position determination formulas for different levels of butterfly operations. After calculating the first signal reading position based on the butterfly operation position determination formula, the other 7 signal reading positions need to be determined. The calculation method of the other 7 signal reading positions is as follows: addr_base2=addr_base+1; addr_base3=addr_base+2; addr_base4=addr_base+3; addr_base5=addr_base+4; addr_base6=addr_base+5; addr_base7=addr_base+6; addr_base8=addr_base+7, where addr_base is the calculated first signal reading position. The first signal reading position is calculated based on the butterfly operation position determination formula.

[0145] Specifically, for the first-level butterfly operation, the butterfly operation position determination formula includes the wr_addr calculation formula and the sram_num calculation formula, wr_addr = floor((64*n5+16*n4+4*n3+n2) / 2), sram_num = mod(n1+n2+n3+n4+n5,4)+mod(n2,2)*4; for the second-level butterfly operation, the butterfly operation position determination formula includes the wr_addr calculation formula and the sram_num calculation formula, the sram_num calculation formula of the second-level butterfly operation is consistent with the first level, the wr_addr of the second-level butterfly operation is floor((64*n2+16*n4+4*n3+n2) / 2); for the third-level butterfly operation, the butterfly operation position determination formula includes the wr_addr calculation formula and the sram_num calculation formula, the sram_num calculation formula of the third-level butterfly operation is consistent with the first level. The formula is consistent with the first level, the wr_addr of the third level butterfly operation is floor((64*n4+16*n1+4*n3+n2) / 2); for the fourth level butterfly operation, the butterfly operation position determination formula includes the wr_addr calculation formula and the sram_num calculation formula, and the sram_num calculation formula of the fourth level butterfly operation is consistent with the first level, and the wr_addr of the fourth level butterfly operation is floor((64*n4+16*n3+4*n2+n1) / 2); for the fifth level butterfly operation, the butterfly operation position determination formula includes the wr_addr calculation formula and the sram_num calculation formula, and the sram_num of the fifth level butterfly operation is mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4, and the wr_addr of the fifth level butterfly operation is floor((64*n4+16*n3+4*n2+n1) / 2).

[0146] B3: Based on the signal reading position, read the time domain signal to be stored in the multi-channel parallel SRAM.

[0147] The signal reading position is determined based on the split serial numbers n1, n2, n3, n4 and n5. If it is required to take out the 8 data required for calculation from the 8-way parallel SRAM, then one reading needs to read 8 determined signal reading positions. If there are 1024 storage locations in the SRAM, then it needs to read 128 times to complete the reading of all the time domain signals to be stored in the SRAM, and perform butterfly operations on all the time domain signals read 128 times one by one, and store the results of the butterfly operations back to the SRAM in situ.

[0148] B4: Based on the number of read bits, a plurality of butterfly computing units are used to simultaneously perform butterfly computing on the read time domain signal to be stored to obtain a computing signal.

[0149] If the requirement is to take out the 8 data required for calculation from the 8-way parallel SRAM, then two butterfly computing units are required to perform butterfly operations on 4 pairs of the time domain signals to be stored at the same time, until the first-level butterfly operation is completed after 128 calculations. By using multiple butterfly computing units to perform butterfly operations on the time domain signals to be stored, the calculation speed can be effectively improved to meet the demand for calculation time. This parallel computing method allows multiple signals to be processed in different butterfly computing units at the same time, thereby speeding up the overall computing speed. By making full use of hardware resources and the advantages of parallel computing, the butterfly operations of multiple signals can be completed in a shorter time, ensuring that the system can respond and process large amounts of data in a timely manner to meet the time requirements of computing tasks.

[0150] It should be noted that the butterfly operation is implemented based on the rotation factor. Let the basis of the rotation factor W N for:

[0151] W N =e -J*2*π / N

[0152] From the decomposition formula of the radix 4-FFT algorithm, it can be concluded that the rotation factor required for each butterfly operation is and Let the rotation factor be Then the corresponding rotation factor is generated according to the position m and basis of the butterfly operation. The calculation formula of m for each of the five levels is as follows:

[0153] First level: m = 0;

[0154] Second level: m = n5*n1*64;

[0155] Level 3: m = (4*n4+n5)*n1*16;

[0156] Level 4: m = (16*n3+4*n4+n5)*n1*4;

[0157] Fifth level: m = (64*n2+16*n3+4*n4+n5)*n1.

[0158] From the nature of butterfly operation, we know that the first rotation factor of each butterfly operation is 1, so each butterfly operation only needs 3 rotation factors, and two butterfly operation units correspond to 6 rotation factors. As can be seen from the above table, the first-level rotation factors are all 1 and do not need to be saved, while the fifth level contains all the rotation factors used in the first four levels, so only the 256*3 rotation factors corresponding to the fifth level need to be saved. The 256*3 rotation factors need to be saved as 6*128 in the order of butterfly operation, divided into 6 modules, and each module saves 128, so as to meet the parallel reading of the rotation factors.

[0159] B5: storing the operation signal and its corresponding time domain serial number in the multi-channel parallel SRAM in situ.

[0160] Storing the calculated signal and its corresponding time domain serial number in situ in multi-way parallel SRAM means storing the calculated signal value and the corresponding time domain serial number directly in the corresponding position of SRAM without additional data transfer or processing. This operation ensures that the relevant information is accurately stored in SRAM, making subsequent reading and processing more efficient and reliable. By storing in situ, the data management process can be simplified, unnecessary complexity can be reduced, and the overall performance and response speed of the system can be improved.

[0161] B6: For the multi-channel parallel SRAM storing the new operation signal, repeat the above steps B2-B5 until the number of repetitions reaches the number of butterfly operation stages.

[0162] For the multi-channel parallel SRAM storing the new operation signal, the steps of determining the B2 signal reading position, reading the B3 signal, butterfly operation at B4 and in-situ storage at B5 are repeated until the number of repetitions reaches the number of butterfly operation stages.

[0163] In one possible implementation, after completing the five-stage butterfly operation, the FFT results are stored in eight parallel SRAMs. In order to output the FFT results in frequency domain order, the correct read address and storage area number (ban_num) need to be determined according to the storage logic of the input data. The SRAM number (sram_num) and write address (wr_addr) can be calculated by the given formula to ensure that the results are read and output in the correct order.

[0164] SRAM number calculation formula:

[0165] sram_num=mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4;

[0166] Write address calculation formula:

[0167] wr_addr=floor((64*n2+16*n3+4*n4+n5) / 2).

[0168] Based on the contents of S101-S105, it can be known that each time domain signal to be stored is first collected one by one according to the signal input order, and a corresponding time domain sequence number is set for each signal to ensure the orderly management of data. Then, multiple split sequence numbers are set for each time domain signal, and the storage position of each signal is accurately calculated in the multi-channel parallel SRAM using these sequence numbers and storage position calculation formulas. Subsequently, each time domain signal to be stored and its corresponding time domain sequence number are associated and stored in an appropriate position in the multi-channel parallel SRAM, thereby achieving effective classification and storage of data. After completing these basic operations, a butterfly operation is performed on the time domain signal stored in the multi-channel parallel SRAM, and then the butterfly operation result is directly stored in situ back in the multi-channel parallel SRAM according to the time domain sequence number associated with the original signal. This application successfully avoids the need for additional cache SRAM by accurately calculating the storage position of each signal and realizing the in-situ storage of the result, effectively reducing the occupation of hardware resources. At the same time, an in-situ storage strategy is adopted to avoid data migration between different SRAMs and reduce data handling and copying operations, thereby reducing the demand for data transmission, improving storage efficiency, speeding up data processing, and reducing the overall power consumption of the system.

[0169] See also Figure 4 , Figure 4 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. Figure 4 As shown, the data processing device includes: a data multiplexer (Multiplexer, MUX), a butterfly operation unit and a multi-way parallel static random access memory SRAM; Figure 4 The multi-way parallel SRAM shown in is an 8-way parallel SRAM;

[0170] A data multiplexer MUX, a butterfly operation unit and a multi-way parallel SRAM; the MUX includes a first MUX and a second MUX;

[0171] The first MUX is connected to the multi-way parallel SRAM; the first MUX is also connected to the butterfly operation unit; the second MUX is connected to the multi-way parallel SRAM; the second MUX is also connected to the butterfly operation unit;

[0172] The first MUX is used to collect each time domain signal to be stored one by one according to the signal input sequence, and set a time domain sequence number for each time domain signal to be stored according to the signal input sequence;

[0173] The first MUX is further used to set a plurality of split sequence numbers for the time domain signal to be stored;

[0174] The first MUX is further used to calculate the storage position of the time domain signal to be stored in the multi-channel parallel SRAM based on the multiple split sequence numbers and storage position calculation formulas;

[0175] The first MUX is further used to associate and store the time domain signal to be stored and the time domain sequence number corresponding to the signal in a corresponding storage position in the multi-channel parallel SRAM;

[0176] The butterfly operation unit is used to perform butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM;

[0177] The MUX is further configured to store the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

[0178] In a possible implementation manner, the first MUX is specifically used to:

[0179] Setting the data index of the time domain signal to be stored;

[0180] Splitting the data index to obtain multiple split indexes;

[0181] The splitting sequence number of each splitting index is calculated based on the frequency domain sequence number corresponding to the time domain signal to be stored.

[0182] In a possible implementation manner, the first MUX is further specifically configured to:

[0183] Determine the decomposition factors in the Fast Fourier Transform;

[0184] Determine the number of segments of the data index based on the decomposition factor in the fast Fourier transform;

[0185] The data index is evenly split based on the number of split segments to obtain a plurality of split indexes of equal length.

[0186] In a possible implementation manner, the first MUX is further specifically configured to:

[0187] Calculating the frequency domain sequence number corresponding to the time domain signal to be stored;

[0188] Determine, based on the valid bits specified in the split index, a split sequence number binary representation of each split index in the frequency domain sequence number;

[0189] Convert the split sequence number binary representation to decimal.

[0190] In a possible implementation, the storage location calculation formula includes: a storage number calculation formula and a write address calculation formula;

[0191] The memory number calculation formula is used to determine the target memory of the time domain signal to be stored in the multi-channel parallel SRAM; the write address calculation formula is used to determine the specific address of the time domain signal to be stored in the target memory;

[0192] The memory number calculation formula is:

[0193] sram_num=mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4;

[0194] The write address calculation formula is:

[0195] wr_addr=floor((64*n4+16*n3+4*n2+n1) / 2);

[0196] Among them, n1, n2, n3, n4 and n5 are the split sequence numbers.

[0197] In a possible implementation, the butterfly operation unit includes a first butterfly operation unit and a second butterfly operation unit; the first MUX is connected to the first butterfly operation unit and the second butterfly operation unit respectively; the second MUX is connected to the output of the first butterfly operation unit and the second butterfly operation unit respectively;

[0198] A second MUX, used to determine a decomposition factor in a fast Fourier transform, and to determine a butterfly operation series based on the decomposition factor in the fast Fourier transform;

[0199] The second MUX is further used to determine the signal reading position based on the butterfly operation position determination formula and the split sequence number;

[0200] The second MUX is further used to read the time domain signal to be stored in the multi-channel parallel SRAM based on the signal reading position;

[0201] The second MUX is further used to use a plurality of butterfly computing units to simultaneously and evenly send the read time domain signal to be stored to the first butterfly computing unit and the second butterfly computing unit for butterfly computing to obtain a computing signal based on the number of read bits; the computing signal has a one-to-one correspondence with the time domain sequence number corresponding to the time domain signal to be stored used when calculating the computing signal;

[0202] The first MUX stores the operation signal and its corresponding time domain serial number in the multi-channel parallel SRAM in situ;

[0203] The repetitive execution module is used to repeatedly execute the steps of determining the signal reading position, reading the signal, butterfly operation and in-situ storage for the multi-channel parallel SRAM storing the new operation signal until the number of repetitive executions reaches the number of butterfly operation stages.

[0204] In addition, an embodiment of the present application also provides a data processing device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the data processing method described above is implemented.

[0205] In addition, an embodiment of the present application further provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a terminal device, the terminal device executes the data processing method as described above.

[0206] This application accurately calculates the storage location and implements in-situ storage of the results, successfully avoiding the use of additional cache SRAM and effectively reducing the consumption of hardware resources. At the same time, the in-situ storage strategy reduces the transmission of data between different SRAMs, reduces data copying and moving operations, improves storage efficiency, and avoids additional data transmission costs.

[0207] The above is a detailed introduction to a data processing method, device, equipment and storage medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0208] It should be understood that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A data processing method, characterized in that: The method comprises: Collect each time domain signal to be stored one by one according to the signal input sequence, and set a time domain sequence number for each time domain signal to be stored according to the signal input sequence; Setting multiple split sequence numbers for the time domain signal to be stored; Based on the plurality of split sequence numbers and storage position calculation formulas, calculating the storage position of the time domain signal to be stored in the multi-channel parallel static random access memory SRAM; The time domain signal to be stored and the time domain serial number corresponding to the signal are stored in a corresponding storage position in the multi-channel parallel SRAM; A butterfly operation is performed on the time domain signal to be stored in the multi-channel parallel SRAM, and the butterfly operation result is stored in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

2. The method according to claim 1, characterized in that The step of setting a plurality of split sequence numbers for each time domain signal to be stored comprises: Setting a data index of the time domain signal to be stored; Splitting the data index to obtain multiple split indexes; The splitting sequence number of each splitting index is calculated based on the frequency domain sequence number corresponding to the time domain signal to be stored.

3. The method according to claim 2, characterized in that The step of splitting the data index to obtain a plurality of split indexes includes: Determine the decomposition factors in the Fast Fourier Transform; Determine the number of segments into which the data index is to be split based on the decomposition factor in the fast Fourier transform; The data index is evenly split based on the number of split segments to obtain a plurality of split indexes of equal length.

4. The method according to claim 2, characterized in that: The calculating the splitting sequence number of each splitting index based on the frequency domain sequence number corresponding to the time domain signal to be stored includes: Calculating the frequency domain sequence number corresponding to the time domain signal to be stored; Determine, based on the valid bits specified in the split index, a split sequence number binary representation of each split index in the frequency domain sequence number; Convert the split sequence number binary representation to decimal.

5. The method according to claim 1, characterized in that: The storage location calculation formula includes: a storage number calculation formula and a write address calculation formula; The memory number calculation formula is used to determine the target memory of the time domain signal to be stored in the multi-channel parallel SRAM; the write address calculation formula is used to determine the specific address of the time domain signal to be stored in the target memory; The memory number calculation formula is: sram_num=mod(n1+n2+n3+n4+n5,4)+mod(n1,2)*4; The calculation formula for the write address is: wr_addr=floor((64*n4+16*n3+4*n2+n1) / 2); Among them, n1, n2, n3, n4 and n5 are the split sequence numbers.

6. The method according to claim 1, characterized in that The step of performing a butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM, and storing the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored, comprises: Determine a decomposition factor in a fast Fourier transform, and determine a butterfly operation series based on the decomposition factor in the fast Fourier transform; Determine the signal reading position based on the butterfly operation position determination formula and the split sequence number; Based on the signal reading position, reading the time domain signal to be stored stored in the multi-channel parallel SRAM; Based on the number of read bits, a plurality of butterfly computing units are used to simultaneously perform butterfly operations on the read time domain signal to be stored to obtain an operation signal; the operation signal has a one-to-one correspondence with a time domain sequence number corresponding to the time domain signal to be stored used when calculating the operation signal; The operation signal and its corresponding time domain serial number are stored in the multi-channel parallel SRAM in situ; For the multi-channel parallel SRAM storing the new operation signal, the steps of determining the signal reading position, signal reading, butterfly operation and in-situ storage are repeatedly performed until the number of repetitions reaches the number of butterfly operation stages.

7. A data processing device, characterized in that: The device comprises: a data multiplexer MUX, a butterfly operation unit and a multi-channel parallel SRAM; The MUX is connected to the multi-channel parallel SRAM; the MUX is also connected to the butterfly operation unit; The MUX is used to collect each time domain signal to be stored one by one according to the signal input sequence, and set a time domain sequence number for each time domain signal to be stored according to the signal input sequence; The MUX is further used to set a plurality of split sequence numbers for the time domain signal to be stored; The MUX is further used to calculate the storage position of the time domain signal to be stored in the multi-channel parallel SRAM based on the multiple split sequence numbers and storage position calculation formulas; The MUX is further used to associate and store the time domain signal to be stored and the time domain sequence number corresponding to the signal in a corresponding storage position in the multi-channel parallel SRAM; The butterfly operation unit is used to perform butterfly operation on the time domain signal to be stored in the multi-channel parallel SRAM; The MUX is further configured to store the butterfly operation result in situ in the multi-channel parallel SRAM based on the time domain sequence number stored in association with the time domain signal to be stored.

8. The device according to claim 7, characterized in that The MUX is specifically used for: Setting the data index of the time domain signal to be stored; Splitting the data index to obtain multiple split indexes; The splitting sequence number of each splitting index is calculated based on the frequency domain sequence number corresponding to the time domain signal to be stored.

9. A data processing device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the data processing method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device executes the data processing method according to any one of claims 1 to 6.

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