A logic synthesis method and device based on precise synthesis

Abstract

This invention relates to the field of circuit optimization technology, specifically to a logic synthesis method and apparatus based on precise synthesis. The method includes: first, acquiring a target two-input combinational logic gate netlist; traversing each node in the netlist and generating a corresponding partition set for each node during the traversal; then, based on the optimization gain of each partition in the partition set, optimizing and replacing the corresponding node in the netlist, and obtaining the optimized and replaced target two-input combinational logic gate netlist; next, calculating the simulated truth table corresponding to each node in the optimized and replaced netlist; finally, based on the simulated truth table, removing redundant nodes in the optimized and replaced netlist, and obtaining the optimized final two-input combinational logic gate netlist. This invention enables precise synthesis to be applied to large-scale netlists and maximizes the optimization scope and improves the optimization effect with less additional time consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit optimization, and in particular to a logic synthesis method and device based on precise synthesis. Background Art

[0002] Logic synthesis is widely used in chip design, digital circuit design and embedded systems. Its main goal is to optimize the logic netlist in circuit design, reduce the number of logic nodes and logic levels, thereby improving circuit performance, reducing power consumption and reducing chip area.

[0003] Exact synthesis is a method that uses SAT (Boolean satisfiability problem) solving technology to find the minimum number of logic nodes required to implement a Boolean function f with n inputs and m outputs. Exact synthesis can ensure that the solution with the minimum number of logic nodes is returned given a Boolean function and logic node type, providing the optimal logic implementation. However, the defects of exact synthesis are also obvious. First, the solution process of exact synthesis is to continuously increase the number of nodes and call SAT to determine whether the Boolean function f can be implemented by nodes with this number of nodes. SAT solving is a relatively time-consuming process, and as the number of nodes increases, the time consumption increases sharply. Therefore, it is only suitable for small Boolean functions. In addition, the minimum number of logic nodes does not mean the minimum number of logic levels, and the number of logic levels often reflects the performance of the results better than the number of logic nodes.

[0004] Therefore, existing precise synthesis technology is difficult to apply to large designs, and the logic level optimization effect is insufficient. Summary of the invention

[0005] In view of this, the present invention provides a logic synthesis method and device based on precise synthesis to solve the problem that the existing precise synthesis technology is difficult to apply to large-scale designs and the optimization effect of the logic level is insufficient.

[0006] In a first aspect, the present invention provides a logic synthesis method based on precise synthesis, the method comprising:

[0007] Obtaining a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized;

[0008] Traversing each node in the target two-input combinational logic gate netlist, and generating a corresponding partition set for each node during the traversal process;

[0009] Based on the optimization benefit of each partition in the partition set, the corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained;

[0010] Calculate the analog truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and substitution;

[0011] Based on the simulation truth table, the redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared, and the optimized final two-input combinational logic gate netlist is obtained.

[0012] The above scheme can accurately evaluate the contribution of each partition to the overall circuit optimization, i.e., the optimization benefit, by traversing each node in the target two-input combinational logic gate netlist and generating a corresponding partition set for each node. Based on these optimization benefits, the optimal partition is selected for replacement, thereby ensuring that each replacement can bring optimization effect. After the optimization replacement, the redundant nodes can be accurately identified by calculating the analog truth table of each node. Subsequently, the redundant nodes are removed, which not only reduces the complexity and power consumption of the circuit, but also improves the stability and reliability of the circuit. The above scheme decomposes the large-scale netlist into multiple partitions through the partitioning strategy, and accurately synthesizes each subnetlist or partition, so that the accurate synthesis can be applied to a larger-scale netlist while maintaining a high optimization effect. Based on the accurate synthesis strategy and the verification of the analog truth table, it can ensure that the optimized circuit is completely consistent with the original circuit in function, while reducing redundancy and unnecessary complexity.

[0013] In an optional implementation, the target two-input combinational logic gate netlist includes nodes and edges, and the nodes are two-input combinational logic nodes.

[0014] In an optional implementation, the step of optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimization benefit of each partition in the partition set, and obtaining the target two-input combinational logic gate netlist after optimization and replacement includes:

[0015] For each node, calculating the optimization benefit of each partition in the partition set, and selecting the target number of partitions with the highest optimization benefits as the best partitions for the corresponding node;

[0016] Based on the optimal partition, corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained.

[0017] In an optional implementation, for each node, calculating the optimization benefit of each partition in the partition set, and selecting a target number of partitions with the highest optimization benefits as the best partitions for the corresponding node, includes:

[0018] For each partition in the partition set of each node, generating a Boolean function of a local netlist corresponding to each partition based on an input signal and an output signal of each partition;

[0019] Performing multi-threaded solving of the Boolean function by using an accurate synthesis solver, and obtaining a series of netlists returned by the accurate synthesis solver;

[0020] Replacing the Boolean functions of the local netlists corresponding to each partition with a series of netlists returned by the precise synthesis solver, and calculating the optimization benefit after the replacement; the optimization benefit is the number of nodes reduced by the partition;

[0021] In the partition set, the partitions with the highest optimization benefits before the target number are retained as the best partitions for the corresponding nodes.

[0022] In an optional implementation, the step of optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimal partitioning, and obtaining the target two-input combinational logic gate netlist after optimization and replacement, includes:

[0023] Based on the optimal partition corresponding to each node, construct a benefit graph of the target two-input combinational logic gate netlist;

[0024] Adding the highest benefit of the best partition corresponding to each node to the corresponding node of the benefit graph, and calculating the maximum weighted independent set of the benefit graph;

[0025] According to the result of the maximum weighted independent set, the partition corresponding to each node in the target two-input combinational logic gate netlist is replaced with the netlist with the highest benefit to obtain the target two-input combinational logic gate netlist after optimization and replacement.

[0026] In an optional implementation, the analog truth table corresponding to each node in the target two-input combinational logic gate netlist after the calculation optimization substitution includes:

[0027] Traversing all nodes in the target two-input combinational logic gate netlist after optimization and replacement, and generating a corresponding optimization window for each traversed node;

[0028] Within the optimization window, a simulation truth table of a corresponding node is generated based on the logic function and input signal of each node.

[0029] In an optional implementation, based on the simulation truth table, removing redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement, and obtaining the optimized final two-input combinational logic gate netlist, includes:

[0030] Based on the simulated truth table of each node, identifying redundant nodes in the target two-input combinational logic gate netlist after optimized replacement;

[0031] Calculate the maximum fan-out-free cone for each redundant node;

[0032] The redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared based on the maximum no-fan-out cone, and the optimized final two-input combinational logic gate netlist is obtained.

[0033] In a second aspect, the present invention provides a logic synthesis device based on precise synthesis, the device comprising:

[0034] A netlist input module, used to obtain a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized;

[0035] A partition set acquisition module, used for traversing each node in the target two-input combinational logic gate netlist, and generating a corresponding partition set for each node during the traversal process;

[0036] A partition optimization replacement module, used to optimize and replace corresponding nodes in the target two-input combinational logic gate netlist based on the optimization benefit of each partition in the partition set, and obtain the target two-input combinational logic gate netlist after optimization and replacement;

[0037] A simulation truth table acquisition module, used for calculating the simulation truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and replacement;

[0038] The netlist output module is used to clear redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement based on the simulation truth table, and obtain the optimized final two-input combinational logic gate netlist.

[0039] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute a logic synthesis method based on precise synthesis of the above-mentioned first aspect or any corresponding embodiment thereof.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a logic synthesis method based on precise synthesis according to the first aspect or any corresponding embodiment thereof.

[0041] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute a logic synthesis method based on precise synthesis according to the first aspect or any corresponding embodiment thereof.

[0042] The technical solution provided by the present invention may include the following beneficial effects:

[0043] The present invention can accurately evaluate the contribution of each partition to the overall circuit optimization, i.e., the optimization benefit, by traversing each node in the target two-input combinational logic gate netlist and generating a corresponding partition set for each node. Based on these optimization benefits, the optimal partition is selected for replacement, thereby ensuring that each replacement can bring optimization effect. After the optimization replacement, the redundant nodes can be accurately identified by calculating the analog truth table of each node. Subsequently, the redundant nodes are removed, which not only reduces the complexity and power consumption of the circuit, but also improves the stability and reliability of the circuit. In addition, the present invention decomposes the large-scale netlist into multiple partitions through a partitioning strategy, and accurately synthesizes each subnetlist or partition, so that the accurate synthesis can be applied to a larger-scale netlist while maintaining a high optimization effect. Based on the verification of the accurate synthesis strategy and the analog truth table, it can ensure that the optimized circuit is completely consistent with the original circuit in function, while reducing redundancy and unnecessary complexity.

[0044] In addition, the netlist obtained by the present invention based on precise synthesis can ensure the optimal number of nodes in the local netlist, so its optimization effect for some relatively small netlists is far better than some heuristic logic synthesis methods. Furthermore, by partitioning, precise synthesis can be applied to large-scale netlists, and by eliminating redundant logic, the optimization scope is expanded as much as possible with less additional time consumption, thereby improving the optimization effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 is a flow chart of a logic synthesis method based on precise synthesis according to an embodiment of the present invention;

[0047] Figure 2 is a flow chart of another logic synthesis method based on precise synthesis according to an embodiment of the present invention;

[0048] Figure 3 is a flow chart of another logic synthesis method based on precise synthesis according to an embodiment of the present invention;

[0049] Figure 4 is a flow chart of an optimization link based on precise synthesis according to an embodiment of the present invention;

[0050] Figure 5is a node topology diagram of a two-input combinational logic gate netlist according to an embodiment of the present invention;

[0051] Figure 6 The embodiment of the present invention is shown Figure 5 The corresponding node replacement diagram;

[0052] Figure 7 The embodiment of the present invention is shown Figure 5 The corresponding node profit graph;

[0053] Figure 8 is a flow chart of a redundant logic elimination link according to an embodiment of the present invention;

[0054] Fig. 9 is a schematic diagram of the structure of another combinational logic gate netlist according to an embodiment of the present invention;

[0055] Fig.10 is a structural block diagram of a logic synthesis device based on precise synthesis according to an embodiment of the present invention;

[0056] Fig.11 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] It should be noted that the target two-input combinational logic gate netlist obtained by the present invention is the logic netlist in the logic synthesis circuit design, that is, the digital circuit to be optimized. The present invention reduces the number of logic nodes and the number of logic levels, thereby improving the performance of the digital circuit to be optimized, reducing power consumption and reducing chip area.

[0059] A logic netlist is a structured description of a digital circuit. It lists the logic gates in a digital circuit and their connections, as well as the input and output ports. A logic netlist usually consists of logic gates (such as AND gates, OR gates, NOT gates, etc.) and the connections (or "nets") between the logic gates. The input and output of each logic gate are connected through a net. A logic netlist is used to describe the function and structure of a digital circuit and is the basis for circuit design and analysis.

[0060] The nodes in the logic netlist refer to the logic gates actually used in the logic netlist. Each logic gate is a node, and the number of nodes is the total number of these logic gates. The logic level refers to the longest distance of the logic gates that the input signal passes through from the input to the output (that is, the longest path for signal transmission). In other words, the nodes in the target two-input combinational logic gate netlist correspond to the logic gates in the digital circuit to be optimized, and the edges (or wires, nets) in the target two-input combinational logic netlist correspond to the connections in the digital circuit to be optimized.

[0061] According to an embodiment of the present invention, a logic synthesis method embodiment based on precise synthesis is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0062] In this embodiment, a logic synthesis method based on precise synthesis is provided. Figure 1 is a flow chart of a logic synthesis method based on precise synthesis according to an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps:

[0063] Step S101, obtaining a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized.

[0064] For further information, see Figure 2 The flowchart of another logic synthesis method based on precise synthesis is shown. The input of this embodiment is a two-input combinational logic gate netlist (the combinational logic represents that there is no sequential node in the netlist). The netlist is composed of nodes and edges. Each node is a two-input combinational logic node (for example, AND, OR, NOT combinational logic gates. There are 16 types of combinational logic gates under two-input conditions). The connection relationship between the output of a node and the input of another node is represented by an edge. After obtaining the input target combinational logic gate netlist, the target combinational logic gate netlist is first optimized based on precise synthesis, and then the target combinational logic gate netlist optimized based on precise synthesis is eliminated by redundant logic. Finally, the optimized two-input combinational logic gate netlist is obtained. In this embodiment, any Boolean function can be represented by a two-input combinational logic gate netlist.

[0065] Furthermore, this embodiment first obtains a target two-input combinational logic gate netlist, which describes the logic structure of the digital circuit to be optimized and includes connection information and logical relationships of all logic gates (such as AND gates, OR gates, NOT gates, etc.).

[0066] Step S102, traversing each node in the target two-input combinational logic gate netlist, and generating a corresponding partition set for each node during the traversal process.

[0067] Furthermore, this embodiment traverses each node in the target two-input combinational logic gate netlist, each node representing a logic gate. During the traversal process, a partition set of each node is generated, and the partition set indicates the possible logical function partition or alternative form of each node, that is, different logical representation methods.

[0068] Step S103, based on the optimization benefit of each partition in the partition set, the corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained.

[0069] Furthermore, this embodiment evaluates each partition set generated in step S102, and calculates the optimization benefit of each partition, which indicates the number of logic gates reduced by each partition, that is, the number of nodes reduced by the partition. Based on the optimization benefit, each node is optimized and replaced, that is, the node is replaced with an alternative logic gate with better performance.

[0070] Step S104, calculating a simulation truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and replacement.

[0071] Furthermore, this embodiment calculates the simulated truth table of each node in the netlist after optimization and replacement. The truth table is a table that describes the output results of the circuit under all input conditions. By calculating the truth table, it can be verified whether each node still performs logical operations as expected after optimization, ensuring that no errors or loss of logical functions are introduced during the optimization process, and verifying the correctness of the logical functions.

[0072] Step S105 , based on the simulation truth table, clearing redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement, and obtaining the optimized final two-input combinational logic gate netlist.

[0073] Furthermore, this embodiment uses the simulated truth table calculated in step S104 to identify and remove redundant nodes in the netlist. Redundant nodes are nodes that have no practical effect on the logic function, that is, removing them does not affect the final output, and can be removed to reduce the complexity of the circuit. After removing these redundant nodes, the final netlist obtained will be more concise and have higher efficiency and performance.

[0074] In summary, the present invention can accurately evaluate the contribution of each partition to the overall circuit optimization, i.e., the optimization benefit, by traversing each node in the target two-input combinational logic gate netlist and generating a corresponding partition set for each node. Based on these optimization benefits, the optimal partition is selected for replacement, thereby ensuring that each replacement can bring optimization effect. After the optimization replacement, the redundant nodes can be accurately identified by calculating the analog truth table of each node. Subsequently, the redundant nodes are removed, which not only reduces the complexity and power consumption of the circuit, but also improves the stability and reliability of the circuit. In addition, the present invention decomposes a large-scale netlist into multiple partitions through a partitioning strategy, and accurately synthesizes each subnetlist or partition, so that the accurate synthesis can be applied to a larger-scale netlist while maintaining a high optimization effect. Based on the verification of the accurate synthesis strategy and the analog truth table, it can ensure that the optimized circuit is completely consistent with the original circuit in function, while reducing redundancy and unnecessary complexity.

[0075] In addition, the netlist obtained by the present invention based on precise synthesis can ensure the optimal number of nodes in the local netlist, so its optimization effect for some relatively small netlists is far better than some heuristic logic synthesis methods. Furthermore, by partitioning, precise synthesis can be applied to large-scale netlists, and by eliminating redundant logic, the optimization scope is expanded as much as possible with less additional time consumption, thereby improving the optimization effect.

[0076] In this embodiment, another logic synthesis method based on precise synthesis is provided. Figure 3 is a flowchart of another logic synthesis method based on precise synthesis according to an embodiment of the present invention, such as Figure 3 As shown, the process includes the following steps:

[0077] Step S301, obtaining a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized.

[0078] In an optional implementation, the target two-input combinational logic gate netlist includes nodes and edges, and the node is a two-input combinational logic node.

[0079] Step S302, traverse each node in the target two-input combinational logic gate netlist, and generate a corresponding partition set for each node during the traversal process.

[0080] In an optional implementation, step S302 includes:

[0081] Traverse each node in the target two-input combinational logic gate netlist in topologically sorted order;

[0082] For each node, a corresponding partition set is generated according to the input signal of each node.

[0083] Furthermore, in the traversal process, in order to ensure that the input dependencies of the logic gates are correctly processed, this embodiment adopts a topological sorting method. Topological sorting is an algorithm for sorting the vertices of a directed acyclic graph (DAG). In the logic gate netlist, the connection relationship between nodes can be regarded as a directed graph, so topological sorting can be used to ensure the order of traversal, that is, first traverse those nodes without pre-dependencies, and then traverse the nodes that depend on them. For each node (logic gate), this embodiment generates a corresponding partition set based on its input signal. A partition set is a set of logical expressions. The purpose of generating a partition set is to obtain different logic implementations, which will serve as the basis for subsequent optimization steps to evaluate the optimization benefits of different alternatives and select the best alternative to replace the original node.

[0084] For further information, see Figure 4 The flowchart of the optimization link based on precise synthesis is shown. Based on the input target two-input combinational logic gate netlist, the nodes in the netlist are first traversed in topological order and a corresponding partition set is generated for each node during the traversal process. The benefit of each partition can be calculated, and the partition with the highest benefit is retained as the partition corresponding to the node. After obtaining the partitions corresponding to all nodes, optimization replacement is performed to obtain the optimized two-input combinational logic gate netlist.

[0085] The method of generating partitions in this embodiment is by enumerating the input nodes of each node and the combination of their partitions. The process has two parameters that can be set manually, namely the input signal number limit k for the partition and the reserved number limit p for the partition. Wherein k means that all generated partitions must satisfy the number of input signals less than or equal to k, and p means the number of partitions that each node can be used to enumerate the next node partition and retain in the process of generating node partitions. Generally, the higher the value of k is set, the better the optimization effect, but the running time will increase significantly with the increase of k value. The optimization effect will be improved to a certain extent as the p value increases within a certain range, but when the p value exceeds a certain limit, the increase of the p value will not have a significant impact on the result, and the increase of the p value will also significantly increase the running time. The setting of the p value and the k value can be manually debugged based on the target netlist size and the expected running time. That is, this embodiment first sets two initialization parameters: the limit k of the number of input signals to be divided and the limit p of the number of divisions to be retained by each node. For each node, this embodiment enumerates all possible division combinations, satisfying the following conditions: the number of input signals contained in each division ≤ k, that is, the number of input signals of each division in the division set is less than or equal to the limit k of the number of input signals to be divided. All divisions that meet the conditions for each node are saved to obtain the corresponding division set generated by each node.

[0086] Step S303 : For each node, calculate the optimization benefit of each partition in the partition set, and select a target number of partitions with the highest optimization benefits as the best partitions for the corresponding node.

[0087] In an optional implementation, step S303 includes:

[0088] For each partition in the partition set of each node, generating a Boolean function of a local netlist corresponding to each partition based on an input signal and an output signal of each partition;

[0089] Performing multi-threaded solving of the Boolean function by using an accurate synthesis solver, and obtaining a series of netlists returned by the accurate synthesis solver;

[0090] Replace the Boolean function of the local netlist corresponding to each partition with a series of netlists returned by the exact synthesis solver, and calculate the optimization benefit after the replacement; the optimization benefit is the number of nodes reduced by the partition;

[0091] In this partition set, the partitions with the highest optimization benefits before the target number are retained as the best partitions for the corresponding nodes.

[0092] Further, for each partition in the partition set of each node, this embodiment first generates a Boolean function of a corresponding local netlist according to its input signal and output signal. The Boolean function is a mathematical description of the partition logic function, which is used for subsequent analysis and optimization. Next, this embodiment uses a precise synthesis solver to perform multi-threaded solution on these Boolean functions. The precise synthesis solver is a tool that can find the optimal or approximately optimal logic network to implement a given Boolean function. Through multi-threaded solution, this process can be accelerated, and a series of possible netlists can be obtained as solution results (each partition corresponds to a series of possible netlists). Then, this embodiment replaces the Boolean function of the original local netlist of each partition with one of the series of netlists returned by the precise synthesis solver in turn, and calculates the optimization benefit brought by this replacement. The optimization benefit of this embodiment is defined as the number of nodes reduced after the replacement, that is, the new netlist logically reduces the number of unnecessary logic elements. Finally, in the partition set of the node, the optimization benefit is sorted according to the level of optimization benefit, and the partition with the highest optimization benefit before the target number is selected as the best partition of the node. This optimal partition will be used to replace the original nodes in subsequent steps to achieve optimization goals such as reducing the number of nodes, reducing power consumption, and improving performance.

[0093] Further, for the specific generation method of the division in this embodiment, please refer to Figure 5 , Figure 5 A schematic diagram of the node topology of a two-input combinational logic gate netlist is shown in FIG. Figure 5As shown, a topological order of nodes is node 3, node 4, node 5, node 1, node 2, node 0. Node 3 has only one partition {{I0, I1}}, similarly node 4 has only one partition {{I2, I3}}, node 5 has only one partition {{I4, I5}}, and node 1 has 4 partitions {{node 3, node 4}, {I0, I1, node 4}, {I2, I3, node 3}, {I0, I1, I2, I3}}. It can be seen that the partition of node 1 is the combination of its two parent nodes and their partitions. Similarly, node 2 also has 4 partitions, namely {{node 4, node 5}, {I2, I3, node 5}, {I4, I5, node 4}, {I2, I3, I4, I5}}. Assume that the k value is 4, that is, the number of input signals divided is less than or equal to 4, then all the partitions of node 0 are {{node 1, node 2}, {node 3, node 4, node 2}, {node 1, node 4, node 5}, {node 3, node 4, node 5}, {I0, I1, node 4, node 5}, {I2, I3, node 3, node 5}, {I4, I5, node 3, node 4}}. Every time a partition is generated, the benefit of the partition can be calculated. The calculation method of the partition benefit is: 1. Based on the partition, the Boolean function of the local netlist is obtained. 2. The Boolean function is passed to the precise synthesis solver. 3. A series of feasible solutions are obtained. 4. Local trial replacement is performed, and the feasible solution with the highest benefit is taken as the benefit of the partition. Since each node of the two-input combinational logic gate netlist is a combinational logic, it is easy to obtain the Boolean function of the local netlist when the input signal (partition) and the output are known. Figure 5 Taking the partition of node 1 in {I0, I1, I2, I3} as an example, assuming that node 1, node 3, and node 4 are all logic AND gates, then the Boolean function of the local netlist is f=I0·I1·I2·I3. The precise synthesis solver will receive a Boolean function and return a series of two-input combinational logic gate netlists. The precise solver is based on SAT implementation, and the time is not completely controllable. Therefore, this embodiment needs to manually set execution limits, generally two points: 1. Maximum execution time t, 2. Maximum number of netlists returned n. That is, the initialization parameters to be set in this embodiment include the above-mentioned input signal number limit k and the number of partitions retained by each node p, as well as the maximum execution time t of the precise synthesis solver and the maximum number of netlists returned by the precise synthesis solver n.

[0094] After each partition obtains a series of netlists returned by the precise synthesis solver, it will try to replace the local netlists in the original partition one by one with the returned netlists. The benefit is the number of nodes that can be reduced after the replacement. The benefit of a partition is the largest benefit among all replacements. Since a node contains multiple partitions, the precise solver based on each partition does not depend on each other. Therefore, the precise solution of multiple partitions of a node can be added to the multi-threaded execution to increase the running efficiency exponentially. In addition, if a replacement increases the number of logical levels of the local netlist, then even if there is a benefit for the replacement, the benefit of the replacement will be artificially changed to -1. If all replacements cannot bring positive benefits or the solver fails to return any netlist for replacement within a unit time, then the benefit of the partition is 0, and the corresponding netlist for replacement is itself. Each node will retain at most p partitions with benefits greater than 0. If the number of partitions exceeds p, they will be retained in descending order of benefits. The logic level calculation method of this embodiment is as follows: 1. The logic level of each node is equal to the maximum logic level of all its inputs plus one; 2. The logic level of the divided input signal is 0. Figure 5 For example, the logic level of input signals I0, I1, I2, I3, I4, and I5 is 0, the logic level of nodes 3, 4, and 5 is 1, the logic level of nodes 1 and 2 is 2, and the logic level of node 0 is 3.

[0095] Figure 6 Shows Figure 5 The corresponding node replacement diagram, assuming there is a replacement such as Figure 6 As shown, if all node logics are AND logic, then Figure 5 and Figure 6 The Boolean functions expressed are the same, all f=I0·I1·I2·I3·I4·I5. Obviously, Figure 6 The node ratio in Figure 5 The number of nodes in is reduced by 1, and the replacement benefit is 1. Figure 6 The logical level is 5, which is greater than Figure 5 The logic level of the replacement is increased, so the benefit of the replacement will be set to -1 and will not be considered. That is, in this embodiment, when trying to replace, the Boolean function of the local netlist is replaced with the netlist returned by the solver, and the optimization benefit after the replacement is calculated (the optimization benefit is the number of nodes reduced). If the logic level increases after the replacement, the benefit is set to -1. If all replacements have no positive benefits or do not return a netlist, the benefit is set to 0. Then, the first p partitions of each node with a benefit greater than 0 are retained.

[0096] Step S304, optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimal partitioning, and obtaining the target two-input combinational logic gate netlist after optimization and replacement.

[0097] In an optional implementation, step S304 includes:

[0098] Based on the optimal partition corresponding to each node, construct a benefit graph of the target two-input combinational logic gate netlist;

[0099] Add the highest benefit of the best partition corresponding to each node to the corresponding node of the benefit graph, and calculate the maximum weighted independent set of the benefit graph;

[0100] According to the result of the maximum weighted independent set, the partition corresponding to each node in the target two-input combinational logic gate netlist is replaced with the netlist with the highest benefit to obtain the target two-input combinational logic gate netlist after optimization and replacement.

[0101] Furthermore, this embodiment first constructs a benefit graph based on the optimal partition corresponding to each node. The benefit graph is used to record the optimization benefits that each node can obtain through the optimal partition. The nodes of the benefit graph represent the nodes in the logic gate netlist, and the weights of the edges represent the optimization benefits brought by the optimal partition. When constructing the benefit graph, each node is associated with the highest benefit of its optimal partition. Next, the maximum weighted independent set of this benefit graph is calculated (the independent set is a set of nodes that are not connected by edges, and the maximum weighted independent set is the one with the largest sum of weights among all independent sets), that is, the maximum weighted independent set refers to a set of nodes selected in the benefit graph, there is no direct dependency relationship between these nodes (that is, no loop is formed), and the sum of the benefits of these nodes is the largest. Finally, according to the result of the maximum weighted independent set, each node in the target two-input combinational logic gate netlist is replaced, that is, the partition corresponding to each node is replaced with the netlist with the highest corresponding benefit in the benefit graph. Since each replaced node is selected based on its optimal partition, and these optimal partitions form the maximum weighted independent set in the benefit graph, the replacement ensures that the optimization benefit of the overall netlist is maximized. After the replacement is completed, the replaced target two-input combinational logic gate netlist can be optimized. The replaced netlist is logically equivalent to the original netlist, but is more concise in structure and has fewer nodes.

[0102] Furthermore, after obtaining the highest-benefit partitions corresponding to all nodes and their corresponding replacement netlists, this embodiment enters the optimization replacement phase. This phase is to replace the partitions corresponding to the nodes with their corresponding netlists with the highest benefits. There are intersections between the partitions corresponding to different nodes. If a partition is replaced, some nodes may no longer exist. Therefore, not every partition corresponding to each node can be replaced. To address this issue, this embodiment constructs a benefit graph based on the partitions of the nodes. The nodes in this benefit graph are the nodes in the input netlist, and the edges are the connection relationships between the two nodes. This embodiment defines the edges as follows: if there is an edge between two nodes, then the areas covered by the partitions of the two nodes (the area from the root node to the input signal, including the root node but not including the input signal, the root node is the node on which the partition generation is based, such as the partition of node 1, then the root node is node 1) have an intersection. In the process of optimization replacement, only one of the partitions with intersections can be selected for replacement. Figure 5 For example, suppose the partitions with the largest benefits corresponding to nodes 0, 1, 2, 3, 4, and 5 are: {node 1, node 2}, {I0, I1, I2, I3}, {I2, I3, I4, I5}, {I0, I1}, {I2, I3}, {I4, I5}. Then obviously, the areas covered by the partitions of nodes 1 and 2 have an intersection of node 4, the areas covered by the partitions of nodes 1 and 3 and 4 have an intersection of node 3 and node 4, and the areas covered by the partitions of nodes 2 and 4 and 5 have an intersection of node 4 and node 5. Thus, the benefits graph can be obtained as follows Figure 7 As shown in the left half of Figure 7 Shows Figure 5 The corresponding node benefit graph, and then add the benefits to each node. Assume that the maximum benefit of the partition corresponding to each node is as follows Figure 7 The right half of the seed is shown. Thus, a complete benefit graph is obtained. This embodiment expects to maximize the benefit after completing all optimization substitutions, which can be achieved through the maximum weighted independent set. In other words, the nodes of the benefit graph are the nodes in the input netlist, the edges represent the intersection of the partitioned areas between the nodes, and the weight of each node is the maximum benefit of its corresponding partition. The graph algorithm can be applied to find the maximum weighted independent set to ensure that the total benefit after optimization substitution is maximized.

[0103] Step S305 , calculating a simulation truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and replacement.

[0104] In an optional implementation, the step S305 includes:

[0105] Traversing all nodes in the target two-input combinational logic gate netlist after optimization and substitution, and generating a corresponding optimization window for each traversed node;

[0106] Within the optimization window, a simulation truth table of the corresponding node is generated based on the logic function and input signal of each node.

[0107] Furthermore, after optimization and substitution, the present embodiment calculates a corresponding analog truth table for each node in the target two-input combinational logic gate netlist. The analog truth table is a table that lists all possible input combinations and their corresponding outputs to verify the correctness of the logic function. The present embodiment first needs to traverse all nodes in the logic gate netlist after optimization and substitution to ensure that each node is taken into account. For each traversed node, an optimization window is generated. The optimization window refers to the set of input signals related to the logic function of the corresponding node and other nodes that affect the output of the node. Within the optimization window, the present embodiment generates a corresponding analog truth table based on the logic function and input signal of each node, that is, by enumerating all possible input combinations and calculating the corresponding output results based on the logic function of the node.

[0108] Furthermore, after the optimization replacement is completed, the optimization phase based on precise synthesis ends, and then the redundant logic elimination phase is entered. The optimization based on precise synthesis only works on the area covered by the smaller partitions, and since only one of the partitions with intersecting coverage can be optimized and replaced, there may still be some redundant logic that has not been eliminated after the optimization phase based on precise synthesis. Please refer to Figure 8 The flowchart of the redundant logic elimination link is shown in FIG. Figure 8 As shown, the netlist nodes are traversed for the input netlist, an optimization window is generated based on the traversed nodes, and then a simulation truth table is generated based on the optimization window locally. The nodes with the same simulation truth table are redundant nodes. That is to say, after completing the optimization substitution, this embodiment first reads the netlist after optimization substitution, obtains the information of all nodes in the netlist, and for each traversed node, generates an optimization window based on the node, and the optimization window includes the node and all directly connected nodes. The local netlist of the optimization window is extracted from the netlist for subsequent redundancy detection and truth table generation. For the local netlist of the optimization window, this embodiment generates its corresponding truth table. The truth table includes all possible input combinations and records the output results under each input combination. After that, the truth tables of each node are compared to identify the nodes with exactly the same truth tables, i.e., redundant nodes.

[0109] Step S306 , based on the simulation truth table, clear the redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement, and obtain the optimized final two-input combinational logic gate netlist.

[0110] In an optional implementation, step S306 includes:

[0111] Based on the simulated truth table of each node, identifying the redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement;

[0112] Calculate the maximum fan-out-free cone for each redundant node;

[0113] Based on the maximum fan-out-free cone, redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared, and the optimized final two-input combinational logic gate netlist is obtained.

[0114] Furthermore, this embodiment calculates the maximum fan-out cone for each identified redundant node. The fan-out cone refers to a node and the set of all its child nodes that are not used by subsequent circuits. The maximum fan-out cone is the case where this set contains the most nodes, that is, the set of nodes where the current node or the corresponding node has no output to other nodes. The purpose of calculating the maximum fan-out cone is to determine which related and no longer needed nodes can be removed together when removing redundant nodes, so as to optimize the circuit more thoroughly. Based on the calculated maximum fan-out cone, this embodiment removes these redundant nodes and their child nodes from the optimized and replaced two-input combinational logic gate netlist, and after removing the redundant nodes, reorganizes the remaining nodes and connections to generate a more concise and efficient optimized final two-input combinational logic gate netlist.

[0115] Furthermore, after finding a series of redundant nodes, this embodiment clears the redundant nodes and their corresponding MFFCs based on the size of MFFC (Maximum Fanout FreeCone, i.e., maximum fan-out cone) (when the truth tables are the same, the node with the smallest MFFC is retained, and other nodes with the same truth tables and their corresponding MFFCs are deleted). After all nodes are traversed, the optimized two-input combinational logic netlist can be obtained. For a general combinational logic gate netlist, there are 16 different logic gates, each representing a different Boolean logic. This embodiment constructs its logic truth table for different logics, and performs simulation truth table calculation based on the constructed truth table. For example, the logic truth value of a node shown in Table 1, when the input is 1001 and 1100 respectively, the simulated truth table obtained is 0111.

[0116] Table 1

[0117]

[0118] The MFFC of this embodiment can refer to Fig. 9 Describe, Fig. 9Another structural diagram of a combinational logic gate netlist is shown in FIG. An MFFC consists of a root node and all its transitive fan-in nodes without external fan-out (a transitive fan-in node is a node that has a path with the root node). Fig. 9 Taking node 3 in as an example, all its transitive fan-in nodes are node 6, node 9 and node 0. However, node 9 has an external fan-out to node 5 (external fan-out means that the fan-out node is not the transitive fan-in of the root node), so node 9 is not counted in the MFFC with node 3 as the root node. The MFFC with node 3 as the root node is: {node 3, node 6, node 0}. Similarly, if the MFFC with node 2 as the root node is: {node 2, node 4, node 5, node 8, node 7}. That is to say, for each redundant node, this embodiment calculates the maximum fan-out free area of ​​its node, and for the redundant nodes with the same truth table, retains the node with the smallest MFFC, and deletes other nodes with the same truth table and their corresponding MFFC, thereby deleting the redundant node and its corresponding MFFC from the original netlist, updating the netlist, and deleting the cleared nodes and connections.

[0119] In summary, the present invention can accurately evaluate the contribution of each partition to the overall circuit optimization, i.e., the optimization benefit, by traversing each node in the target two-input combinational logic gate netlist and generating a corresponding partition set for each node. Based on these optimization benefits, the optimal partition is selected for replacement, thereby ensuring that each replacement can bring optimization effect. After the optimization replacement, the redundant nodes can be accurately identified by calculating the analog truth table of each node. Subsequently, the redundant nodes are removed, which not only reduces the complexity and power consumption of the circuit, but also improves the stability and reliability of the circuit. In addition, the present invention decomposes a large-scale netlist into multiple partitions through a partitioning strategy, and accurately synthesizes each subnetlist or partition, so that the accurate synthesis can be applied to a larger-scale netlist while maintaining a high optimization effect. Based on the verification of the accurate synthesis strategy and the analog truth table, it can ensure that the optimized circuit is completely consistent with the original circuit in function, while reducing redundancy and unnecessary complexity.

[0120] In addition, the netlist obtained by the present invention based on precise synthesis can ensure the optimal number of nodes in the local netlist, so its optimization effect for some relatively small netlists is far better than some heuristic logic synthesis methods. Furthermore, by partitioning, precise synthesis can be applied to large-scale netlists, and by eliminating redundant logic, the optimization scope is expanded as much as possible with less additional time consumption, thereby improving the optimization effect.

[0121] In this embodiment, a logic synthesis device based on precise synthesis is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0122] This embodiment provides a logic synthesis device based on precise synthesis, such as Fig.10 As shown, including:

[0123] The netlist input module 1001 is used to obtain a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized;

[0124] A partition set acquisition module 1002 is used to traverse each node in the target two-input combinational logic gate netlist and generate a corresponding partition set for each node during the traversal process;

[0125] A partition optimization replacement module 1003 is used to optimize and replace corresponding nodes in the target two-input combinational logic gate netlist based on the optimization benefit of each partition in the partition set, and obtain the target two-input combinational logic gate netlist after optimization and replacement;

[0126] A simulation truth table acquisition module 1004 is used to calculate a simulation truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and replacement;

[0127] The netlist output module 1005 is used to clear redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement based on the simulation truth table, and obtain the optimized final two-input combinational logic gate netlist.

[0128] In some optional implementations, the target two-input combinational logic gate netlist includes nodes and edges, and the node is a two-input combinational logic node.

[0129] In some optional implementations, the partition set acquisition module 1002 is further used to:

[0130] Traverse each node in the target two-input combinational logic gate netlist in topologically sorted order;

[0131] For each node, a corresponding partition set is generated according to the input signal of each node.

[0132] In some optional implementations, the partition optimization substitution module 1003 is further used to:

[0133] For each node, calculate the optimization benefit of each partition in the partition set, and select the target number of partitions with the highest optimization benefit as the best partition for the corresponding node;

[0134] Based on the optimal partition, corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained.

[0135] In some optional implementations, the partition optimization substitution module 1003 is further used to:

[0136] For each partition in the partition set of each node, generating a Boolean function of a local netlist corresponding to each partition based on an input signal and an output signal of each partition;

[0137] Performing multi-threaded solving of the Boolean function by using an accurate synthesis solver, and obtaining a series of netlists returned by the accurate synthesis solver;

[0138] Replace the Boolean function of the local netlist corresponding to each partition with a series of netlists returned by the exact synthesis solver, and calculate the optimization benefit after the replacement; the optimization benefit is the number of nodes reduced by the partition;

[0139] In this partition set, the partitions with the highest optimization benefits before the target number are retained as the best partitions for the corresponding nodes.

[0140] In some optional implementations, the partition optimization substitution module 1003 is further used to:

[0141] Based on the optimal partition corresponding to each node, construct a benefit graph of the target two-input combinational logic gate netlist;

[0142] Add the highest benefit of the best partition corresponding to each node to the corresponding node of the benefit graph, and calculate the maximum weighted independent set of the benefit graph;

[0143] According to the result of the maximum weighted independent set, the partition corresponding to each node in the target two-input combinational logic gate netlist is replaced with the netlist with the highest benefit to obtain the target two-input combinational logic gate netlist after optimization and replacement.

[0144] In some optional implementations, the simulation truth table acquisition module 1004 is further used to:

[0145] Traversing all nodes in the target two-input combinational logic gate netlist after optimization and substitution, and generating a corresponding optimization window for each traversed node;

[0146] Within the optimization window, a simulation truth table of the corresponding node is generated based on the logic function and input signal of each node.

[0147] In some optional implementations, the netlist output module 1005 is further used to:

[0148] Based on the simulated truth table of each node, identifying the redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement;

[0149] Calculate the maximum fan-out-free cone for each redundant node;

[0150] Based on the maximum fan-out-free cone, redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared, and the optimized final two-input combinational logic gate netlist is obtained.

[0151] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0152] In this embodiment, a logic synthesis device based on precise synthesis is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0153] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.11 As shown, the computer device includes: one or more processors 1110, memory 1120, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component utilizes different buses to communicate with each other, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 1110 is taken as an example.

[0154] The processor 1110 may be a central processing unit, a network processor or a combination thereof. The processor 1110 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable logic gate array, a general purpose array logic or any combination thereof.

[0155] The memory 1120 stores instructions executable by at least one processor 1110 so that the at least one processor 1110 executes the method shown in the above embodiment.

[0156] The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 1120 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 1120 may optionally include a memory remotely arranged relative to the processor 1110, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0157] The memory 1120 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 1120 may also include a combination of the above types of memory.

[0158] The computer device also includes a communication interface 1130 for the computer device to communicate with other devices or a communication network.

[0159] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0160] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0161] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. A logic synthesis method based on precise synthesis, characterized in that: The method comprises: Obtaining a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized; Traversing each node in the target two-input combinational logic gate netlist, and generating a corresponding partition set for each node during the traversal process; Based on the optimization benefit of each partition in the partition set, the corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained; the optimization benefit is used to indicate the number of nodes reduced after the corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced; Calculate the analog truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and substitution; Based on the simulation truth table, the redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared, and the optimized final two-input combinational logic gate netlist is obtained; the redundant nodes are the same nodes as the simulation truth table.

2. The method according to claim 1, characterized in that The target two-input combinational logic gate netlist includes nodes and edges, and the nodes are two-input combinational logic nodes.

3. The method according to claim 1, characterized in that The traversing each node in the target two-input combinational logic gate netlist and generating a corresponding partition set for each node during the traversal process includes: Traverse each node in the target two-input combinational logic gate netlist in a topologically sorted order; For each of the nodes, a corresponding partition set is generated according to an input signal of each of the nodes.

4. The method according to claim 1, characterized in that: The step of optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimization benefit of each partition in the partition set, and obtaining the target two-input combinational logic gate netlist after optimization and replacement includes: For each node, calculating the optimization benefit of each partition in the partition set, and selecting the target number of partitions with the highest optimization benefits as the best partitions for the corresponding node; Based on the optimal partition, corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced, and the target two-input combinational logic gate netlist after optimization and replacement is obtained.

5. The method according to claim 4, characterized in that For each node, calculating the optimization benefit of each partition in the partition set, and selecting a target number of partitions with the highest optimization benefits as the best partitions for the corresponding node, including: For each partition in the partition set of each node, generating a Boolean function of a local netlist corresponding to each partition based on an input signal and an output signal of each partition; Performing multi-threaded solving of the Boolean function by using an accurate synthesis solver, and obtaining a series of netlists returned by the accurate synthesis solver; Replacing the Boolean functions of the local netlists corresponding to each partition with a series of netlists returned by the precise synthesis solver, and calculating the optimization benefit after the replacement; the optimization benefit is the number of nodes reduced by the partition; In the partition set, the partitions with the highest optimization benefits before the target number are retained as the best partitions for the corresponding nodes.

6. The method according to claim 4, characterized in that The step of optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimal partitioning, and obtaining the target two-input combinational logic gate netlist after optimization and replacement, includes: Based on the optimal partition corresponding to each node, construct a benefit graph of the target two-input combinational logic gate netlist; Adding the highest benefit of the best partition corresponding to each node to the corresponding node of the benefit graph, and calculating the maximum weighted independent set of the benefit graph; According to the result of the maximum weighted independent set, the partition corresponding to each node in the target two-input combinational logic gate netlist is replaced with the netlist with the highest benefit to obtain the target two-input combinational logic gate netlist after optimization and replacement.

7. The method according to any one of claims 1 to 6, characterized in that: The analog truth table corresponding to each node in the target two-input combinational logic gate netlist after the calculation optimization substitution includes: Traversing all nodes in the target two-input combinational logic gate netlist after optimization and replacement, and generating a corresponding optimization window for each traversed node; Within the optimization window, a simulation truth table of a corresponding node is generated based on the logic function and input signal of each node.

8. The method according to any one of claims 1 to 6, characterized in that: The step of removing redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement based on the simulation truth table, and obtaining the optimized final two-input combinational logic gate netlist, includes: Based on the simulated truth table of each node, identifying redundant nodes in the target two-input combinational logic gate netlist after optimized replacement; Calculate the maximum fan-out-free cone for each redundant node; The redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement are cleared based on the maximum no-fan-out cone, and the optimized final two-input combinational logic gate netlist is obtained.

9. A logic synthesis device based on precise synthesis, characterized in that: The device comprises: A netlist input module, used to obtain a target two-input combinational logic gate netlist; the target two-input combinational logic gate netlist is used to indicate a digital circuit to be optimized; A partition set acquisition module, used for traversing each node in the target two-input combinational logic gate netlist, and generating a corresponding partition set for each node during the traversal process; A partition optimization replacement module, used for optimizing and replacing corresponding nodes in the target two-input combinational logic gate netlist based on the optimization benefit of each partition in the partition set, and obtaining the target two-input combinational logic gate netlist after optimization and replacement; the optimization benefit is used to indicate the number of nodes reduced after the corresponding nodes in the target two-input combinational logic gate netlist are optimized and replaced; A simulation truth table acquisition module, used for calculating the simulation truth table corresponding to each node in the target two-input combinational logic gate netlist after optimization and replacement; A netlist output module is used to clear redundant nodes in the target two-input combinational logic gate netlist after optimization and replacement based on the simulation truth table, and obtain the optimized final two-input combinational logic gate netlist; the redundant nodes are the same nodes as the simulation truth table.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a logic synthesis method based on precise synthesis according to any one of claims 1 to 8 by executing the computer instructions.

Images